Module Definition
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Module : flash_ctrl_prog
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.17 100.00 97.06 94.44

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_prog.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_flash_ctrl_prog 97.17 100.00 97.06 94.44



Module Instance : tb.dut.u_flash_ctrl_prog

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.17 100.00 97.06 94.44


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.88 100.00 97.06 100.00 94.44


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.69 97.12 93.60 98.44 100.00 84.29 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_cnt 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : flash_ctrl_prog
Line No.TotalCoveredPercent
TOTAL5454100.00
ALWAYS5533100.00
ALWAYS9044100.00
CONT_ASSIGN9711100.00
CONT_ASSIGN9811100.00
ALWAYS10155100.00
CONT_ASSIGN11211100.00
CONT_ASSIGN12211100.00
CONT_ASSIGN12311100.00
CONT_ASSIGN12411100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN12611100.00
ALWAYS1322626100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18511100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
CONT_ASSIGN19311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_prog.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 1 1
56 1 1
58 1 1
90 1 1
91 1 1
92 1 1
93 1 1
MISSING_ELSE
97 1 1
98 1 1
101 1 1
102 1 1
103 1 1
104 1 1
106 1 1
112 1 1
122 1 1
123 1 1
124 1 1
125 1 1
126 1 1
132 1 1
133 1 1
134 1 1
135 1 1
136 1 1
138 1 1
144 1 1
146 1 1
148 1 1
150 1 1
152 1 1
153 1 1
154 1 1
155 1 1
157 1 1
158 1 1
160 1 1
MISSING_ELSE
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
MISSING_ELSE
172 1 1
174 1 1
175 1 1
176 1 1
MISSING_ELSE
183 1 1
184 1 1
185 1 1
186 1 1
187 1 1
188 1 1
189 1 1
193 1 1


Cond Coverage for Module : flash_ctrl_prog
TotalCoveredPercent
Conditions343397.06
Logical343397.06
Non-Logical00
Event00

 LINE       74
 EXPRESSION (op_start_i && op_done_o)
             -----1----    ----2----
-1--2-StatusTests
01CoveredT180,T138,T185
10CoveredT1,T17,T18
11CoveredT1,T17,T18

 LINE       92
 EXPRESSION (((~|op_err_q)) && ((|op_err_d)))
             -------1------    ------2------
-1--2-StatusTests
01CoveredT18,T5,T25
10CoveredT1,T2,T3
11CoveredT18,T5,T25

 LINE       97
 EXPRESSION (flash_req_o && flash_done_i)
             -----1-----    ------2-----
-1--2-StatusTests
01CoveredT2,T4,T16
10CoveredT1,T17,T18
11CoveredT1,T17,T18

 LINE       103
 EXPRESSION (op_start_i && op_done_o)
             -----1----    ----2----
-1--2-StatusTests
01CoveredT180,T138,T185
10CoveredT1,T17,T18
11CoveredT1,T17,T18

 LINE       125
 EXPRESSION (start_window != end_window)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T16

 LINE       126
 EXPRESSION (pgm_res_err | op_addr_oob_i)
             -----1-----   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT2,T4,T16

 LINE       148
 EXPRESSION (op_start_i && prog_type_avail && ((!win_err)))
             -----1----    -------2-------    ------3-----
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT76,T77,T78
110CoveredT197,T198,T199
111CoveredT1,T17,T18

 LINE       160
 EXPRESSION (((|op_err_d)) ? StErr : StNorm)
             ------1------
-1-StatusTests
0CoveredT1,T17,T18
1CoveredT18,T5,T25

 LINE       164
 EXPRESSION (op_start_i && (((!prog_type_avail)) || win_err))
             -----1----    ----------------2----------------
-1--2-StatusTests
01CoveredT2,T4,T16
10Not Covered
11CoveredT76,T197,T198

 LINE       164
 SUB-EXPRESSION (((!prog_type_avail)) || win_err)
                 ----------1---------    ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T4,T16
10CoveredT76,T77,T78

 LINE       174
 EXPRESSION (data_rdy_i && cnt_hit)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT18,T5,T25
10CoveredT18,T5,T56
11CoveredT18,T5,T25

 LINE       187
 EXPRESSION (flash_req_o & cnt_hit)
             -----1-----   ---2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T17,T18
11CoveredT1,T17,T18

Branch Coverage for Module : flash_ctrl_prog
Line No.TotalCoveredPercent
Branches 18 17 94.44
IF 55 2 2 100.00
IF 90 3 3 100.00
IF 101 3 3 100.00
CASE 138 10 9 90.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 55 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 90 if ((!rst_ni)) -2-: 92 if (((~|op_err_q) && (|op_err_d)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T18,T5,T25
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 101 if ((!rst_ni)) -2-: 103 if ((op_start_i && op_done_o))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T17,T18
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 138 case (st_q) -2-: 144 if (cnt_err_o) -3-: 148 if (((op_start_i && prog_type_avail) && (!win_err))) -4-: 152 if (txn_done) -5-: 157 if (cnt_hit) -6-: 160 ((|op_err_d)) ? -7-: 164 if ((op_start_i && ((!prog_type_avail) || win_err))) -8-: 174 if ((data_rdy_i && cnt_hit))

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StNorm 1 - - - - - - Covered T12,T13,T14
StNorm 0 1 1 1 - - - Covered T1,T17,T18
StNorm 0 1 1 0 1 - - Covered T18,T5,T25
StNorm 0 1 1 0 0 - - Covered T1,T17,T18
StNorm 0 1 0 - - - - Covered T1,T17,T18
StNorm 0 0 - - - 1 - Covered T76,T197,T198
StNorm 0 0 - - - 0 - Covered T1,T2,T3
StErr - - - - - - 1 Covered T18,T5,T25
StErr - - - - - - 0 Covered T18,T5,T25
default - - - - - - - Not Covered

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%