Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	28312200	1		T1	102098		T2	120159		T3	84
full_word	7962530	1		T1	16335		T2	25045		T3	54

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	36274450	1		T1	118433		T2	145204		T3	138
auto[TlIntgErrCmd]	76	1		T103	6		T104	4		T105	6
auto[TlIntgErrData]	97	1		T103	5		T104	4		T105	3
auto[TlIntgErrBoth]	107	1		T103	9		T104	2		T105	11

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31709240	1		T1	106217		T2	128591		T3	58
auto[1]	4565490	1		T1	12216		T2	16613		T3	80

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	27566730	1		T1	100523		T2	118919		T3	57
auto[TlIntgErrNone]	partial	auto[1]	745220	1		T1	1575		T2	1240		T3	27
auto[TlIntgErrNone]	full_word	auto[0]	4142380	1		T1	5694		T2	9672		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	3820120	1		T1	10641		T2	15373		T3	53
auto[TlIntgErrCmd]	partial	auto[0]	32	1		T103	4		T104	1		T105	4
auto[TlIntgErrCmd]	partial	auto[1]	38	1		T103	2		T104	3		T105	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T308	1		T354	1		T355	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T283	1		T354	1		T355	1
auto[TlIntgErrData]	partial	auto[0]	43	1		T103	4		T105	1		T248	2
auto[TlIntgErrData]	partial	auto[1]	40	1		T103	1		T104	3		T105	2
auto[TlIntgErrData]	full_word	auto[0]	6	1		T281	1		T308	1		T353	1
auto[TlIntgErrData]	full_word	auto[1]	8	1		T104	1		T249	1		T281	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1		T103	5		T104	1		T105	4
auto[TlIntgErrBoth]	partial	auto[1]	56	1		T103	4		T104	1		T105	5
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T105	1		T249	1		T274	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T105	1		T274	1		T281	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	19721	1		T103	19		T106	392		T107	1182
full_word	3663351	1		T7	16957		T6	5		T8	8779

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3682808	1		T7	16957		T6	5		T8	8779
auto[TlIntgErrCmd]	86	1		T103	8		T104	3		T105	6
auto[TlIntgErrData]	93	1		T103	5		T104	5		T105	6
auto[TlIntgErrBoth]	85	1		T103	6		T104	2		T105	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3657122	1		T7	16957		T6	5		T8	8779
auto[1]	25950	1		T103	15		T106	524		T107	1522

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1338	1		T106	50		T107	119		T208	73
auto[TlIntgErrNone]	partial	auto[1]	18139	1		T106	342		T107	1063		T208	1067
auto[TlIntgErrNone]	full_word	auto[0]	3655688	1		T7	16957		T6	5		T8	8779
auto[TlIntgErrNone]	full_word	auto[1]	7643	1		T106	182		T107	459		T208	313
auto[TlIntgErrCmd]	partial	auto[0]	25	1		T103	1		T104	2		T105	4
auto[TlIntgErrCmd]	partial	auto[1]	55	1		T103	7		T104	1		T105	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T283	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T274	1		T281	1		T350	1
auto[TlIntgErrData]	partial	auto[0]	41	1		T103	1		T104	2		T105	3
auto[TlIntgErrData]	partial	auto[1]	43	1		T103	4		T104	3		T105	3
auto[TlIntgErrData]	full_word	auto[0]	3	1		T274	1		T308	1		T356	1
auto[TlIntgErrData]	full_word	auto[1]	6	1		T281	1		T357	1		T350	1
auto[TlIntgErrBoth]	partial	auto[0]	23	1		T103	2		T104	1		T105	4
auto[TlIntgErrBoth]	partial	auto[1]	57	1		T103	4		T104	1		T105	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T105	1		T352	2		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T274	1		T283	1		-	-