Unified Coverage Report :: Module :: flash_ctrl_arb

Module : flash_ctrl_arb

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_arb.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_ctrl_arb	100.00	100.00	100.00		100.00	100.00	100.00

---

Module Instance : tb.dut.u_ctrl_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.85	97.12	94.40	98.44		100.00	84.29	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : flash_ctrl_arb

	Line No.	Total	Covered	Percent
TOTAL		66	66	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	3	3	100.00
ALWAYS	127	22	22	100.00
ALWAYS	194	25	25	100.00
ALWAYS	240	13	13	100.00
CONT_ASSIGN	275	1	1	100.00
CONT_ASSIGN	278	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_arb.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
120	1	1
123	3	3
127	1	1
128	1	1
129	1	1
130	1	1
132	1	1
136	1	1
139	1	1
			MISSING_ELSE
144	1	1
146	1	1
147	1	1
			MISSING_ELSE
153	1	1
155	1	1
158	1	1
159	1	1
162	1	1
163	1	1
164	1	1
165	1	1
			MISSING_ELSE
170	1	1
174	1	1
175	1	1
			MISSING_ELSE
180	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
202	1	1
203	1	1
204	1	1
206	1	1
209	1	1
210	1	1
211	1	1
212	1	1
215	1	1
216	1	1
217	1	1
223	1	1
224	1	1
225	1	1
226	1	1
229	1	1
230	1	1
231	1	1
240	1	1
241	1	1
242	1	1
244	1	1
246	1	1
247	1	1
248	1	1
252	1	1
253	1	1
254	1	1
258	1	1
259	1	1
260	1	1
			MISSING_ELSE
275	1	1
278	1	1

---

Cond Coverage for Module : flash_ctrl_arb

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       174
 EXPRESSION (prog_ack_i || rd_ack_i || erase_ack_i)
             -----1----    ----2---    -----3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	1	0	Covered	T1,T2,T4
1	0	0	Covered	T1,T2,T4

 LINE       278
 EXPRESSION ((func_sel == SwSel) ? PhaseInvalid : hw_phase_i)
             ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       278
 SUB-EXPRESSION (func_sel == SwSel)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : flash_ctrl_arb

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	5	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StDisabled	158	Covered	T13,T14,T64
StHw	139	Covered	T1,T2,T3
StReset	133	Covered	T1,T2,T3
StSwActive	165	Covered	T1,T2,T4
StSwIdle	147	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StHw->StSwIdle	147	Covered	T1,T2,T3
StReset->StHw	139	Covered	T1,T2,T3
StSwActive->StSwIdle	175	Covered	T1,T2,T4
StSwIdle->StDisabled	158	Covered	T13,T14,T64
StSwIdle->StHw	163	Covered	T1,T2,T3
StSwIdle->StSwActive	165	Covered	T1,T2,T4

---

Branch Coverage for Module : flash_ctrl_arb

	Line No.	Total	Covered	Percent
Branches		24	24	100.00
TERNARY	278	2	2	100.00
IF	123	2	2	100.00
CASE	132	12	12	100.00
CASE	206	3	3	100.00
CASE	244	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_arb.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	278	((func_sel == SwSel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	132	case (state_q)
-2-:	136	if ((!flash_phy_busy_i))
-3-:	146	if ((!hw_req_i))
-4-:	155	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-5-:	159	if (hw_req_i)
-6-:	164	if (sw_req)
-7-:	174	if (((prog_ack_i || rd_ack_i) || erase_ack_i))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
StReset	1	-	-	-	-	-	Covered	T1,T2,T3
StReset	0	-	-	-	-	-	Covered	T1,T2,T3
StHw	-	1	-	-	-	-	Covered	T1,T2,T3
StHw	-	0	-	-	-	-	Covered	T1,T2,T3
StSwIdle	-	-	1	-	-	-	Covered	T13,T14,T64
StSwIdle	-	-	0	1	-	-	Covered	T1,T2,T3
StSwIdle	-	-	0	0	1	-	Covered	T1,T2,T4
StSwIdle	-	-	0	0	0	-	Covered	T1,T2,T3
StSwActive	-	-	-	-	-	1	Covered	T1,T2,T4
StSwActive	-	-	-	-	-	0	Covered	T1,T2,T4
StDisabled	-	-	-	-	-	-	Covered	T13,T14,T64
default	-	-	-	-	-	-	Covered	T15,T12,T16

	LineNo.	Expression
-1-:	206	case (func_sel)

Branches:

-1-	Status	Tests
HwSel	Covered	T1,T2,T3
SwSel	Covered	T1,T2,T3
default	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	244	case (muxed_ctrl_o.op.q)
-2-:	266	if (muxed_ctrl_o.start)

Branches:

-1-	-2-	Status	Tests
FlashOpProgram	-	Covered	T1,T2,T4
FlashOpErase	-	Covered	T1,T2,T4
FlashOpRead	-	Covered	T1,T2,T3
default	1	Covered	T230,T135,T153
default	0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_ctrl_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
u_state_regs_A	382045251	381153728	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045251	381153728	0	0
T1	265843	249942	0	0
T2	101581	101575	0	0
T3	2777	2715	0	0
T4	804469	804443	0	0
T5	144193	144097	0	0
T6	2817	2663	0	0
T7	68006	67818	0	0
T17	1202	1135	0	0
T18	1042	991	0	0
T19	190305	190295	0	0