Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T6,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T6,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T6,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T6,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T6,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T6,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T6,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T6,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T6,T8

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1528180632	1524614540	0	0
CheckNGreaterZero_A	4164	4164	0	0
GntImpliesReady_A	1528180632	411358151	0	0
GntImpliesValid_A	1528180632	411358151	0	0
GrantKnown_A	1528180632	1524614540	0	0
IdxKnown_A	1528180632	1524614540	0	0
IndexIsCorrect_A	1528180632	411358151	0	0
NoReadyValidNoGrant_A	1528180632	183508486	0	0
Priority_A	1528180632	434873507	0	0
ReadyAndValidImplyGrant_A	1528180632	411358151	0	0
ReqAndReadyImplyGrant_A	1528180632	411358151	0	0
ReqImpliesValid_A	1528180632	434873507	0	0
ValidKnown_A	1528180632	1524614540	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1528180632	1524614540	0	0
T1	1063372	999768	0	0
T2	406324	406300	0	0
T3	11108	10860	0	0
T4	3217876	3217772	0	0
T5	576772	576388	0	0
T6	11268	10652	0	0
T7	272024	271272	0	0
T17	4808	4540	0	0
T18	4168	3964	0	0
T19	761220	761180	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4164	4164	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1528180632	411358151	0	0
T1	531686	329232	0	0
T2	406324	1436738	0	0
T3	11108	64	0	0
T4	3217876	1089042	0	0
T5	576772	2632	0	0
T6	11268	520	0	0
T7	272024	46904	0	0
T8	0	20416	0	0
T9	0	21092	0	0
T17	4808	64	0	0
T18	4168	64	0	0
T19	761220	1556936	0	0
T24	0	150936	0	0
T47	759044	0	0	0
T59	0	419882	0	0
T64	0	255794	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1528180632	411358151	0	0
T1	531686	329232	0	0
T2	406324	1436738	0	0
T3	11108	64	0	0
T4	3217876	1089042	0	0
T5	576772	2632	0	0
T6	11268	520	0	0
T7	272024	46904	0	0
T8	0	20416	0	0
T9	0	21092	0	0
T17	4808	64	0	0
T18	4168	64	0	0
T19	761220	1556936	0	0
T24	0	150936	0	0
T47	759044	0	0	0
T59	0	419882	0	0
T64	0	255794	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1528180632	1524614540	0	0
T1	1063372	999768	0	0
T2	406324	406300	0	0
T3	11108	10860	0	0
T4	3217876	3217772	0	0
T5	576772	576388	0	0
T6	11268	10652	0	0
T7	272024	271272	0	0
T17	4808	4540	0	0
T18	4168	3964	0	0
T19	761220	761180	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1528180632	1524614540	0	0
T1	1063372	999768	0	0
T2	406324	406300	0	0
T3	11108	10860	0	0
T4	3217876	3217772	0	0
T5	576772	576388	0	0
T6	11268	10652	0	0
T7	272024	271272	0	0
T17	4808	4540	0	0
T18	4168	3964	0	0
T19	761220	761180	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1528180632	411358151	0	0
T1	531686	329232	0	0
T2	406324	1436738	0	0
T3	11108	64	0	0
T4	3217876	1089042	0	0
T5	576772	2632	0	0
T6	11268	520	0	0
T7	272024	46904	0	0
T8	0	20416	0	0
T9	0	21092	0	0
T17	4808	64	0	0
T18	4168	64	0	0
T19	761220	1556936	0	0
T24	0	150936	0	0
T47	759044	0	0	0
T59	0	419882	0	0
T64	0	255794	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1528180632	183508486	0	0
T1	531686	79064	0	0
T2	406324	16202	0	0
T3	11108	256	0	0
T4	3217876	425034	0	0
T5	576772	5376	0	0
T6	11268	780	0	0
T7	272024	129828	0	0
T8	0	58280	0	0
T9	0	28146	0	0
T17	4808	256	0	0
T18	4168	256	0	0
T19	761220	3392	0	0
T21	0	160	0	0
T31	0	964914	0	0
T47	759044	0	0	0
T59	0	1444	0	0
T64	0	1048576	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1528180632	434873507	0	0
T1	531686	329232	0	0
T2	406324	1436738	0	0
T3	11108	64	0	0
T4	3217876	1089042	0	0
T5	576772	2632	0	0
T6	11268	520	0	0
T7	272024	49788	0	0
T8	0	22314	0	0
T9	0	31398	0	0
T17	4808	64	0	0
T18	4168	64	0	0
T19	761220	1556936	0	0
T24	0	150936	0	0
T47	759044	0	0	0
T59	0	419882	0	0
T64	0	255794	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1528180632	411358151	0	0
T1	531686	329232	0	0
T2	406324	1436738	0	0
T3	11108	64	0	0
T4	3217876	1089042	0	0
T5	576772	2632	0	0
T6	11268	520	0	0
T7	272024	46904	0	0
T8	0	20416	0	0
T9	0	21092	0	0
T17	4808	64	0	0
T18	4168	64	0	0
T19	761220	1556936	0	0
T24	0	150936	0	0
T47	759044	0	0	0
T59	0	419882	0	0
T64	0	255794	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1528180632	411358151	0	0
T1	531686	329232	0	0
T2	406324	1436738	0	0
T3	11108	64	0	0
T4	3217876	1089042	0	0
T5	576772	2632	0	0
T6	11268	520	0	0
T7	272024	46904	0	0
T8	0	20416	0	0
T9	0	21092	0	0
T17	4808	64	0	0
T18	4168	64	0	0
T19	761220	1556936	0	0
T24	0	150936	0	0
T47	759044	0	0	0
T59	0	419882	0	0
T64	0	255794	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1528180632	434873507	0	0
T1	531686	329232	0	0
T2	406324	1436738	0	0
T3	11108	64	0	0
T4	3217876	1089042	0	0
T5	576772	2632	0	0
T6	11268	520	0	0
T7	272024	49788	0	0
T8	0	22314	0	0
T9	0	31398	0	0
T17	4808	64	0	0
T18	4168	64	0	0
T19	761220	1556936	0	0
T24	0	150936	0	0
T47	759044	0	0	0
T59	0	419882	0	0
T64	0	255794	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1528180632	1524614540	0	0
T1	1063372	999768	0	0
T2	406324	406300	0	0
T3	11108	10860	0	0
T4	3217876	3217772	0	0
T5	576772	576388	0	0
T6	11268	10652	0	0
T7	272024	271272	0	0
T17	4808	4540	0	0
T18	4168	3964	0	0
T19	761220	761180	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T6,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T6,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T6,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T6,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T6,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T6,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T6,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T6,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T6,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	382045158	381153635	0	0
CheckNGreaterZero_A	1041	1041	0	0
GntImpliesReady_A	382045158	105200946	0	0
GntImpliesValid_A	382045158	105200946	0	0
GrantKnown_A	382045158	381153635	0	0
IdxKnown_A	382045158	381153635	0	0
IndexIsCorrect_A	382045158	105200946	0	0
NoReadyValidNoGrant_A	382045158	47345726	0	0
Priority_A	382045158	111089434	0	0
ReadyAndValidImplyGrant_A	382045158	105200946	0	0
ReqAndReadyImplyGrant_A	382045158	105200946	0	0
ReqImpliesValid_A	382045158	111089434	0	0
ValidKnown_A	382045158	381153635	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	381153635	0	0
T1	265843	249942	0	0
T2	101581	101575	0	0
T3	2777	2715	0	0
T4	804469	804443	0	0
T5	144193	144097	0	0
T6	2817	2663	0	0
T7	68006	67818	0	0
T17	1202	1135	0	0
T18	1042	991	0	0
T19	190305	190295	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1041	1041	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	105200946	0	0
T1	265843	164616	0	0
T2	101581	5930	0	0
T3	2777	32	0	0
T4	804469	274908	0	0
T5	144193	1316	0	0
T6	2817	180	0	0
T7	68006	15174	0	0
T17	1202	32	0	0
T18	1042	32	0	0
T19	190305	121875	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	105200946	0	0
T1	265843	164616	0	0
T2	101581	5930	0	0
T3	2777	32	0	0
T4	804469	274908	0	0
T5	144193	1316	0	0
T6	2817	180	0	0
T7	68006	15174	0	0
T17	1202	32	0	0
T18	1042	32	0	0
T19	190305	121875	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	381153635	0	0
T1	265843	249942	0	0
T2	101581	101575	0	0
T3	2777	2715	0	0
T4	804469	804443	0	0
T5	144193	144097	0	0
T6	2817	2663	0	0
T7	68006	67818	0	0
T17	1202	1135	0	0
T18	1042	991	0	0
T19	190305	190295	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	381153635	0	0
T1	265843	249942	0	0
T2	101581	101575	0	0
T3	2777	2715	0	0
T4	804469	804443	0	0
T5	144193	144097	0	0
T6	2817	2663	0	0
T7	68006	67818	0	0
T17	1202	1135	0	0
T18	1042	991	0	0
T19	190305	190295	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	105200946	0	0
T1	265843	164616	0	0
T2	101581	5930	0	0
T3	2777	32	0	0
T4	804469	274908	0	0
T5	144193	1316	0	0
T6	2817	180	0	0
T7	68006	15174	0	0
T17	1202	32	0	0
T18	1042	32	0	0
T19	190305	121875	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	47345726	0	0
T1	265843	39532	0	0
T2	101581	2582	0	0
T3	2777	128	0	0
T4	804469	107353	0	0
T5	144193	2688	0	0
T6	2817	352	0	0
T7	68006	40348	0	0
T17	1202	128	0	0
T18	1042	128	0	0
T19	190305	1696	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	111089434	0	0
T1	265843	164616	0	0
T2	101581	5930	0	0
T3	2777	32	0	0
T4	804469	274908	0	0
T5	144193	1316	0	0
T6	2817	180	0	0
T7	68006	15534	0	0
T17	1202	32	0	0
T18	1042	32	0	0
T19	190305	121875	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	105200946	0	0
T1	265843	164616	0	0
T2	101581	5930	0	0
T3	2777	32	0	0
T4	804469	274908	0	0
T5	144193	1316	0	0
T6	2817	180	0	0
T7	68006	15174	0	0
T17	1202	32	0	0
T18	1042	32	0	0
T19	190305	121875	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	105200946	0	0
T1	265843	164616	0	0
T2	101581	5930	0	0
T3	2777	32	0	0
T4	804469	274908	0	0
T5	144193	1316	0	0
T6	2817	180	0	0
T7	68006	15174	0	0
T17	1202	32	0	0
T18	1042	32	0	0
T19	190305	121875	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	111089434	0	0
T1	265843	164616	0	0
T2	101581	5930	0	0
T3	2777	32	0	0
T4	804469	274908	0	0
T5	144193	1316	0	0
T6	2817	180	0	0
T7	68006	15534	0	0
T17	1202	32	0	0
T18	1042	32	0	0
T19	190305	121875	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	381153635	0	0
T1	265843	249942	0	0
T2	101581	101575	0	0
T3	2777	2715	0	0
T4	804469	804443	0	0
T5	144193	144097	0	0
T6	2817	2663	0	0
T7	68006	67818	0	0
T17	1202	1135	0	0
T18	1042	991	0	0
T19	190305	190295	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T6,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T6,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T6,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T6,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T6,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T6,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T6,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T6,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T6,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	382045158	381153635	0	0
CheckNGreaterZero_A	1041	1041	0	0
GntImpliesReady_A	382045158	105200946	0	0
GntImpliesValid_A	382045158	105200946	0	0
GrantKnown_A	382045158	381153635	0	0
IdxKnown_A	382045158	381153635	0	0
IndexIsCorrect_A	382045158	105200946	0	0
NoReadyValidNoGrant_A	382045158	47345726	0	0
Priority_A	382045158	111089434	0	0
ReadyAndValidImplyGrant_A	382045158	105200946	0	0
ReqAndReadyImplyGrant_A	382045158	105200946	0	0
ReqImpliesValid_A	382045158	111089434	0	0
ValidKnown_A	382045158	381153635	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	381153635	0	0
T1	265843	249942	0	0
T2	101581	101575	0	0
T3	2777	2715	0	0
T4	804469	804443	0	0
T5	144193	144097	0	0
T6	2817	2663	0	0
T7	68006	67818	0	0
T17	1202	1135	0	0
T18	1042	991	0	0
T19	190305	190295	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1041	1041	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	105200946	0	0
T1	265843	164616	0	0
T2	101581	5930	0	0
T3	2777	32	0	0
T4	804469	274908	0	0
T5	144193	1316	0	0
T6	2817	180	0	0
T7	68006	15174	0	0
T17	1202	32	0	0
T18	1042	32	0	0
T19	190305	121875	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	105200946	0	0
T1	265843	164616	0	0
T2	101581	5930	0	0
T3	2777	32	0	0
T4	804469	274908	0	0
T5	144193	1316	0	0
T6	2817	180	0	0
T7	68006	15174	0	0
T17	1202	32	0	0
T18	1042	32	0	0
T19	190305	121875	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	381153635	0	0
T1	265843	249942	0	0
T2	101581	101575	0	0
T3	2777	2715	0	0
T4	804469	804443	0	0
T5	144193	144097	0	0
T6	2817	2663	0	0
T7	68006	67818	0	0
T17	1202	1135	0	0
T18	1042	991	0	0
T19	190305	190295	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	381153635	0	0
T1	265843	249942	0	0
T2	101581	101575	0	0
T3	2777	2715	0	0
T4	804469	804443	0	0
T5	144193	144097	0	0
T6	2817	2663	0	0
T7	68006	67818	0	0
T17	1202	1135	0	0
T18	1042	991	0	0
T19	190305	190295	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	105200946	0	0
T1	265843	164616	0	0
T2	101581	5930	0	0
T3	2777	32	0	0
T4	804469	274908	0	0
T5	144193	1316	0	0
T6	2817	180	0	0
T7	68006	15174	0	0
T17	1202	32	0	0
T18	1042	32	0	0
T19	190305	121875	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	47345726	0	0
T1	265843	39532	0	0
T2	101581	2582	0	0
T3	2777	128	0	0
T4	804469	107353	0	0
T5	144193	2688	0	0
T6	2817	352	0	0
T7	68006	40348	0	0
T17	1202	128	0	0
T18	1042	128	0	0
T19	190305	1696	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	111089434	0	0
T1	265843	164616	0	0
T2	101581	5930	0	0
T3	2777	32	0	0
T4	804469	274908	0	0
T5	144193	1316	0	0
T6	2817	180	0	0
T7	68006	15534	0	0
T17	1202	32	0	0
T18	1042	32	0	0
T19	190305	121875	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	105200946	0	0
T1	265843	164616	0	0
T2	101581	5930	0	0
T3	2777	32	0	0
T4	804469	274908	0	0
T5	144193	1316	0	0
T6	2817	180	0	0
T7	68006	15174	0	0
T17	1202	32	0	0
T18	1042	32	0	0
T19	190305	121875	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	105200946	0	0
T1	265843	164616	0	0
T2	101581	5930	0	0
T3	2777	32	0	0
T4	804469	274908	0	0
T5	144193	1316	0	0
T6	2817	180	0	0
T7	68006	15174	0	0
T17	1202	32	0	0
T18	1042	32	0	0
T19	190305	121875	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	111089434	0	0
T1	265843	164616	0	0
T2	101581	5930	0	0
T3	2777	32	0	0
T4	804469	274908	0	0
T5	144193	1316	0	0
T6	2817	180	0	0
T7	68006	15534	0	0
T17	1202	32	0	0
T18	1042	32	0	0
T19	190305	121875	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	381153635	0	0
T1	265843	249942	0	0
T2	101581	101575	0	0
T3	2777	2715	0	0
T4	804469	804443	0	0
T5	144193	144097	0	0
T6	2817	2663	0	0
T7	68006	67818	0	0
T17	1202	1135	0	0
T18	1042	991	0	0
T19	190305	190295	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T6
1	0	Covered	T7,T6,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T6,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T6,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T6,T8
1	0	Covered	T2,T4,T6
1	1	Covered	T7,T6,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T6,T8
1	1	Covered	T2,T4,T6

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T6,T8
1	1	Covered	T2,T4,T7

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T6,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T6,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	382045158	381153635	0	0
CheckNGreaterZero_A	1041	1041	0	0
GntImpliesReady_A	382045158	100478117	0	0
GntImpliesValid_A	382045158	100478117	0	0
GrantKnown_A	382045158	381153635	0	0
IdxKnown_A	382045158	381153635	0	0
IndexIsCorrect_A	382045158	100478117	0	0
NoReadyValidNoGrant_A	382045158	44408545	0	0
Priority_A	382045158	106347279	0	0
ReadyAndValidImplyGrant_A	382045158	100478117	0	0
ReqAndReadyImplyGrant_A	382045158	100478117	0	0
ReqImpliesValid_A	382045158	106347279	0	0
ValidKnown_A	382045158	381153635	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	381153635	0	0
T1	265843	249942	0	0
T2	101581	101575	0	0
T3	2777	2715	0	0
T4	804469	804443	0	0
T5	144193	144097	0	0
T6	2817	2663	0	0
T7	68006	67818	0	0
T17	1202	1135	0	0
T18	1042	991	0	0
T19	190305	190295	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1041	1041	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	100478117	0	0
T2	101581	712439	0	0
T3	2777	0	0	0
T4	804469	269613	0	0
T5	144193	0	0	0
T6	2817	80	0	0
T7	68006	8278	0	0
T8	0	10208	0	0
T9	0	10546	0	0
T17	1202	0	0	0
T18	1042	0	0	0
T19	190305	656593	0	0
T24	0	75468	0	0
T47	379522	0	0	0
T59	0	209941	0	0
T64	0	127897	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	100478117	0	0
T2	101581	712439	0	0
T3	2777	0	0	0
T4	804469	269613	0	0
T5	144193	0	0	0
T6	2817	80	0	0
T7	68006	8278	0	0
T8	0	10208	0	0
T9	0	10546	0	0
T17	1202	0	0	0
T18	1042	0	0	0
T19	190305	656593	0	0
T24	0	75468	0	0
T47	379522	0	0	0
T59	0	209941	0	0
T64	0	127897	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	381153635	0	0
T1	265843	249942	0	0
T2	101581	101575	0	0
T3	2777	2715	0	0
T4	804469	804443	0	0
T5	144193	144097	0	0
T6	2817	2663	0	0
T7	68006	67818	0	0
T17	1202	1135	0	0
T18	1042	991	0	0
T19	190305	190295	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	381153635	0	0
T1	265843	249942	0	0
T2	101581	101575	0	0
T3	2777	2715	0	0
T4	804469	804443	0	0
T5	144193	144097	0	0
T6	2817	2663	0	0
T7	68006	67818	0	0
T17	1202	1135	0	0
T18	1042	991	0	0
T19	190305	190295	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	100478117	0	0
T2	101581	712439	0	0
T3	2777	0	0	0
T4	804469	269613	0	0
T5	144193	0	0	0
T6	2817	80	0	0
T7	68006	8278	0	0
T8	0	10208	0	0
T9	0	10546	0	0
T17	1202	0	0	0
T18	1042	0	0	0
T19	190305	656593	0	0
T24	0	75468	0	0
T47	379522	0	0	0
T59	0	209941	0	0
T64	0	127897	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	44408545	0	0
T2	101581	5519	0	0
T3	2777	0	0	0
T4	804469	105164	0	0
T5	144193	0	0	0
T6	2817	38	0	0
T7	68006	24566	0	0
T8	0	29140	0	0
T9	0	14073	0	0
T17	1202	0	0	0
T18	1042	0	0	0
T19	190305	0	0	0
T21	0	80	0	0
T31	0	482457	0	0
T47	379522	0	0	0
T59	0	722	0	0
T64	0	524288	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	106347279	0	0
T2	101581	712439	0	0
T3	2777	0	0	0
T4	804469	269613	0	0
T5	144193	0	0	0
T6	2817	80	0	0
T7	68006	9360	0	0
T8	0	11157	0	0
T9	0	15699	0	0
T17	1202	0	0	0
T18	1042	0	0	0
T19	190305	656593	0	0
T24	0	75468	0	0
T47	379522	0	0	0
T59	0	209941	0	0
T64	0	127897	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	100478117	0	0
T2	101581	712439	0	0
T3	2777	0	0	0
T4	804469	269613	0	0
T5	144193	0	0	0
T6	2817	80	0	0
T7	68006	8278	0	0
T8	0	10208	0	0
T9	0	10546	0	0
T17	1202	0	0	0
T18	1042	0	0	0
T19	190305	656593	0	0
T24	0	75468	0	0
T47	379522	0	0	0
T59	0	209941	0	0
T64	0	127897	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	100478117	0	0
T2	101581	712439	0	0
T3	2777	0	0	0
T4	804469	269613	0	0
T5	144193	0	0	0
T6	2817	80	0	0
T7	68006	8278	0	0
T8	0	10208	0	0
T9	0	10546	0	0
T17	1202	0	0	0
T18	1042	0	0	0
T19	190305	656593	0	0
T24	0	75468	0	0
T47	379522	0	0	0
T59	0	209941	0	0
T64	0	127897	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	106347279	0	0
T2	101581	712439	0	0
T3	2777	0	0	0
T4	804469	269613	0	0
T5	144193	0	0	0
T6	2817	80	0	0
T7	68006	9360	0	0
T8	0	11157	0	0
T9	0	15699	0	0
T17	1202	0	0	0
T18	1042	0	0	0
T19	190305	656593	0	0
T24	0	75468	0	0
T47	379522	0	0	0
T59	0	209941	0	0
T64	0	127897	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	381153635	0	0
T1	265843	249942	0	0
T2	101581	101575	0	0
T3	2777	2715	0	0
T4	804469	804443	0	0
T5	144193	144097	0	0
T6	2817	2663	0	0
T7	68006	67818	0	0
T17	1202	1135	0	0
T18	1042	991	0	0
T19	190305	190295	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T6
1	0	Covered	T7,T6,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T6,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T7,T6,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T6,T8
1	0	Covered	T2,T4,T6
1	1	Covered	T7,T6,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T6,T8
1	1	Covered	T2,T4,T6

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T6,T8
1	1	Covered	T2,T4,T7

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T6,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T6,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	382045158	381153635	0	0
CheckNGreaterZero_A	1041	1041	0	0
GntImpliesReady_A	382045158	100478142	0	0
GntImpliesValid_A	382045158	100478142	0	0
GrantKnown_A	382045158	381153635	0	0
IdxKnown_A	382045158	381153635	0	0
IndexIsCorrect_A	382045158	100478142	0	0
NoReadyValidNoGrant_A	382045158	44408489	0	0
Priority_A	382045158	106347360	0	0
ReadyAndValidImplyGrant_A	382045158	100478142	0	0
ReqAndReadyImplyGrant_A	382045158	100478142	0	0
ReqImpliesValid_A	382045158	106347360	0	0
ValidKnown_A	382045158	381153635	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	381153635	0	0
T1	265843	249942	0	0
T2	101581	101575	0	0
T3	2777	2715	0	0
T4	804469	804443	0	0
T5	144193	144097	0	0
T6	2817	2663	0	0
T7	68006	67818	0	0
T17	1202	1135	0	0
T18	1042	991	0	0
T19	190305	190295	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1041	1041	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	100478142	0	0
T2	101581	712439	0	0
T3	2777	0	0	0
T4	804469	269613	0	0
T5	144193	0	0	0
T6	2817	80	0	0
T7	68006	8278	0	0
T8	0	10208	0	0
T9	0	10546	0	0
T17	1202	0	0	0
T18	1042	0	0	0
T19	190305	656593	0	0
T24	0	75468	0	0
T47	379522	0	0	0
T59	0	209941	0	0
T64	0	127897	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	100478142	0	0
T2	101581	712439	0	0
T3	2777	0	0	0
T4	804469	269613	0	0
T5	144193	0	0	0
T6	2817	80	0	0
T7	68006	8278	0	0
T8	0	10208	0	0
T9	0	10546	0	0
T17	1202	0	0	0
T18	1042	0	0	0
T19	190305	656593	0	0
T24	0	75468	0	0
T47	379522	0	0	0
T59	0	209941	0	0
T64	0	127897	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	381153635	0	0
T1	265843	249942	0	0
T2	101581	101575	0	0
T3	2777	2715	0	0
T4	804469	804443	0	0
T5	144193	144097	0	0
T6	2817	2663	0	0
T7	68006	67818	0	0
T17	1202	1135	0	0
T18	1042	991	0	0
T19	190305	190295	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	381153635	0	0
T1	265843	249942	0	0
T2	101581	101575	0	0
T3	2777	2715	0	0
T4	804469	804443	0	0
T5	144193	144097	0	0
T6	2817	2663	0	0
T7	68006	67818	0	0
T17	1202	1135	0	0
T18	1042	991	0	0
T19	190305	190295	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	100478142	0	0
T2	101581	712439	0	0
T3	2777	0	0	0
T4	804469	269613	0	0
T5	144193	0	0	0
T6	2817	80	0	0
T7	68006	8278	0	0
T8	0	10208	0	0
T9	0	10546	0	0
T17	1202	0	0	0
T18	1042	0	0	0
T19	190305	656593	0	0
T24	0	75468	0	0
T47	379522	0	0	0
T59	0	209941	0	0
T64	0	127897	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	44408489	0	0
T2	101581	5519	0	0
T3	2777	0	0	0
T4	804469	105164	0	0
T5	144193	0	0	0
T6	2817	38	0	0
T7	68006	24566	0	0
T8	0	29140	0	0
T9	0	14073	0	0
T17	1202	0	0	0
T18	1042	0	0	0
T19	190305	0	0	0
T21	0	80	0	0
T31	0	482457	0	0
T47	379522	0	0	0
T59	0	722	0	0
T64	0	524288	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	106347360	0	0
T2	101581	712439	0	0
T3	2777	0	0	0
T4	804469	269613	0	0
T5	144193	0	0	0
T6	2817	80	0	0
T7	68006	9360	0	0
T8	0	11157	0	0
T9	0	15699	0	0
T17	1202	0	0	0
T18	1042	0	0	0
T19	190305	656593	0	0
T24	0	75468	0	0
T47	379522	0	0	0
T59	0	209941	0	0
T64	0	127897	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	100478142	0	0
T2	101581	712439	0	0
T3	2777	0	0	0
T4	804469	269613	0	0
T5	144193	0	0	0
T6	2817	80	0	0
T7	68006	8278	0	0
T8	0	10208	0	0
T9	0	10546	0	0
T17	1202	0	0	0
T18	1042	0	0	0
T19	190305	656593	0	0
T24	0	75468	0	0
T47	379522	0	0	0
T59	0	209941	0	0
T64	0	127897	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	100478142	0	0
T2	101581	712439	0	0
T3	2777	0	0	0
T4	804469	269613	0	0
T5	144193	0	0	0
T6	2817	80	0	0
T7	68006	8278	0	0
T8	0	10208	0	0
T9	0	10546	0	0
T17	1202	0	0	0
T18	1042	0	0	0
T19	190305	656593	0	0
T24	0	75468	0	0
T47	379522	0	0	0
T59	0	209941	0	0
T64	0	127897	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	106347360	0	0
T2	101581	712439	0	0
T3	2777	0	0	0
T4	804469	269613	0	0
T5	144193	0	0	0
T6	2817	80	0	0
T7	68006	9360	0	0
T8	0	11157	0	0
T9	0	15699	0	0
T17	1202	0	0	0
T18	1042	0	0	0
T19	190305	656593	0	0
T24	0	75468	0	0
T47	379522	0	0	0
T59	0	209941	0	0
T64	0	127897	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	382045158	381153635	0	0
T1	265843	249942	0	0
T2	101581	101575	0	0
T3	2777	2715	0	0
T4	804469	804443	0	0
T5	144193	144097	0	0
T6	2817	2663	0	0
T7	68006	67818	0	0
T17	1202	1135	0	0
T18	1042	991	0	0
T19	190305	190295	0	0