Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block] 100.00 1 100 1 64 64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0



Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 25046833 1 T1 1411 T2 614 T3 7450
full_word 8016732 1 T1 656 T2 607 T3 32258



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 33063275 1 T1 2067 T2 1221 T3 39708
auto[TlIntgErrCmd] 87 1 T205 5 T271 7 T334 7
auto[TlIntgErrData] 91 1 T101 5 T238 7 T205 6
auto[TlIntgErrBoth] 112 1 T101 5 T238 3 T205 9



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 28515496 1 T1 1421 T2 1157 T3 33077
auto[1] 4548069 1 T1 646 T2 64 T3 6631



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 24312551 1 T1 1375 T2 605 T3 5069
auto[TlIntgErrNone] partial auto[1] 734013 1 T1 36 T2 9 T3 2381
auto[TlIntgErrNone] full_word auto[0] 4202824 1 T1 46 T2 552 T3 28008
auto[TlIntgErrNone] full_word auto[1] 3813887 1 T1 610 T2 55 T3 4250
auto[TlIntgErrCmd] partial auto[0] 35 1 T205 2 T271 4 T334 3
auto[TlIntgErrCmd] partial auto[1] 47 1 T205 3 T271 3 T334 4
auto[TlIntgErrCmd] full_word auto[0] 1 1 T297 1 - - - -
auto[TlIntgErrCmd] full_word auto[1] 4 1 T293 1 T337 2 T297 1
auto[TlIntgErrData] partial auto[0] 45 1 T101 2 T238 6 T205 2
auto[TlIntgErrData] partial auto[1] 41 1 T101 3 T238 1 T205 3
auto[TlIntgErrData] full_word auto[0] 1 1 T333 1 - - - -
auto[TlIntgErrData] full_word auto[1] 4 1 T205 1 T271 1 T293 1
auto[TlIntgErrBoth] partial auto[0] 36 1 T101 2 T238 1 T205 2
auto[TlIntgErrBoth] partial auto[1] 65 1 T101 1 T238 2 T205 7
auto[TlIntgErrBoth] full_word auto[0] 3 1 T101 1 T298 1 T338 1
auto[TlIntgErrBoth] full_word auto[1] 8 1 T101 1 T271 1 T333 1


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 19785 1 T101 9 T102 93 T104 491
full_word 3834862 1 T1 164 T3 16711 T6 16799



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 3854373 1 T1 164 T3 16711 T6 16799
auto[TlIntgErrCmd] 82 1 T101 2 T238 4 T205 5
auto[TlIntgErrData] 109 1 T101 4 T238 3 T205 7
auto[TlIntgErrBoth] 83 1 T101 4 T238 2 T205 7



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3831014 1 T1 164 T3 16711 T6 16799
auto[1] 23633 1 T101 5 T102 152 T104 676



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 1371 1 T102 16 T104 66 T103 10
auto[TlIntgErrNone] partial auto[1] 18169 1 T102 77 T104 425 T103 108
auto[TlIntgErrNone] full_word auto[0] 3829519 1 T1 164 T3 16711 T6 16799
auto[TlIntgErrNone] full_word auto[1] 5314 1 T102 75 T104 251 T103 38
auto[TlIntgErrCmd] partial auto[0] 26 1 T101 2 T238 2 T205 2
auto[TlIntgErrCmd] partial auto[1] 48 1 T238 2 T205 3 T271 6
auto[TlIntgErrCmd] full_word auto[0] 6 1 T271 1 T339 1 T340 1
auto[TlIntgErrCmd] full_word auto[1] 2 1 T271 1 T277 1 - -
auto[TlIntgErrData] partial auto[0] 53 1 T101 1 T238 2 T205 2
auto[TlIntgErrData] partial auto[1] 41 1 T101 3 T238 1 T205 3
auto[TlIntgErrData] full_word auto[0] 4 1 T205 1 T336 1 T340 1
auto[TlIntgErrData] full_word auto[1] 11 1 T205 1 T271 1 T334 1
auto[TlIntgErrBoth] partial auto[0] 34 1 T101 2 T238 2 T205 1
auto[TlIntgErrBoth] partial auto[1] 43 1 T101 1 T205 5 T271 2
auto[TlIntgErrBoth] full_word auto[0] 1 1 T341 1 - - - -
auto[TlIntgErrBoth] full_word auto[1] 5 1 T101 1 T205 1 T293 1

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