Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1596302624	1592684932	0	0
CheckNGreaterZero_A	4168	4168	0	0
GntImpliesReady_A	1596302624	408468520	0	0
GntImpliesValid_A	1596302624	408468520	0	0
GrantKnown_A	1596302624	1592684932	0	0
IdxKnown_A	1596302624	1592684932	0	0
IndexIsCorrect_A	1596302624	408468520	0	0
NoReadyValidNoGrant_A	1596302624	178183296	0	0
Priority_A	1596302624	432616672	0	0
ReadyAndValidImplyGrant_A	1596302624	408468520	0	0
ReqAndReadyImplyGrant_A	1596302624	408468520	0	0
ReqImpliesValid_A	1596302624	432616672	0	0
ValidKnown_A	1596302624	1592684932	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1596302624	1592684932	0	0
T1	24212	23996	0	0
T2	1604964	1604900	0	0
T3	628552	627992	0	0
T4	517848	416972	0	0
T5	2353852	2353492	0	0
T6	294416	293708	0	0
T10	4440	3692	0	0
T11	13944	11124	0	0
T13	5592	5356	0	0
T14	277828	277620	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4168	4168	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T10	4	4	0	0
T11	4	4	0	0
T13	4	4	0	0
T14	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1596302624	408468520	0	0
T1	24212	6122	0	0
T2	1604964	514600	0	0
T3	628552	86206	0	0
T4	517848	0	0	0
T5	2353852	1111190	0	0
T6	294416	51210	0	0
T10	4440	134	0	0
T11	13944	324	0	0
T13	5592	64	0	0
T14	277828	44416	0	0
T15	0	568786	0	0
T19	0	33430	0	0
T28	0	82942	0	0
T30	0	80	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1596302624	408468520	0	0
T1	24212	6122	0	0
T2	1604964	514600	0	0
T3	628552	86206	0	0
T4	517848	0	0	0
T5	2353852	1111190	0	0
T6	294416	51210	0	0
T10	4440	134	0	0
T11	13944	324	0	0
T13	5592	64	0	0
T14	277828	44416	0	0
T15	0	568786	0	0
T19	0	33430	0	0
T28	0	82942	0	0
T30	0	80	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1596302624	1592684932	0	0
T1	24212	23996	0	0
T2	1604964	1604900	0	0
T3	628552	627992	0	0
T4	517848	416972	0	0
T5	2353852	2353492	0	0
T6	294416	293708	0	0
T10	4440	3692	0	0
T11	13944	11124	0	0
T13	5592	5356	0	0
T14	277828	277620	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1596302624	1592684932	0	0
T1	24212	23996	0	0
T2	1604964	1604900	0	0
T3	628552	627992	0	0
T4	517848	416972	0	0
T5	2353852	2353492	0	0
T6	294416	293708	0	0
T10	4440	3692	0	0
T11	13944	11124	0	0
T13	5592	5356	0	0
T14	277828	277620	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1596302624	408468520	0	0
T1	24212	6122	0	0
T2	1604964	514600	0	0
T3	628552	86206	0	0
T4	517848	0	0	0
T5	2353852	1111190	0	0
T6	294416	51210	0	0
T10	4440	134	0	0
T11	13944	324	0	0
T13	5592	64	0	0
T14	277828	44416	0	0
T15	0	568786	0	0
T19	0	33430	0	0
T28	0	82942	0	0
T30	0	80	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1596302624	178183296	0	0
T1	24212	918	0	0
T2	1604964	2109952	0	0
T3	628552	142116	0	0
T4	517848	0	0	0
T5	2353852	2452	0	0
T6	294416	146984	0	0
T10	4440	536	0	0
T11	13944	1296	0	0
T13	5592	256	0	0
T14	277828	126764	0	0
T15	0	187728	0	0
T19	0	92800	0	0
T28	0	60454	0	0
T30	0	122	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1596302624	432616672	0	0
T1	24212	6236	0	0
T2	1604964	514600	0	0
T3	628552	95014	0	0
T4	517848	0	0	0
T5	2353852	1111190	0	0
T6	294416	55452	0	0
T10	4440	134	0	0
T11	13944	324	0	0
T13	5592	64	0	0
T14	277828	47028	0	0
T15	0	688886	0	0
T19	0	35246	0	0
T28	0	94670	0	0
T30	0	80	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1596302624	408468520	0	0
T1	24212	6122	0	0
T2	1604964	514600	0	0
T3	628552	86206	0	0
T4	517848	0	0	0
T5	2353852	1111190	0	0
T6	294416	51210	0	0
T10	4440	134	0	0
T11	13944	324	0	0
T13	5592	64	0	0
T14	277828	44416	0	0
T15	0	568786	0	0
T19	0	33430	0	0
T28	0	82942	0	0
T30	0	80	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1596302624	408468520	0	0
T1	24212	6122	0	0
T2	1604964	514600	0	0
T3	628552	86206	0	0
T4	517848	0	0	0
T5	2353852	1111190	0	0
T6	294416	51210	0	0
T10	4440	134	0	0
T11	13944	324	0	0
T13	5592	64	0	0
T14	277828	44416	0	0
T15	0	568786	0	0
T19	0	33430	0	0
T28	0	82942	0	0
T30	0	80	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1596302624	432616672	0	0
T1	24212	6236	0	0
T2	1604964	514600	0	0
T3	628552	95014	0	0
T4	517848	0	0	0
T5	2353852	1111190	0	0
T6	294416	55452	0	0
T10	4440	134	0	0
T11	13944	324	0	0
T13	5592	64	0	0
T14	277828	47028	0	0
T15	0	688886	0	0
T19	0	35246	0	0
T28	0	94670	0	0
T30	0	80	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1596302624	1592684932	0	0
T1	24212	23996	0	0
T2	1604964	1604900	0	0
T3	628552	627992	0	0
T4	517848	416972	0	0
T5	2353852	2353492	0	0
T6	294416	293708	0	0
T10	4440	3692	0	0
T11	13944	11124	0	0
T13	5592	5356	0	0
T14	277828	277620	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	399075656	398171233	0	0
CheckNGreaterZero_A	1042	1042	0	0
GntImpliesReady_A	399075656	107756689	0	0
GntImpliesValid_A	399075656	107756689	0	0
GrantKnown_A	399075656	398171233	0	0
IdxKnown_A	399075656	398171233	0	0
IndexIsCorrect_A	399075656	107756689	0	0
NoReadyValidNoGrant_A	399075656	46441012	0	0
Priority_A	399075656	113718940	0	0
ReadyAndValidImplyGrant_A	399075656	107756689	0	0
ReqAndReadyImplyGrant_A	399075656	107756689	0	0
ReqImpliesValid_A	399075656	113718940	0	0
ValidKnown_A	399075656	398171233	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	398171233	0	0
T1	6053	5999	0	0
T2	401241	401225	0	0
T3	157138	156998	0	0
T4	129462	104243	0	0
T5	588463	588373	0	0
T6	73604	73427	0	0
T10	1110	923	0	0
T11	3486	2781	0	0
T13	1398	1339	0	0
T14	69457	69405	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	107756689	0	0
T1	6053	1062	0	0
T2	401241	129403	0	0
T3	157138	21417	0	0
T4	129462	0	0	0
T5	588463	275724	0	0
T6	73604	17280	0	0
T10	1110	67	0	0
T11	3486	162	0	0
T13	1398	32	0	0
T14	69457	13011	0	0
T15	0	164708	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	107756689	0	0
T1	6053	1062	0	0
T2	401241	129403	0	0
T3	157138	21417	0	0
T4	129462	0	0	0
T5	588463	275724	0	0
T6	73604	17280	0	0
T10	1110	67	0	0
T11	3486	162	0	0
T13	1398	32	0	0
T14	69457	13011	0	0
T15	0	164708	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	398171233	0	0
T1	6053	5999	0	0
T2	401241	401225	0	0
T3	157138	156998	0	0
T4	129462	104243	0	0
T5	588463	588373	0	0
T6	73604	73427	0	0
T10	1110	923	0	0
T11	3486	2781	0	0
T13	1398	1339	0	0
T14	69457	69405	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	398171233	0	0
T1	6053	5999	0	0
T2	401241	401225	0	0
T3	157138	156998	0	0
T4	129462	104243	0	0
T5	588463	588373	0	0
T6	73604	73427	0	0
T10	1110	923	0	0
T11	3486	2781	0	0
T13	1398	1339	0	0
T14	69457	69405	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	107756689	0	0
T1	6053	1062	0	0
T2	401241	129403	0	0
T3	157138	21417	0	0
T4	129462	0	0	0
T5	588463	275724	0	0
T6	73604	17280	0	0
T10	1110	67	0	0
T11	3486	162	0	0
T13	1398	32	0	0
T14	69457	13011	0	0
T15	0	164708	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	46441012	0	0
T1	6053	297	0	0
T2	401241	530688	0	0
T3	157138	36750	0	0
T4	129462	0	0	0
T5	588463	642	0	0
T6	73604	47737	0	0
T10	1110	268	0	0
T11	3486	648	0	0
T13	1398	128	0	0
T14	69457	36113	0	0
T15	0	48824	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	113718940	0	0
T1	6053	1081	0	0
T2	401241	129403	0	0
T3	157138	23299	0	0
T4	129462	0	0	0
T5	588463	275724	0	0
T6	73604	17889	0	0
T10	1110	67	0	0
T11	3486	162	0	0
T13	1398	32	0	0
T14	69457	13578	0	0
T15	0	195627	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	107756689	0	0
T1	6053	1062	0	0
T2	401241	129403	0	0
T3	157138	21417	0	0
T4	129462	0	0	0
T5	588463	275724	0	0
T6	73604	17280	0	0
T10	1110	67	0	0
T11	3486	162	0	0
T13	1398	32	0	0
T14	69457	13011	0	0
T15	0	164708	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	107756689	0	0
T1	6053	1062	0	0
T2	401241	129403	0	0
T3	157138	21417	0	0
T4	129462	0	0	0
T5	588463	275724	0	0
T6	73604	17280	0	0
T10	1110	67	0	0
T11	3486	162	0	0
T13	1398	32	0	0
T14	69457	13011	0	0
T15	0	164708	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	113718940	0	0
T1	6053	1081	0	0
T2	401241	129403	0	0
T3	157138	23299	0	0
T4	129462	0	0	0
T5	588463	275724	0	0
T6	73604	17889	0	0
T10	1110	67	0	0
T11	3486	162	0	0
T13	1398	32	0	0
T14	69457	13578	0	0
T15	0	195627	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	398171233	0	0
T1	6053	5999	0	0
T2	401241	401225	0	0
T3	157138	156998	0	0
T4	129462	104243	0	0
T5	588463	588373	0	0
T6	73604	73427	0	0
T10	1110	923	0	0
T11	3486	2781	0	0
T13	1398	1339	0	0
T14	69457	69405	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	399075656	398171233	0	0
CheckNGreaterZero_A	1042	1042	0	0
GntImpliesReady_A	399075656	107756689	0	0
GntImpliesValid_A	399075656	107756689	0	0
GrantKnown_A	399075656	398171233	0	0
IdxKnown_A	399075656	398171233	0	0
IndexIsCorrect_A	399075656	107756689	0	0
NoReadyValidNoGrant_A	399075656	46441012	0	0
Priority_A	399075656	113718940	0	0
ReadyAndValidImplyGrant_A	399075656	107756689	0	0
ReqAndReadyImplyGrant_A	399075656	107756689	0	0
ReqImpliesValid_A	399075656	113718940	0	0
ValidKnown_A	399075656	398171233	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	398171233	0	0
T1	6053	5999	0	0
T2	401241	401225	0	0
T3	157138	156998	0	0
T4	129462	104243	0	0
T5	588463	588373	0	0
T6	73604	73427	0	0
T10	1110	923	0	0
T11	3486	2781	0	0
T13	1398	1339	0	0
T14	69457	69405	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	107756689	0	0
T1	6053	1062	0	0
T2	401241	129403	0	0
T3	157138	21417	0	0
T4	129462	0	0	0
T5	588463	275724	0	0
T6	73604	17280	0	0
T10	1110	67	0	0
T11	3486	162	0	0
T13	1398	32	0	0
T14	69457	13011	0	0
T15	0	164708	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	107756689	0	0
T1	6053	1062	0	0
T2	401241	129403	0	0
T3	157138	21417	0	0
T4	129462	0	0	0
T5	588463	275724	0	0
T6	73604	17280	0	0
T10	1110	67	0	0
T11	3486	162	0	0
T13	1398	32	0	0
T14	69457	13011	0	0
T15	0	164708	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	398171233	0	0
T1	6053	5999	0	0
T2	401241	401225	0	0
T3	157138	156998	0	0
T4	129462	104243	0	0
T5	588463	588373	0	0
T6	73604	73427	0	0
T10	1110	923	0	0
T11	3486	2781	0	0
T13	1398	1339	0	0
T14	69457	69405	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	398171233	0	0
T1	6053	5999	0	0
T2	401241	401225	0	0
T3	157138	156998	0	0
T4	129462	104243	0	0
T5	588463	588373	0	0
T6	73604	73427	0	0
T10	1110	923	0	0
T11	3486	2781	0	0
T13	1398	1339	0	0
T14	69457	69405	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	107756689	0	0
T1	6053	1062	0	0
T2	401241	129403	0	0
T3	157138	21417	0	0
T4	129462	0	0	0
T5	588463	275724	0	0
T6	73604	17280	0	0
T10	1110	67	0	0
T11	3486	162	0	0
T13	1398	32	0	0
T14	69457	13011	0	0
T15	0	164708	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	46441012	0	0
T1	6053	297	0	0
T2	401241	530688	0	0
T3	157138	36750	0	0
T4	129462	0	0	0
T5	588463	642	0	0
T6	73604	47737	0	0
T10	1110	268	0	0
T11	3486	648	0	0
T13	1398	128	0	0
T14	69457	36113	0	0
T15	0	48824	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	113718940	0	0
T1	6053	1081	0	0
T2	401241	129403	0	0
T3	157138	23299	0	0
T4	129462	0	0	0
T5	588463	275724	0	0
T6	73604	17889	0	0
T10	1110	67	0	0
T11	3486	162	0	0
T13	1398	32	0	0
T14	69457	13578	0	0
T15	0	195627	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	107756689	0	0
T1	6053	1062	0	0
T2	401241	129403	0	0
T3	157138	21417	0	0
T4	129462	0	0	0
T5	588463	275724	0	0
T6	73604	17280	0	0
T10	1110	67	0	0
T11	3486	162	0	0
T13	1398	32	0	0
T14	69457	13011	0	0
T15	0	164708	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	107756689	0	0
T1	6053	1062	0	0
T2	401241	129403	0	0
T3	157138	21417	0	0
T4	129462	0	0	0
T5	588463	275724	0	0
T6	73604	17280	0	0
T10	1110	67	0	0
T11	3486	162	0	0
T13	1398	32	0	0
T14	69457	13011	0	0
T15	0	164708	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	113718940	0	0
T1	6053	1081	0	0
T2	401241	129403	0	0
T3	157138	23299	0	0
T4	129462	0	0	0
T5	588463	275724	0	0
T6	73604	17889	0	0
T10	1110	67	0	0
T11	3486	162	0	0
T13	1398	32	0	0
T14	69457	13578	0	0
T15	0	195627	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	398171233	0	0
T1	6053	5999	0	0
T2	401241	401225	0	0
T3	157138	156998	0	0
T4	129462	104243	0	0
T5	588463	588373	0	0
T6	73604	73427	0	0
T10	1110	923	0	0
T11	3486	2781	0	0
T13	1398	1339	0	0
T14	69457	69405	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	399075656	398171233	0	0
CheckNGreaterZero_A	1042	1042	0	0
GntImpliesReady_A	399075656	96477571	0	0
GntImpliesValid_A	399075656	96477571	0	0
GrantKnown_A	399075656	398171233	0	0
IdxKnown_A	399075656	398171233	0	0
IndexIsCorrect_A	399075656	96477571	0	0
NoReadyValidNoGrant_A	399075656	42650636	0	0
Priority_A	399075656	102589396	0	0
ReadyAndValidImplyGrant_A	399075656	96477571	0	0
ReqAndReadyImplyGrant_A	399075656	96477571	0	0
ReqImpliesValid_A	399075656	102589396	0	0
ValidKnown_A	399075656	398171233	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	398171233	0	0
T1	6053	5999	0	0
T2	401241	401225	0	0
T3	157138	156998	0	0
T4	129462	104243	0	0
T5	588463	588373	0	0
T6	73604	73427	0	0
T10	1110	923	0	0
T11	3486	2781	0	0
T13	1398	1339	0	0
T14	69457	69405	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	96477571	0	0
T1	6053	1999	0	0
T2	401241	127897	0	0
T3	157138	21686	0	0
T4	129462	0	0	0
T5	588463	279871	0	0
T6	73604	8325	0	0
T10	1110	0	0	0
T11	3486	0	0	0
T13	1398	0	0	0
T14	69457	9197	0	0
T15	0	119685	0	0
T19	0	16715	0	0
T28	0	41471	0	0
T30	0	40	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	96477571	0	0
T1	6053	1999	0	0
T2	401241	127897	0	0
T3	157138	21686	0	0
T4	129462	0	0	0
T5	588463	279871	0	0
T6	73604	8325	0	0
T10	1110	0	0	0
T11	3486	0	0	0
T13	1398	0	0	0
T14	69457	9197	0	0
T15	0	119685	0	0
T19	0	16715	0	0
T28	0	41471	0	0
T30	0	40	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	398171233	0	0
T1	6053	5999	0	0
T2	401241	401225	0	0
T3	157138	156998	0	0
T4	129462	104243	0	0
T5	588463	588373	0	0
T6	73604	73427	0	0
T10	1110	923	0	0
T11	3486	2781	0	0
T13	1398	1339	0	0
T14	69457	69405	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	398171233	0	0
T1	6053	5999	0	0
T2	401241	401225	0	0
T3	157138	156998	0	0
T4	129462	104243	0	0
T5	588463	588373	0	0
T6	73604	73427	0	0
T10	1110	923	0	0
T11	3486	2781	0	0
T13	1398	1339	0	0
T14	69457	69405	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	96477571	0	0
T1	6053	1999	0	0
T2	401241	127897	0	0
T3	157138	21686	0	0
T4	129462	0	0	0
T5	588463	279871	0	0
T6	73604	8325	0	0
T10	1110	0	0	0
T11	3486	0	0	0
T13	1398	0	0	0
T14	69457	9197	0	0
T15	0	119685	0	0
T19	0	16715	0	0
T28	0	41471	0	0
T30	0	40	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	42650636	0	0
T1	6053	162	0	0
T2	401241	524288	0	0
T3	157138	34308	0	0
T4	129462	0	0	0
T5	588463	584	0	0
T6	73604	25755	0	0
T10	1110	0	0	0
T11	3486	0	0	0
T13	1398	0	0	0
T14	69457	27269	0	0
T15	0	45040	0	0
T19	0	46400	0	0
T28	0	30227	0	0
T30	0	61	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	102589396	0	0
T1	6053	2037	0	0
T2	401241	127897	0	0
T3	157138	24208	0	0
T4	129462	0	0	0
T5	588463	279871	0	0
T6	73604	9837	0	0
T10	1110	0	0	0
T11	3486	0	0	0
T13	1398	0	0	0
T14	69457	9936	0	0
T15	0	148816	0	0
T19	0	17623	0	0
T28	0	47335	0	0
T30	0	40	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	96477571	0	0
T1	6053	1999	0	0
T2	401241	127897	0	0
T3	157138	21686	0	0
T4	129462	0	0	0
T5	588463	279871	0	0
T6	73604	8325	0	0
T10	1110	0	0	0
T11	3486	0	0	0
T13	1398	0	0	0
T14	69457	9197	0	0
T15	0	119685	0	0
T19	0	16715	0	0
T28	0	41471	0	0
T30	0	40	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	96477571	0	0
T1	6053	1999	0	0
T2	401241	127897	0	0
T3	157138	21686	0	0
T4	129462	0	0	0
T5	588463	279871	0	0
T6	73604	8325	0	0
T10	1110	0	0	0
T11	3486	0	0	0
T13	1398	0	0	0
T14	69457	9197	0	0
T15	0	119685	0	0
T19	0	16715	0	0
T28	0	41471	0	0
T30	0	40	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	102589396	0	0
T1	6053	2037	0	0
T2	401241	127897	0	0
T3	157138	24208	0	0
T4	129462	0	0	0
T5	588463	279871	0	0
T6	73604	9837	0	0
T10	1110	0	0	0
T11	3486	0	0	0
T13	1398	0	0	0
T14	69457	9936	0	0
T15	0	148816	0	0
T19	0	17623	0	0
T28	0	47335	0	0
T30	0	40	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	398171233	0	0
T1	6053	5999	0	0
T2	401241	401225	0	0
T3	157138	156998	0	0
T4	129462	104243	0	0
T5	588463	588373	0	0
T6	73604	73427	0	0
T10	1110	923	0	0
T11	3486	2781	0	0
T13	1398	1339	0	0
T14	69457	69405	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	399075656	398171233	0	0
CheckNGreaterZero_A	1042	1042	0	0
GntImpliesReady_A	399075656	96477571	0	0
GntImpliesValid_A	399075656	96477571	0	0
GrantKnown_A	399075656	398171233	0	0
IdxKnown_A	399075656	398171233	0	0
IndexIsCorrect_A	399075656	96477571	0	0
NoReadyValidNoGrant_A	399075656	42650636	0	0
Priority_A	399075656	102589396	0	0
ReadyAndValidImplyGrant_A	399075656	96477571	0	0
ReqAndReadyImplyGrant_A	399075656	96477571	0	0
ReqImpliesValid_A	399075656	102589396	0	0
ValidKnown_A	399075656	398171233	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	398171233	0	0
T1	6053	5999	0	0
T2	401241	401225	0	0
T3	157138	156998	0	0
T4	129462	104243	0	0
T5	588463	588373	0	0
T6	73604	73427	0	0
T10	1110	923	0	0
T11	3486	2781	0	0
T13	1398	1339	0	0
T14	69457	69405	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	96477571	0	0
T1	6053	1999	0	0
T2	401241	127897	0	0
T3	157138	21686	0	0
T4	129462	0	0	0
T5	588463	279871	0	0
T6	73604	8325	0	0
T10	1110	0	0	0
T11	3486	0	0	0
T13	1398	0	0	0
T14	69457	9197	0	0
T15	0	119685	0	0
T19	0	16715	0	0
T28	0	41471	0	0
T30	0	40	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	96477571	0	0
T1	6053	1999	0	0
T2	401241	127897	0	0
T3	157138	21686	0	0
T4	129462	0	0	0
T5	588463	279871	0	0
T6	73604	8325	0	0
T10	1110	0	0	0
T11	3486	0	0	0
T13	1398	0	0	0
T14	69457	9197	0	0
T15	0	119685	0	0
T19	0	16715	0	0
T28	0	41471	0	0
T30	0	40	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	398171233	0	0
T1	6053	5999	0	0
T2	401241	401225	0	0
T3	157138	156998	0	0
T4	129462	104243	0	0
T5	588463	588373	0	0
T6	73604	73427	0	0
T10	1110	923	0	0
T11	3486	2781	0	0
T13	1398	1339	0	0
T14	69457	69405	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	398171233	0	0
T1	6053	5999	0	0
T2	401241	401225	0	0
T3	157138	156998	0	0
T4	129462	104243	0	0
T5	588463	588373	0	0
T6	73604	73427	0	0
T10	1110	923	0	0
T11	3486	2781	0	0
T13	1398	1339	0	0
T14	69457	69405	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	96477571	0	0
T1	6053	1999	0	0
T2	401241	127897	0	0
T3	157138	21686	0	0
T4	129462	0	0	0
T5	588463	279871	0	0
T6	73604	8325	0	0
T10	1110	0	0	0
T11	3486	0	0	0
T13	1398	0	0	0
T14	69457	9197	0	0
T15	0	119685	0	0
T19	0	16715	0	0
T28	0	41471	0	0
T30	0	40	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	42650636	0	0
T1	6053	162	0	0
T2	401241	524288	0	0
T3	157138	34308	0	0
T4	129462	0	0	0
T5	588463	584	0	0
T6	73604	25755	0	0
T10	1110	0	0	0
T11	3486	0	0	0
T13	1398	0	0	0
T14	69457	27269	0	0
T15	0	45040	0	0
T19	0	46400	0	0
T28	0	30227	0	0
T30	0	61	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	102589396	0	0
T1	6053	2037	0	0
T2	401241	127897	0	0
T3	157138	24208	0	0
T4	129462	0	0	0
T5	588463	279871	0	0
T6	73604	9837	0	0
T10	1110	0	0	0
T11	3486	0	0	0
T13	1398	0	0	0
T14	69457	9936	0	0
T15	0	148816	0	0
T19	0	17623	0	0
T28	0	47335	0	0
T30	0	40	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	96477571	0	0
T1	6053	1999	0	0
T2	401241	127897	0	0
T3	157138	21686	0	0
T4	129462	0	0	0
T5	588463	279871	0	0
T6	73604	8325	0	0
T10	1110	0	0	0
T11	3486	0	0	0
T13	1398	0	0	0
T14	69457	9197	0	0
T15	0	119685	0	0
T19	0	16715	0	0
T28	0	41471	0	0
T30	0	40	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	96477571	0	0
T1	6053	1999	0	0
T2	401241	127897	0	0
T3	157138	21686	0	0
T4	129462	0	0	0
T5	588463	279871	0	0
T6	73604	8325	0	0
T10	1110	0	0	0
T11	3486	0	0	0
T13	1398	0	0	0
T14	69457	9197	0	0
T15	0	119685	0	0
T19	0	16715	0	0
T28	0	41471	0	0
T30	0	40	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	102589396	0	0
T1	6053	2037	0	0
T2	401241	127897	0	0
T3	157138	24208	0	0
T4	129462	0	0	0
T5	588463	279871	0	0
T6	73604	9837	0	0
T10	1110	0	0	0
T11	3486	0	0	0
T13	1398	0	0	0
T14	69457	9936	0	0
T15	0	148816	0	0
T19	0	17623	0	0
T28	0	47335	0	0
T30	0	40	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399075656	398171233	0	0
T1	6053	5999	0	0
T2	401241	401225	0	0
T3	157138	156998	0	0
T4	129462	104243	0	0
T5	588463	588373	0	0
T6	73604	73427	0	0
T10	1110	923	0	0
T11	3486	2781	0	0
T13	1398	1339	0	0
T14	69457	69405	0	0