| T1080 |
/workspace/coverage/default/67.flash_ctrl_otp_reset.1147483363 |
|
|
Aug 13 06:23:28 PM PDT 24 |
Aug 13 06:25:43 PM PDT 24 |
129826200 ps |
| T1081 |
/workspace/coverage/default/38.flash_ctrl_hw_sec_otp.1648619074 |
|
|
Aug 13 06:21:42 PM PDT 24 |
Aug 13 06:22:55 PM PDT 24 |
2283423200 ps |
| T1082 |
/workspace/coverage/default/6.flash_ctrl_re_evict.586178051 |
|
|
Aug 13 06:17:16 PM PDT 24 |
Aug 13 06:17:51 PM PDT 24 |
187724000 ps |
| T1083 |
/workspace/coverage/default/23.flash_ctrl_disable.2255683470 |
|
|
Aug 13 06:20:26 PM PDT 24 |
Aug 13 06:20:48 PM PDT 24 |
16778100 ps |
| T1084 |
/workspace/coverage/default/24.flash_ctrl_prog_reset.1290482854 |
|
|
Aug 13 06:20:34 PM PDT 24 |
Aug 13 06:20:47 PM PDT 24 |
67195400 ps |
| T1085 |
/workspace/coverage/default/9.flash_ctrl_intr_wr.4119952684 |
|
|
Aug 13 06:18:05 PM PDT 24 |
Aug 13 06:19:14 PM PDT 24 |
7175705800 ps |
| T1086 |
/workspace/coverage/default/10.flash_ctrl_intr_rd_slow_flash.4137027345 |
|
|
Aug 13 06:18:14 PM PDT 24 |
Aug 13 06:22:42 PM PDT 24 |
40831434200 ps |
| T1087 |
/workspace/coverage/default/1.flash_ctrl_integrity.308262238 |
|
|
Aug 13 06:14:42 PM PDT 24 |
Aug 13 06:24:31 PM PDT 24 |
3593898200 ps |
| T1088 |
/workspace/coverage/default/9.flash_ctrl_error_mp.573503226 |
|
|
Aug 13 06:17:57 PM PDT 24 |
Aug 13 06:59:06 PM PDT 24 |
10010245900 ps |
| T1089 |
/workspace/coverage/default/1.flash_ctrl_config_regwen.2002413571 |
|
|
Aug 13 06:15:00 PM PDT 24 |
Aug 13 06:15:14 PM PDT 24 |
29271200 ps |
| T1090 |
/workspace/coverage/default/2.flash_ctrl_wo.1749493564 |
|
|
Aug 13 06:15:08 PM PDT 24 |
Aug 13 06:18:44 PM PDT 24 |
2643691000 ps |
| T188 |
/workspace/coverage/default/1.flash_ctrl_rma_err.1537409492 |
|
|
Aug 13 06:14:58 PM PDT 24 |
Aug 13 06:29:51 PM PDT 24 |
83806140100 ps |
| T1091 |
/workspace/coverage/default/13.flash_ctrl_hw_rma_reset.2866452132 |
|
|
Aug 13 06:18:45 PM PDT 24 |
Aug 13 06:35:04 PM PDT 24 |
180176064300 ps |
| T1092 |
/workspace/coverage/default/8.flash_ctrl_disable.1811450362 |
|
|
Aug 13 06:17:56 PM PDT 24 |
Aug 13 06:18:18 PM PDT 24 |
20270300 ps |
| T1093 |
/workspace/coverage/default/3.flash_ctrl_fetch_code.766000823 |
|
|
Aug 13 06:15:42 PM PDT 24 |
Aug 13 06:16:03 PM PDT 24 |
271329400 ps |
| T1094 |
/workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.1211114555 |
|
|
Aug 13 06:18:30 PM PDT 24 |
Aug 13 06:18:44 PM PDT 24 |
15680300 ps |
| T1095 |
/workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.2776488162 |
|
|
Aug 13 06:18:08 PM PDT 24 |
Aug 13 06:18:21 PM PDT 24 |
27367600 ps |
| T90 |
/workspace/coverage/default/4.flash_ctrl_phy_ack_consistency.1170724140 |
|
|
Aug 13 06:16:41 PM PDT 24 |
Aug 13 06:16:55 PM PDT 24 |
29446200 ps |
| T167 |
/workspace/coverage/default/1.flash_ctrl_mid_op_rst.1474524342 |
|
|
Aug 13 06:14:34 PM PDT 24 |
Aug 13 06:15:45 PM PDT 24 |
3302657200 ps |
| T1096 |
/workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.2490602486 |
|
|
Aug 13 06:18:06 PM PDT 24 |
Aug 13 06:20:15 PM PDT 24 |
10012363400 ps |
| T1097 |
/workspace/coverage/default/5.flash_ctrl_error_prog_win.3532280845 |
|
|
Aug 13 06:16:39 PM PDT 24 |
Aug 13 06:31:35 PM PDT 24 |
384074500 ps |
| T1098 |
/workspace/coverage/default/63.flash_ctrl_otp_reset.66373284 |
|
|
Aug 13 06:23:18 PM PDT 24 |
Aug 13 06:25:31 PM PDT 24 |
149314600 ps |
| T209 |
/workspace/coverage/default/7.flash_ctrl_rw_derr.3401880106 |
|
|
Aug 13 06:17:39 PM PDT 24 |
Aug 13 06:20:58 PM PDT 24 |
7935263000 ps |
| T1099 |
/workspace/coverage/default/22.flash_ctrl_otp_reset.3490954068 |
|
|
Aug 13 06:20:22 PM PDT 24 |
Aug 13 06:22:12 PM PDT 24 |
147804800 ps |
| T1100 |
/workspace/coverage/default/38.flash_ctrl_intr_rd.4167223201 |
|
|
Aug 13 06:21:43 PM PDT 24 |
Aug 13 06:24:01 PM PDT 24 |
795192600 ps |
| T1101 |
/workspace/coverage/default/7.flash_ctrl_hw_read_seed_err.845444577 |
|
|
Aug 13 06:17:36 PM PDT 24 |
Aug 13 06:17:50 PM PDT 24 |
15166600 ps |
| T1102 |
/workspace/coverage/default/0.flash_ctrl_rw.2549625504 |
|
|
Aug 13 06:13:52 PM PDT 24 |
Aug 13 06:21:09 PM PDT 24 |
4789673100 ps |
| T395 |
/workspace/coverage/default/2.flash_ctrl_re_evict.620824042 |
|
|
Aug 13 06:15:25 PM PDT 24 |
Aug 13 06:15:59 PM PDT 24 |
353612800 ps |
| T1103 |
/workspace/coverage/default/1.flash_ctrl_serr_counter.10987695 |
|
|
Aug 13 06:14:34 PM PDT 24 |
Aug 13 06:15:50 PM PDT 24 |
1475552100 ps |
| T1104 |
/workspace/coverage/default/11.flash_ctrl_lcmgr_intg.1102251084 |
|
|
Aug 13 06:18:31 PM PDT 24 |
Aug 13 06:18:44 PM PDT 24 |
15996200 ps |
| T1105 |
/workspace/coverage/default/5.flash_ctrl_rw_serr.2064599384 |
|
|
Aug 13 06:16:52 PM PDT 24 |
Aug 13 06:21:47 PM PDT 24 |
2304962300 ps |
| T1106 |
/workspace/coverage/default/31.flash_ctrl_alert_test.2741273563 |
|
|
Aug 13 06:21:12 PM PDT 24 |
Aug 13 06:21:26 PM PDT 24 |
36235400 ps |
| T1107 |
/workspace/coverage/default/19.flash_ctrl_wo.3928198635 |
|
|
Aug 13 06:19:56 PM PDT 24 |
Aug 13 06:23:19 PM PDT 24 |
12694666800 ps |
| T1108 |
/workspace/coverage/default/2.flash_ctrl_rd_intg.4050125308 |
|
|
Aug 13 06:15:23 PM PDT 24 |
Aug 13 06:15:55 PM PDT 24 |
66010200 ps |
| T1109 |
/workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.2883978822 |
|
|
Aug 13 06:19:33 PM PDT 24 |
Aug 13 06:19:46 PM PDT 24 |
26753100 ps |
| T1110 |
/workspace/coverage/default/62.flash_ctrl_otp_reset.2201479025 |
|
|
Aug 13 06:23:17 PM PDT 24 |
Aug 13 06:25:32 PM PDT 24 |
40498900 ps |
| T1111 |
/workspace/coverage/default/13.flash_ctrl_wo.1386546026 |
|
|
Aug 13 06:18:54 PM PDT 24 |
Aug 13 06:21:51 PM PDT 24 |
9929258700 ps |
| T1112 |
/workspace/coverage/default/25.flash_ctrl_connect.2863073860 |
|
|
Aug 13 06:20:43 PM PDT 24 |
Aug 13 06:20:59 PM PDT 24 |
54428700 ps |
| T1113 |
/workspace/coverage/default/1.flash_ctrl_hw_rma_reset.2862987751 |
|
|
Aug 13 06:14:25 PM PDT 24 |
Aug 13 06:29:05 PM PDT 24 |
160198177100 ps |
| T1114 |
/workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.3470307979 |
|
|
Aug 13 06:16:04 PM PDT 24 |
Aug 13 06:17:11 PM PDT 24 |
10019569700 ps |
| T1115 |
/workspace/coverage/default/12.flash_ctrl_wo.451320302 |
|
|
Aug 13 06:18:40 PM PDT 24 |
Aug 13 06:22:01 PM PDT 24 |
11167069200 ps |
| T1116 |
/workspace/coverage/default/0.flash_ctrl_connect.2148069663 |
|
|
Aug 13 06:14:12 PM PDT 24 |
Aug 13 06:14:28 PM PDT 24 |
16200700 ps |
| T264 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.3116297983 |
|
|
Aug 13 06:30:39 PM PDT 24 |
Aug 13 06:30:53 PM PDT 24 |
120407100 ps |
| T265 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.3225472834 |
|
|
Aug 13 06:30:29 PM PDT 24 |
Aug 13 06:30:43 PM PDT 24 |
17131300 ps |
| T59 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.3197408500 |
|
|
Aug 13 06:30:25 PM PDT 24 |
Aug 13 06:30:44 PM PDT 24 |
85824600 ps |
| T1117 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1091434032 |
|
|
Aug 13 06:30:03 PM PDT 24 |
Aug 13 06:30:17 PM PDT 24 |
17396300 ps |
| T60 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1984241457 |
|
|
Aug 13 06:29:54 PM PDT 24 |
Aug 13 06:30:11 PM PDT 24 |
68573400 ps |
| T1118 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2262654258 |
|
|
Aug 13 06:30:27 PM PDT 24 |
Aug 13 06:30:43 PM PDT 24 |
18789700 ps |
| T61 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.1781979695 |
|
|
Aug 13 06:30:14 PM PDT 24 |
Aug 13 06:30:48 PM PDT 24 |
891529400 ps |
| T101 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3175140590 |
|
|
Aug 13 06:30:30 PM PDT 24 |
Aug 13 06:38:20 PM PDT 24 |
1662281200 ps |
| T266 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.2123437188 |
|
|
Aug 13 06:30:29 PM PDT 24 |
Aug 13 06:30:43 PM PDT 24 |
14868700 ps |
| T312 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3797173541 |
|
|
Aug 13 06:30:28 PM PDT 24 |
Aug 13 06:30:41 PM PDT 24 |
18530400 ps |
| T1119 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2681648976 |
|
|
Aug 13 06:30:12 PM PDT 24 |
Aug 13 06:30:25 PM PDT 24 |
23404400 ps |
| T102 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.1748406077 |
|
|
Aug 13 06:30:04 PM PDT 24 |
Aug 13 06:30:19 PM PDT 24 |
50347800 ps |
| T313 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.1573399719 |
|
|
Aug 13 06:30:25 PM PDT 24 |
Aug 13 06:30:39 PM PDT 24 |
33033500 ps |
| T314 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.4005176492 |
|
|
Aug 13 06:30:24 PM PDT 24 |
Aug 13 06:30:37 PM PDT 24 |
71453600 ps |
| T1120 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.3269806088 |
|
|
Aug 13 06:30:19 PM PDT 24 |
Aug 13 06:30:35 PM PDT 24 |
16661600 ps |
| T104 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1576745865 |
|
|
Aug 13 06:30:18 PM PDT 24 |
Aug 13 06:30:33 PM PDT 24 |
62289100 ps |
| T315 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3211969121 |
|
|
Aug 13 06:30:34 PM PDT 24 |
Aug 13 06:30:48 PM PDT 24 |
45018100 ps |
| T103 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.285856793 |
|
|
Aug 13 06:30:02 PM PDT 24 |
Aug 13 06:30:22 PM PDT 24 |
173659000 ps |
| T1121 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3508688644 |
|
|
Aug 13 06:30:19 PM PDT 24 |
Aug 13 06:30:36 PM PDT 24 |
46691900 ps |
| T244 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.321247308 |
|
|
Aug 13 06:30:12 PM PDT 24 |
Aug 13 06:30:30 PM PDT 24 |
37837100 ps |
| T1122 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2485290323 |
|
|
Aug 13 06:30:05 PM PDT 24 |
Aug 13 06:30:21 PM PDT 24 |
40840800 ps |
| T1123 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.1360265313 |
|
|
Aug 13 06:30:21 PM PDT 24 |
Aug 13 06:30:36 PM PDT 24 |
18695100 ps |
| T1124 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3736441532 |
|
|
Aug 13 06:30:07 PM PDT 24 |
Aug 13 06:30:26 PM PDT 24 |
51239100 ps |
| T1125 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.629497574 |
|
|
Aug 13 06:30:19 PM PDT 24 |
Aug 13 06:30:34 PM PDT 24 |
29237500 ps |
| T1126 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.533094301 |
|
|
Aug 13 06:30:28 PM PDT 24 |
Aug 13 06:30:44 PM PDT 24 |
15694600 ps |
| T245 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2386230802 |
|
|
Aug 13 06:30:05 PM PDT 24 |
Aug 13 06:30:23 PM PDT 24 |
43891700 ps |
| T316 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.4233341334 |
|
|
Aug 13 06:30:29 PM PDT 24 |
Aug 13 06:30:42 PM PDT 24 |
52365900 ps |
| T262 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3875486212 |
|
|
Aug 13 06:30:06 PM PDT 24 |
Aug 13 06:30:33 PM PDT 24 |
340233900 ps |
| T317 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2416939045 |
|
|
Aug 13 06:30:27 PM PDT 24 |
Aug 13 06:30:40 PM PDT 24 |
24160800 ps |
| T204 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2930179642 |
|
|
Aug 13 06:30:08 PM PDT 24 |
Aug 13 06:30:25 PM PDT 24 |
563605400 ps |
| T238 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.4012415651 |
|
|
Aug 13 06:30:15 PM PDT 24 |
Aug 13 06:38:03 PM PDT 24 |
337063600 ps |
| T233 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3624143479 |
|
|
Aug 13 06:30:05 PM PDT 24 |
Aug 13 06:30:22 PM PDT 24 |
44769000 ps |
| T205 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.3388433169 |
|
|
Aug 13 06:30:02 PM PDT 24 |
Aug 13 06:45:16 PM PDT 24 |
720153300 ps |
| T206 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.1004080138 |
|
|
Aug 13 06:30:25 PM PDT 24 |
Aug 13 06:30:41 PM PDT 24 |
56283300 ps |
| T246 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.2986500049 |
|
|
Aug 13 06:30:02 PM PDT 24 |
Aug 13 06:30:19 PM PDT 24 |
36248400 ps |
| T1127 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3170101990 |
|
|
Aug 13 06:30:29 PM PDT 24 |
Aug 13 06:30:42 PM PDT 24 |
14839600 ps |
| T1128 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2571952872 |
|
|
Aug 13 06:30:15 PM PDT 24 |
Aug 13 06:30:31 PM PDT 24 |
45993700 ps |
| T318 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.3876445858 |
|
|
Aug 13 06:30:16 PM PDT 24 |
Aug 13 06:30:29 PM PDT 24 |
16818600 ps |
| T1129 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3190462106 |
|
|
Aug 13 06:30:27 PM PDT 24 |
Aug 13 06:30:41 PM PDT 24 |
58696600 ps |
| T1130 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.1507945029 |
|
|
Aug 13 06:30:04 PM PDT 24 |
Aug 13 06:30:18 PM PDT 24 |
13240200 ps |
| T1131 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.428032244 |
|
|
Aug 13 06:30:25 PM PDT 24 |
Aug 13 06:30:40 PM PDT 24 |
28881800 ps |
| T247 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2485378152 |
|
|
Aug 13 06:30:05 PM PDT 24 |
Aug 13 06:30:24 PM PDT 24 |
84332900 ps |
| T1132 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1617453164 |
|
|
Aug 13 06:30:01 PM PDT 24 |
Aug 13 06:30:15 PM PDT 24 |
14361100 ps |
| T248 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.334233015 |
|
|
Aug 13 06:30:23 PM PDT 24 |
Aug 13 06:30:42 PM PDT 24 |
86096500 ps |
| T249 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1284666467 |
|
|
Aug 13 06:30:18 PM PDT 24 |
Aug 13 06:30:37 PM PDT 24 |
140996600 ps |
| T234 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3656238463 |
|
|
Aug 13 06:30:12 PM PDT 24 |
Aug 13 06:30:28 PM PDT 24 |
41961900 ps |
| T235 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.3858843782 |
|
|
Aug 13 06:30:18 PM PDT 24 |
Aug 13 06:30:35 PM PDT 24 |
82628700 ps |
| T1133 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.1981563351 |
|
|
Aug 13 06:30:25 PM PDT 24 |
Aug 13 06:30:38 PM PDT 24 |
128416000 ps |
| T1134 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.1026278960 |
|
|
Aug 13 06:30:18 PM PDT 24 |
Aug 13 06:30:32 PM PDT 24 |
11365200 ps |
| T236 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3473732545 |
|
|
Aug 13 06:30:01 PM PDT 24 |
Aug 13 06:30:19 PM PDT 24 |
202474800 ps |
| T1135 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.1513919455 |
|
|
Aug 13 06:30:03 PM PDT 24 |
Aug 13 06:30:49 PM PDT 24 |
81152500 ps |
| T237 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.511724271 |
|
|
Aug 13 06:30:18 PM PDT 24 |
Aug 13 06:30:38 PM PDT 24 |
47407600 ps |
| T1136 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1044494619 |
|
|
Aug 13 06:30:31 PM PDT 24 |
Aug 13 06:30:44 PM PDT 24 |
39421600 ps |
| T1137 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.2880767515 |
|
|
Aug 13 06:30:31 PM PDT 24 |
Aug 13 06:30:44 PM PDT 24 |
29378900 ps |
| T270 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2232503576 |
|
|
Aug 13 06:30:21 PM PDT 24 |
Aug 13 06:30:42 PM PDT 24 |
69461700 ps |
| T269 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1905311093 |
|
|
Aug 13 06:30:20 PM PDT 24 |
Aug 13 06:30:37 PM PDT 24 |
155464400 ps |
| T271 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3335163356 |
|
|
Aug 13 06:30:08 PM PDT 24 |
Aug 13 06:42:50 PM PDT 24 |
346288600 ps |
| T1138 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.2930347274 |
|
|
Aug 13 06:30:03 PM PDT 24 |
Aug 13 06:30:49 PM PDT 24 |
2972919000 ps |
| T1139 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.3296381699 |
|
|
Aug 13 06:30:39 PM PDT 24 |
Aug 13 06:30:53 PM PDT 24 |
47959100 ps |
| T1140 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.2838101309 |
|
|
Aug 13 06:30:38 PM PDT 24 |
Aug 13 06:30:52 PM PDT 24 |
15855800 ps |
| T250 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1806137866 |
|
|
Aug 13 06:30:24 PM PDT 24 |
Aug 13 06:30:41 PM PDT 24 |
37297500 ps |
| T1141 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.2904645754 |
|
|
Aug 13 06:30:09 PM PDT 24 |
Aug 13 06:30:26 PM PDT 24 |
36409800 ps |
| T334 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.524655739 |
|
|
Aug 13 06:30:29 PM PDT 24 |
Aug 13 06:45:42 PM PDT 24 |
1323687500 ps |
| T1142 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3288910341 |
|
|
Aug 13 06:30:02 PM PDT 24 |
Aug 13 06:30:33 PM PDT 24 |
24987900 ps |
| T1143 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2594910521 |
|
|
Aug 13 06:30:31 PM PDT 24 |
Aug 13 06:30:45 PM PDT 24 |
25222800 ps |
| T251 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1720272367 |
|
|
Aug 13 06:30:24 PM PDT 24 |
Aug 13 06:30:41 PM PDT 24 |
159560100 ps |
| T333 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2558363201 |
|
|
Aug 13 06:30:06 PM PDT 24 |
Aug 13 06:45:25 PM PDT 24 |
1966149100 ps |
| T1144 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.263647224 |
|
|
Aug 13 06:30:30 PM PDT 24 |
Aug 13 06:30:43 PM PDT 24 |
104605100 ps |
| T1145 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.4279645406 |
|
|
Aug 13 06:30:28 PM PDT 24 |
Aug 13 06:30:44 PM PDT 24 |
226316500 ps |
| T240 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.2312951986 |
|
|
Aug 13 06:30:00 PM PDT 24 |
Aug 13 06:30:14 PM PDT 24 |
25499300 ps |
| T1146 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.3198897403 |
|
|
Aug 13 06:30:06 PM PDT 24 |
Aug 13 06:30:21 PM PDT 24 |
14321000 ps |
| T263 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.2780498347 |
|
|
Aug 13 06:30:33 PM PDT 24 |
Aug 13 06:30:52 PM PDT 24 |
128016000 ps |
| T275 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.1731771803 |
|
|
Aug 13 06:30:23 PM PDT 24 |
Aug 13 06:30:43 PM PDT 24 |
461997200 ps |
| T1147 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.3315913498 |
|
|
Aug 13 06:30:20 PM PDT 24 |
Aug 13 06:30:33 PM PDT 24 |
15055200 ps |
| T293 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3694110509 |
|
|
Aug 13 06:29:56 PM PDT 24 |
Aug 13 06:37:37 PM PDT 24 |
1613792100 ps |
| T299 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.3483498833 |
|
|
Aug 13 06:30:23 PM PDT 24 |
Aug 13 06:30:40 PM PDT 24 |
111863500 ps |
| T1148 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.758000009 |
|
|
Aug 13 06:30:35 PM PDT 24 |
Aug 13 06:30:49 PM PDT 24 |
24907400 ps |
| T1149 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2375937558 |
|
|
Aug 13 06:30:06 PM PDT 24 |
Aug 13 06:30:24 PM PDT 24 |
177198900 ps |
| T1150 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.3920711075 |
|
|
Aug 13 06:30:22 PM PDT 24 |
Aug 13 06:30:37 PM PDT 24 |
261146600 ps |
| T1151 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.923482268 |
|
|
Aug 13 06:30:02 PM PDT 24 |
Aug 13 06:30:16 PM PDT 24 |
23883600 ps |
| T1152 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.3245423016 |
|
|
Aug 13 06:30:23 PM PDT 24 |
Aug 13 06:30:43 PM PDT 24 |
43967700 ps |
| T1153 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1426862839 |
|
|
Aug 13 06:30:27 PM PDT 24 |
Aug 13 06:30:41 PM PDT 24 |
22280500 ps |
| T294 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.2103751880 |
|
|
Aug 13 06:30:05 PM PDT 24 |
Aug 13 06:30:25 PM PDT 24 |
1311075000 ps |
| T1154 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.4071151096 |
|
|
Aug 13 06:30:03 PM PDT 24 |
Aug 13 06:30:17 PM PDT 24 |
17197400 ps |
| T1155 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.4051576232 |
|
|
Aug 13 06:30:22 PM PDT 24 |
Aug 13 06:30:53 PM PDT 24 |
175481800 ps |
| T276 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3321868757 |
|
|
Aug 13 06:29:54 PM PDT 24 |
Aug 13 06:30:13 PM PDT 24 |
54367700 ps |
| T1156 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.1710022393 |
|
|
Aug 13 06:30:05 PM PDT 24 |
Aug 13 06:30:42 PM PDT 24 |
2277447900 ps |
| T335 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.2963900123 |
|
|
Aug 13 06:30:06 PM PDT 24 |
Aug 13 06:42:57 PM PDT 24 |
1448038000 ps |
| T1157 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1233972202 |
|
|
Aug 13 06:30:13 PM PDT 24 |
Aug 13 06:30:34 PM PDT 24 |
629458600 ps |
| T1158 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.2521076164 |
|
|
Aug 13 06:30:07 PM PDT 24 |
Aug 13 06:30:23 PM PDT 24 |
12280500 ps |
| T1159 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.93208456 |
|
|
Aug 13 06:30:08 PM PDT 24 |
Aug 13 06:30:27 PM PDT 24 |
114044400 ps |
| T1160 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.2232190435 |
|
|
Aug 13 06:30:02 PM PDT 24 |
Aug 13 06:30:16 PM PDT 24 |
48847100 ps |
| T1161 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.3457140931 |
|
|
Aug 13 06:30:02 PM PDT 24 |
Aug 13 06:30:42 PM PDT 24 |
2535196400 ps |
| T1162 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.646296565 |
|
|
Aug 13 06:30:04 PM PDT 24 |
Aug 13 06:30:18 PM PDT 24 |
69879600 ps |
| T1163 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2379186805 |
|
|
Aug 13 06:30:21 PM PDT 24 |
Aug 13 06:30:37 PM PDT 24 |
49089500 ps |
| T1164 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.2126822315 |
|
|
Aug 13 06:30:28 PM PDT 24 |
Aug 13 06:30:42 PM PDT 24 |
28387300 ps |
| T267 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.2260061559 |
|
|
Aug 13 06:30:06 PM PDT 24 |
Aug 13 06:30:24 PM PDT 24 |
163023600 ps |
| T1165 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.327049985 |
|
|
Aug 13 06:30:22 PM PDT 24 |
Aug 13 06:30:36 PM PDT 24 |
45496400 ps |
| T337 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.2769460788 |
|
|
Aug 13 06:30:20 PM PDT 24 |
Aug 13 06:36:48 PM PDT 24 |
691742900 ps |
| T273 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.4025310916 |
|
|
Aug 13 06:30:14 PM PDT 24 |
Aug 13 06:30:30 PM PDT 24 |
287934000 ps |
| T1166 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.4053007657 |
|
|
Aug 13 06:30:21 PM PDT 24 |
Aug 13 06:30:35 PM PDT 24 |
16990100 ps |
| T295 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.1559397686 |
|
|
Aug 13 06:30:10 PM PDT 24 |
Aug 13 06:30:45 PM PDT 24 |
200672000 ps |
| T1167 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.2116699718 |
|
|
Aug 13 06:30:34 PM PDT 24 |
Aug 13 06:30:48 PM PDT 24 |
96331200 ps |
| T296 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2363918090 |
|
|
Aug 13 06:30:15 PM PDT 24 |
Aug 13 06:30:29 PM PDT 24 |
137062700 ps |
| T1168 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.4039459064 |
|
|
Aug 13 06:30:08 PM PDT 24 |
Aug 13 06:30:26 PM PDT 24 |
68666800 ps |
| T1169 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.2208981377 |
|
|
Aug 13 06:30:01 PM PDT 24 |
Aug 13 06:31:07 PM PDT 24 |
4146035700 ps |
| T1170 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.1444375511 |
|
|
Aug 13 06:30:36 PM PDT 24 |
Aug 13 06:30:49 PM PDT 24 |
108026300 ps |
| T297 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2294987161 |
|
|
Aug 13 06:30:23 PM PDT 24 |
Aug 13 06:38:03 PM PDT 24 |
1581393100 ps |
| T1171 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2737420702 |
|
|
Aug 13 06:30:03 PM PDT 24 |
Aug 13 06:30:16 PM PDT 24 |
13217100 ps |
| T1172 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2511431998 |
|
|
Aug 13 06:30:27 PM PDT 24 |
Aug 13 06:30:42 PM PDT 24 |
63915100 ps |
| T1173 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.4246227277 |
|
|
Aug 13 06:30:18 PM PDT 24 |
Aug 13 06:30:32 PM PDT 24 |
26599400 ps |
| T1174 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3643160692 |
|
|
Aug 13 06:30:07 PM PDT 24 |
Aug 13 06:30:25 PM PDT 24 |
88923800 ps |
| T1175 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.4152223154 |
|
|
Aug 13 06:30:05 PM PDT 24 |
Aug 13 06:30:19 PM PDT 24 |
15229100 ps |
| T1176 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3986460037 |
|
|
Aug 13 06:30:34 PM PDT 24 |
Aug 13 06:30:48 PM PDT 24 |
126948100 ps |
| T1177 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.1598570619 |
|
|
Aug 13 06:30:06 PM PDT 24 |
Aug 13 06:30:20 PM PDT 24 |
81946200 ps |
| T1178 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1163296395 |
|
|
Aug 13 06:30:27 PM PDT 24 |
Aug 13 06:30:42 PM PDT 24 |
36742500 ps |
| T1179 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2376587637 |
|
|
Aug 13 06:30:12 PM PDT 24 |
Aug 13 06:30:28 PM PDT 24 |
21095700 ps |
| T1180 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1845089375 |
|
|
Aug 13 06:30:21 PM PDT 24 |
Aug 13 06:30:37 PM PDT 24 |
14632200 ps |
| T1181 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.783279731 |
|
|
Aug 13 06:30:33 PM PDT 24 |
Aug 13 06:30:53 PM PDT 24 |
45783700 ps |
| T1182 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2178831212 |
|
|
Aug 13 06:30:24 PM PDT 24 |
Aug 13 06:30:40 PM PDT 24 |
36262000 ps |
| T1183 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3676464355 |
|
|
Aug 13 06:30:17 PM PDT 24 |
Aug 13 06:31:37 PM PDT 24 |
9096265700 ps |
| T1184 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3376636989 |
|
|
Aug 13 06:30:02 PM PDT 24 |
Aug 13 06:30:20 PM PDT 24 |
90648800 ps |
| T1185 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.969664555 |
|
|
Aug 13 06:30:25 PM PDT 24 |
Aug 13 06:38:10 PM PDT 24 |
343880300 ps |
| T1186 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2486324871 |
|
|
Aug 13 06:30:06 PM PDT 24 |
Aug 13 06:31:02 PM PDT 24 |
1818225100 ps |
| T1187 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3352588028 |
|
|
Aug 13 06:30:03 PM PDT 24 |
Aug 13 06:30:21 PM PDT 24 |
642391100 ps |
| T1188 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.3549390861 |
|
|
Aug 13 06:30:25 PM PDT 24 |
Aug 13 06:30:38 PM PDT 24 |
16012900 ps |
| T298 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3817818814 |
|
|
Aug 13 06:30:23 PM PDT 24 |
Aug 13 06:38:08 PM PDT 24 |
414917600 ps |
| T1189 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.1489294036 |
|
|
Aug 13 06:30:16 PM PDT 24 |
Aug 13 06:30:35 PM PDT 24 |
728418600 ps |
| T1190 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.657311003 |
|
|
Aug 13 06:30:21 PM PDT 24 |
Aug 13 06:30:34 PM PDT 24 |
43354500 ps |
| T1191 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.4096681 |
|
|
Aug 13 06:30:19 PM PDT 24 |
Aug 13 06:30:33 PM PDT 24 |
45880600 ps |
| T1192 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1906662608 |
|
|
Aug 13 06:30:02 PM PDT 24 |
Aug 13 06:30:39 PM PDT 24 |
1790384900 ps |
| T1193 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.2875396929 |
|
|
Aug 13 06:30:19 PM PDT 24 |
Aug 13 06:30:36 PM PDT 24 |
14087700 ps |
| T1194 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.200871820 |
|
|
Aug 13 06:30:09 PM PDT 24 |
Aug 13 06:30:23 PM PDT 24 |
16472600 ps |
| T300 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.276360797 |
|
|
Aug 13 06:30:24 PM PDT 24 |
Aug 13 06:30:42 PM PDT 24 |
198854700 ps |
| T1195 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.3538017465 |
|
|
Aug 13 06:30:22 PM PDT 24 |
Aug 13 06:30:40 PM PDT 24 |
71190100 ps |
| T241 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.647105344 |
|
|
Aug 13 06:30:00 PM PDT 24 |
Aug 13 06:30:15 PM PDT 24 |
60665000 ps |
| T1196 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.3264655265 |
|
|
Aug 13 06:30:50 PM PDT 24 |
Aug 13 06:31:04 PM PDT 24 |
14720800 ps |
| T305 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.3959195860 |
|
|
Aug 13 06:30:23 PM PDT 24 |
Aug 13 06:30:38 PM PDT 24 |
325311100 ps |
| T1197 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2408480236 |
|
|
Aug 13 06:30:37 PM PDT 24 |
Aug 13 06:30:51 PM PDT 24 |
102602800 ps |
| T332 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1061635921 |
|
|
Aug 13 06:30:10 PM PDT 24 |
Aug 13 06:30:27 PM PDT 24 |
46681200 ps |
| T268 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.663824469 |
|
|
Aug 13 06:30:22 PM PDT 24 |
Aug 13 06:30:48 PM PDT 24 |
68477700 ps |
| T301 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.3636194260 |
|
|
Aug 13 06:30:05 PM PDT 24 |
Aug 13 06:30:35 PM PDT 24 |
118870800 ps |
| T1198 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.1426748276 |
|
|
Aug 13 06:30:05 PM PDT 24 |
Aug 13 06:37:51 PM PDT 24 |
815253600 ps |
| T1199 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.2823677297 |
|
|
Aug 13 06:30:39 PM PDT 24 |
Aug 13 06:30:53 PM PDT 24 |
47522100 ps |
| T1200 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.563896980 |
|
|
Aug 13 06:30:05 PM PDT 24 |
Aug 13 06:30:25 PM PDT 24 |
113031500 ps |
| T1201 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.1840642567 |
|
|
Aug 13 06:29:57 PM PDT 24 |
Aug 13 06:30:13 PM PDT 24 |
34380900 ps |
| T272 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.317672088 |
|
|
Aug 13 06:30:08 PM PDT 24 |
Aug 13 06:30:26 PM PDT 24 |
149830500 ps |
| T1202 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.176473381 |
|
|
Aug 13 06:30:33 PM PDT 24 |
Aug 13 06:30:46 PM PDT 24 |
15182700 ps |
| T302 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.581392482 |
|
|
Aug 13 06:30:29 PM PDT 24 |
Aug 13 06:30:46 PM PDT 24 |
338399400 ps |
| T303 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.332010770 |
|
|
Aug 13 06:30:16 PM PDT 24 |
Aug 13 06:30:35 PM PDT 24 |
243861300 ps |
| T1203 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.4119259063 |
|
|
Aug 13 06:30:30 PM PDT 24 |
Aug 13 06:30:47 PM PDT 24 |
37563400 ps |
| T1204 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2797696243 |
|
|
Aug 13 06:30:07 PM PDT 24 |
Aug 13 06:30:21 PM PDT 24 |
15431100 ps |
| T1205 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.803195433 |
|
|
Aug 13 06:30:26 PM PDT 24 |
Aug 13 06:30:43 PM PDT 24 |
20322900 ps |
| T1206 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.3607028211 |
|
|
Aug 13 06:30:05 PM PDT 24 |
Aug 13 06:30:19 PM PDT 24 |
186265300 ps |
| T1207 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.4057871711 |
|
|
Aug 13 06:30:06 PM PDT 24 |
Aug 13 06:30:44 PM PDT 24 |
3610474300 ps |
| T1208 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.1325174694 |
|
|
Aug 13 06:30:28 PM PDT 24 |
Aug 13 06:30:42 PM PDT 24 |
62636200 ps |
| T242 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.2414118387 |
|
|
Aug 13 06:30:04 PM PDT 24 |
Aug 13 06:30:18 PM PDT 24 |
23565900 ps |
| T1209 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.2328042620 |
|
|
Aug 13 06:30:06 PM PDT 24 |
Aug 13 06:30:23 PM PDT 24 |
51227200 ps |
| T1210 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3794083927 |
|
|
Aug 13 06:30:22 PM PDT 24 |
Aug 13 06:30:38 PM PDT 24 |
17818600 ps |
| T1211 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.661651535 |
|
|
Aug 13 06:30:00 PM PDT 24 |
Aug 13 06:30:17 PM PDT 24 |
41441300 ps |
| T339 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1147820120 |
|
|
Aug 13 06:30:02 PM PDT 24 |
Aug 13 06:45:13 PM PDT 24 |
1350967300 ps |
| T1212 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.1837093284 |
|
|
Aug 13 06:30:31 PM PDT 24 |
Aug 13 06:30:45 PM PDT 24 |
41729800 ps |
| T336 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.3149387580 |
|
|
Aug 13 06:30:21 PM PDT 24 |
Aug 13 06:36:49 PM PDT 24 |
354691500 ps |
| T1213 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.3960447897 |
|
|
Aug 13 06:30:16 PM PDT 24 |
Aug 13 06:30:33 PM PDT 24 |
37992100 ps |
| T340 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.614763369 |
|
|
Aug 13 06:30:01 PM PDT 24 |
Aug 13 06:45:08 PM PDT 24 |
3071786900 ps |
| T277 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1286794795 |
|
|
Aug 13 06:30:24 PM PDT 24 |
Aug 13 06:36:54 PM PDT 24 |
1755923600 ps |
| T243 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.4117977921 |
|
|
Aug 13 06:30:06 PM PDT 24 |
Aug 13 06:30:20 PM PDT 24 |
19412900 ps |
| T1214 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.971494003 |
|
|
Aug 13 06:30:22 PM PDT 24 |
Aug 13 06:30:35 PM PDT 24 |
17225700 ps |
| T1215 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.1495764471 |
|
|
Aug 13 06:30:31 PM PDT 24 |
Aug 13 06:30:44 PM PDT 24 |
178330600 ps |
| T1216 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.480150784 |
|
|
Aug 13 06:30:34 PM PDT 24 |
Aug 13 06:30:48 PM PDT 24 |
155988500 ps |
| T1217 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.703434196 |
|
|
Aug 13 06:30:02 PM PDT 24 |
Aug 13 06:30:15 PM PDT 24 |
41509700 ps |
| T1218 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.968388237 |
|
|
Aug 13 06:30:22 PM PDT 24 |
Aug 13 06:30:36 PM PDT 24 |
26686300 ps |
| T274 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.3704950496 |
|
|
Aug 13 06:30:28 PM PDT 24 |
Aug 13 06:30:47 PM PDT 24 |
185048800 ps |
| T1219 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.916101290 |
|
|
Aug 13 06:30:07 PM PDT 24 |
Aug 13 06:30:23 PM PDT 24 |
11429500 ps |
| T1220 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2759340286 |
|
|
Aug 13 06:29:58 PM PDT 24 |
Aug 13 06:30:30 PM PDT 24 |
87688200 ps |
| T1221 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.243612858 |
|
|
Aug 13 06:30:46 PM PDT 24 |
Aug 13 06:30:59 PM PDT 24 |
32101200 ps |
| T1222 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1726791048 |
|
|
Aug 13 06:30:07 PM PDT 24 |
Aug 13 06:30:21 PM PDT 24 |
113674000 ps |
| T1223 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1660590517 |
|
|
Aug 13 06:30:20 PM PDT 24 |
Aug 13 06:30:35 PM PDT 24 |
31174600 ps |
| T1224 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2992731845 |
|
|
Aug 13 06:30:25 PM PDT 24 |
Aug 13 06:30:41 PM PDT 24 |
12391100 ps |
| T1225 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.286896809 |
|
|
Aug 13 06:30:21 PM PDT 24 |
Aug 13 06:30:37 PM PDT 24 |
57402900 ps |
| T304 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.4219625224 |
|
|
Aug 13 06:30:06 PM PDT 24 |
Aug 13 06:30:24 PM PDT 24 |
303096000 ps |
| T341 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.1299542713 |
|
|
Aug 13 06:30:20 PM PDT 24 |
Aug 13 06:45:23 PM PDT 24 |
1446906000 ps |
| T1226 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.2203683732 |
|
|
Aug 13 06:30:06 PM PDT 24 |
Aug 13 06:30:20 PM PDT 24 |
13560100 ps |
| T1227 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.3561470863 |
|
|
Aug 13 06:30:21 PM PDT 24 |
Aug 13 06:30:43 PM PDT 24 |
65328600 ps |
| T338 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.2490459487 |
|
|
Aug 13 06:30:25 PM PDT 24 |
Aug 13 06:43:05 PM PDT 24 |
3933223400 ps |
| T1228 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.2948205038 |
|
|
Aug 13 06:30:29 PM PDT 24 |
Aug 13 06:30:46 PM PDT 24 |
87962800 ps |
| T1229 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.4061392145 |
|
|
Aug 13 06:30:06 PM PDT 24 |
Aug 13 06:30:21 PM PDT 24 |
19330100 ps |
| T1230 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1633401351 |
|
|
Aug 13 06:30:31 PM PDT 24 |
Aug 13 06:30:47 PM PDT 24 |
74741400 ps |
| T1231 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.3454228978 |
|
|
Aug 13 06:30:23 PM PDT 24 |
Aug 13 06:30:42 PM PDT 24 |
61594100 ps |
| T1232 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.2181134781 |
|
|
Aug 13 06:30:20 PM PDT 24 |
Aug 13 06:30:34 PM PDT 24 |
15402600 ps |
| T1233 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.1324790437 |
|
|
Aug 13 06:30:05 PM PDT 24 |
Aug 13 06:30:18 PM PDT 24 |
108883100 ps |
| T1234 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.2772623207 |
|
|
Aug 13 06:30:03 PM PDT 24 |
Aug 13 06:30:18 PM PDT 24 |
91830000 ps |
| T1235 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.1275207053 |
|
|
Aug 13 06:30:01 PM PDT 24 |
Aug 13 06:30:15 PM PDT 24 |
18615500 ps |
| T1236 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.288051177 |
|
|
Aug 13 06:30:43 PM PDT 24 |
Aug 13 06:30:57 PM PDT 24 |
29711900 ps |
| T1237 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.2179651334 |
|
|
Aug 13 06:30:22 PM PDT 24 |
Aug 13 06:30:39 PM PDT 24 |
49263600 ps |
| T1238 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3445006124 |
|
|
Aug 13 06:30:09 PM PDT 24 |
Aug 13 06:30:32 PM PDT 24 |
140807200 ps |
| T1239 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.1785032390 |
|
|
Aug 13 06:30:13 PM PDT 24 |
Aug 13 06:36:44 PM PDT 24 |
366716400 ps |
| T1240 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.4028599602 |
|
|
Aug 13 06:30:26 PM PDT 24 |
Aug 13 06:30:46 PM PDT 24 |
386995800 ps |
| T1241 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.4095314821 |
|
|
Aug 13 06:30:40 PM PDT 24 |
Aug 13 06:30:54 PM PDT 24 |
55231700 ps |
| T1242 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2631764108 |
|
|
Aug 13 06:30:02 PM PDT 24 |
Aug 13 06:30:20 PM PDT 24 |
57510900 ps |
| T1243 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.138963578 |
|
|
Aug 13 06:30:21 PM PDT 24 |
Aug 13 06:30:34 PM PDT 24 |
34571700 ps |
| T1244 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.468242674 |
|
|
Aug 13 06:30:08 PM PDT 24 |
Aug 13 06:30:21 PM PDT 24 |
44265900 ps |
| T1245 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.1606381402 |
|
|
Aug 13 06:30:04 PM PDT 24 |
Aug 13 06:30:19 PM PDT 24 |
59693100 ps |
| T1246 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.3192416807 |
|
|
Aug 13 06:30:06 PM PDT 24 |
Aug 13 06:30:22 PM PDT 24 |
142169300 ps |
| T1247 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.721212769 |
|
|
Aug 13 06:30:25 PM PDT 24 |
Aug 13 06:30:41 PM PDT 24 |
17565000 ps |
| T1248 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.4185555272 |
|
|
Aug 13 06:30:22 PM PDT 24 |
Aug 13 06:30:36 PM PDT 24 |
39512900 ps |
| T1249 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.4007557403 |
|
|
Aug 13 06:30:20 PM PDT 24 |
Aug 13 06:30:38 PM PDT 24 |
110974900 ps |
| T1250 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1372479642 |
|
|
Aug 13 06:30:22 PM PDT 24 |
Aug 13 06:30:38 PM PDT 24 |
195367500 ps |