Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.25	95.70	93.92	98.31	92.52	98.23	96.89	98.21

Total test records in report: 1257

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html

T1251	/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.2191852424			Aug 13 06:30:40 PM PDT 24	Aug 13 06:30:58 PM PDT 24	118189300 ps
T1252	/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.1904158483			Aug 13 06:30:06 PM PDT 24	Aug 13 06:30:20 PM PDT 24	92173900 ps
T1253	/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.522236454			Aug 13 06:30:22 PM PDT 24	Aug 13 06:30:42 PM PDT 24	310301700 ps
T1254	/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.2698156369			Aug 13 06:30:40 PM PDT 24	Aug 13 06:30:54 PM PDT 24	53968200 ps
T1255	/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.1033921676			Aug 13 06:30:06 PM PDT 24	Aug 13 06:30:26 PM PDT 24	68470800 ps
T1256	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1644164423			Aug 13 06:29:56 PM PDT 24	Aug 13 06:31:19 PM PDT 24	18242214200 ps
T1257	/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.3304740853			Aug 13 06:30:12 PM PDT 24	Aug 13 06:30:31 PM PDT 24	95736900 ps

Test location	/workspace/coverage/default/3.flash_ctrl_phy_arb.4264610249
Short name	T1
Test name
Test status
Simulation time	202201600 ps
CPU time	279.78 seconds
Started	Aug 13 06:15:44 PM PDT 24
Finished	Aug 13 06:20:24 PM PDT 24
Peak memory	263836 kb
Host	smart-45adc3c2-d37e-4374-9914-1f4f423051eb
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4264610249 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.4264610249
Directory	/workspace/3.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3175140590
Short name	T101
Test name
Test status
Simulation time	1662281200 ps
CPU time	469.6 seconds
Started	Aug 13 06:30:30 PM PDT 24
Finished	Aug 13 06:38:20 PM PDT 24
Peak memory	261648 kb
Host	smart-3046b375-58f0-4f66-8915-41ecf076b6a2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175140590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctr l_tl_intg_err.3175140590
Directory	/workspace/17.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/16.flash_ctrl_hw_rma_reset.3617664529
Short name	T2
Test name
Test status
Simulation time	40124150500 ps
CPU time	864.9 seconds
Started	Aug 13 06:19:27 PM PDT 24
Finished	Aug 13 06:33:52 PM PDT 24
Peak memory	265164 kb
Host	smart-c32dc1a9-5b2f-495f-8920-0b2f64c89077
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617664529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 16.flash_ctrl_hw_rma_reset.3617664529
Directory	/workspace/16.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/10.flash_ctrl_mp_regions.303255936
Short name	T62
Test name
Test status
Simulation time	36528814700 ps
CPU time	281.38 seconds
Started	Aug 13 06:18:01 PM PDT 24
Finished	Aug 13 06:22:43 PM PDT 24
Peak memory	275256 kb
Host	smart-8e60a5df-7476-4211-b446-f4e2317b3a3e
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303255936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_mp_regions.303255936
Directory	/workspace/10.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/3.flash_ctrl_sec_cm.4064886184
Short name	T4
Test name
Test status
Simulation time	5385694200 ps
CPU time	4977.57 seconds
Started	Aug 13 06:16:03 PM PDT 24
Finished	Aug 13 07:39:02 PM PDT 24
Peak memory	290016 kb
Host	smart-47ed88af-c43e-4121-b645-f6ab4a51fcd4
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064886184 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.4064886184
Directory	/workspace/3.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rw_serr.2521304704
Short name	T28
Test name
Test status
Simulation time	1823104900 ps
CPU time	239.11 seconds
Started	Aug 13 06:15:15 PM PDT 24
Finished	Aug 13 06:19:15 PM PDT 24
Peak memory	290644 kb
Host	smart-139e8681-62bf-411e-b922-22e581c6ddb9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521304704 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.flash_ctrl_rw_serr.2521304704
Directory	/workspace/2.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_erase_suspend.631505742
Short name	T160
Test name
Test status
Simulation time	2132271600 ps
CPU time	423.16 seconds
Started	Aug 13 06:14:27 PM PDT 24
Finished	Aug 13 06:21:30 PM PDT 24
Peak memory	263936 kb
Host	smart-1a80fdb8-f813-42e4-a373-cefe3575765a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=631505742 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.631505742
Directory	/workspace/1.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/30.flash_ctrl_otp_reset.423187330
Short name	T39
Test name
Test status
Simulation time	39445000 ps
CPU time	131.45 seconds
Started	Aug 13 06:21:05 PM PDT 24
Finished	Aug 13 06:23:16 PM PDT 24
Peak memory	260712 kb
Host	smart-e722cc4c-12a5-43a2-b905-3f8178e86254
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423187330 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_ot p_reset.423187330
Directory	/workspace/30.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3473732545
Short name	T236
Test name
Test status
Simulation time	202474800 ps
CPU time	18.75 seconds
Started	Aug 13 06:30:01 PM PDT 24
Finished	Aug 13 06:30:19 PM PDT 24
Peak memory	264296 kb
Host	smart-25b2b9c6-867e-4b4e-b80d-18061224393c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473732545 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.3 473732545
Directory	/workspace/0.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/3.flash_ctrl_mid_op_rst.3999289768
Short name	T86
Test name
Test status
Simulation time	1709220200 ps
CPU time	72.24 seconds
Started	Aug 13 06:15:55 PM PDT 24
Finished	Aug 13 06:17:08 PM PDT 24
Peak memory	261240 kb
Host	smart-1f1376de-becc-4e2c-9a53-96067270d86b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3999289768 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.3999289768
Directory	/workspace/3.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/29.flash_ctrl_intr_rd.4158809084
Short name	T19
Test name
Test status
Simulation time	4335681200 ps
CPU time	190.31 seconds
Started	Aug 13 06:20:56 PM PDT 24
Finished	Aug 13 06:24:07 PM PDT 24
Peak memory	295112 kb
Host	smart-39ce8cc3-bc60-4fdb-9daa-1939d1fa6d0c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158809084 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.fla sh_ctrl_intr_rd.4158809084
Directory	/workspace/29.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/0.flash_ctrl_phy_host_grant_err.1143889240
Short name	T9
Test name
Test status
Simulation time	45431500 ps
CPU time	13.95 seconds
Started	Aug 13 06:14:11 PM PDT 24
Finished	Aug 13 06:14:25 PM PDT 24
Peak memory	263544 kb
Host	smart-454e626e-b55f-4b05-988f-10c99522fd74
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143889240 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.1143889240
Directory	/workspace/0.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/68.flash_ctrl_otp_reset.3504289666
Short name	T11
Test name
Test status
Simulation time	435991000 ps
CPU time	111.7 seconds
Started	Aug 13 06:23:29 PM PDT 24
Finished	Aug 13 06:25:21 PM PDT 24
Peak memory	261344 kb
Host	smart-d6726c3f-0d5b-416e-946b-513665104529
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504289666 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_o tp_reset.3504289666
Directory	/workspace/68.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.2975674578
Short name	T81
Test name
Test status
Simulation time	10014631800 ps
CPU time	228.53 seconds
Started	Aug 13 06:17:21 PM PDT 24
Finished	Aug 13 06:21:10 PM PDT 24
Peak memory	272840 kb
Host	smart-330f310a-4238-4c2d-a56a-f40ee5671f3d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975674578 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.2975674578
Directory	/workspace/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/37.flash_ctrl_hw_sec_otp.1672508660
Short name	T92
Test name
Test status
Simulation time	31194223500 ps
CPU time	135.38 seconds
Started	Aug 13 06:21:37 PM PDT 24
Finished	Aug 13 06:23:53 PM PDT 24
Peak memory	263344 kb
Host	smart-eb4ffc8f-3918-47d6-a74d-781433bae0e4
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672508660 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_ hw_sec_otp.1672508660
Directory	/workspace/37.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.4233341334
Short name	T316
Test name
Test status
Simulation time	52365900 ps
CPU time	13.42 seconds
Started	Aug 13 06:30:29 PM PDT 24
Finished	Aug 13 06:30:42 PM PDT 24
Peak memory	261700 kb
Host	smart-4ff1ee93-8ad8-478a-94e1-181454937fd6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233341334 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test. 4233341334
Directory	/workspace/25.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/default/4.flash_ctrl_sec_cm.35888854
Short name	T52
Test name
Test status
Simulation time	1581623000 ps
CPU time	4849.29 seconds
Started	Aug 13 06:16:30 PM PDT 24
Finished	Aug 13 07:37:20 PM PDT 24
Peak memory	290584 kb
Host	smart-9d5debd5-afd6-48e4-a2da-61fb82eaa9aa
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35888854 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.35888854
Directory	/workspace/4.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/16.flash_ctrl_otp_reset.3951900859
Short name	T179
Test name
Test status
Simulation time	272078700 ps
CPU time	130.91 seconds
Started	Aug 13 06:19:22 PM PDT 24
Finished	Aug 13 06:21:33 PM PDT 24
Peak memory	260652 kb
Host	smart-a3a64b76-ae77-44b8-9362-83ffc353b522
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951900859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_o tp_reset.3951900859
Directory	/workspace/16.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rw_derr.879293324
Short name	T47
Test name
Test status
Simulation time	7997542100 ps
CPU time	248.12 seconds
Started	Aug 13 06:14:41 PM PDT 24
Finished	Aug 13 06:18:49 PM PDT 24
Peak memory	295664 kb
Host	smart-9bdbeb20-cfad-4426-b146-1c4700679eab
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879293324 -ass ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_derr.879293324
Directory	/workspace/1.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.3388433169
Short name	T205
Test name
Test status
Simulation time	720153300 ps
CPU time	914.09 seconds
Started	Aug 13 06:30:02 PM PDT 24
Finished	Aug 13 06:45:16 PM PDT 24
Peak memory	264168 kb
Host	smart-a491cd1f-5a16-425c-8fbc-e1ffc8a40227
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388433169 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl _tl_intg_err.3388433169
Directory	/workspace/1.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/2.flash_ctrl_host_ctrl_arb.1956618334
Short name	T73
Test name
Test status
Simulation time	240531765200 ps
CPU time	2428.7 seconds
Started	Aug 13 06:15:04 PM PDT 24
Finished	Aug 13 06:55:33 PM PDT 24
Peak memory	264816 kb
Host	smart-3cdaad93-1dc5-432f-a240-5bb0c27984ff
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956618334 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.flash_ctrl_host_ctrl_arb.1956618334
Directory	/workspace/2.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/default/40.flash_ctrl_disable.4106307505
Short name	T71
Test name
Test status
Simulation time	11173300 ps
CPU time	21.5 seconds
Started	Aug 13 06:22:07 PM PDT 24
Finished	Aug 13 06:22:29 PM PDT 24
Peak memory	274152 kb
Host	smart-9320fc82-5c77-4560-ba58-e69c1d5a41f2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106307505 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_disable.4106307505
Directory	/workspace/40.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rw_evict_all_en.1070590340
Short name	T21
Test name
Test status
Simulation time	41965500 ps
CPU time	30.99 seconds
Started	Aug 13 06:17:39 PM PDT 24
Finished	Aug 13 06:18:10 PM PDT 24
Peak memory	275532 kb
Host	smart-3f1abfe8-48da-4b00-93f0-96121b122147
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070590340 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict_all_en.1070590340
Directory	/workspace/7.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/26.flash_ctrl_sec_info_access.2825848000
Short name	T199
Test name
Test status
Simulation time	2385005900 ps
CPU time	81.17 seconds
Started	Aug 13 06:20:51 PM PDT 24
Finished	Aug 13 06:22:12 PM PDT 24
Peak memory	264240 kb
Host	smart-8f975ddf-91ec-49c8-8871-4140f5ebd398
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2825848000 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.2825848000
Directory	/workspace/26.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rma_err.2230963736
Short name	T175
Test name
Test status
Simulation time	171151672500 ps
CPU time	943.95 seconds
Started	Aug 13 06:14:19 PM PDT 24
Finished	Aug 13 06:30:03 PM PDT 24
Peak memory	261848 kb
Host	smart-5953e7cf-6b47-4177-8e49-7b16e488bc0b
User	root
Command	/workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230963736 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rma_err.2230963736
Directory	/workspace/0.flash_ctrl_rma_err/latest

Test location	/workspace/coverage/default/6.flash_ctrl_fetch_code.1761681292
Short name	T43
Test name
Test status
Simulation time	588988500 ps
CPU time	23.38 seconds
Started	Aug 13 06:17:03 PM PDT 24
Finished	Aug 13 06:17:26 PM PDT 24
Peak memory	263172 kb
Host	smart-06dade45-7e8c-499b-a556-bde8e3898e31
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761681292 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetch_code.1761681292
Directory	/workspace/6.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/0.flash_ctrl_mid_op_rst.671318905
Short name	T85
Test name
Test status
Simulation time	1267192000 ps
CPU time	70.88 seconds
Started	Aug 13 06:13:42 PM PDT 24
Finished	Aug 13 06:14:53 PM PDT 24
Peak memory	261224 kb
Host	smart-ba9f5575-2dd4-4117-9998-1b7e4b3150be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=671318905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.671318905
Directory	/workspace/0.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/14.flash_ctrl_alert_test.3867252207
Short name	T87
Test name
Test status
Simulation time	67100800 ps
CPU time	13.57 seconds
Started	Aug 13 06:19:10 PM PDT 24
Finished	Aug 13 06:19:24 PM PDT 24
Peak memory	258976 kb
Host	smart-aa586360-3568-410f-b6d5-4f6ef16e7c57
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867252207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test. 3867252207
Directory	/workspace/14.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/20.flash_ctrl_intr_rd.1177820539
Short name	T534
Test name
Test status
Simulation time	1195092100 ps
CPU time	143.16 seconds
Started	Aug 13 06:20:13 PM PDT 24
Finished	Aug 13 06:22:36 PM PDT 24
Peak memory	294828 kb
Host	smart-c50d7a0e-0921-4d39-8ece-7a9b256aecf5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177820539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.fla sh_ctrl_intr_rd.1177820539
Directory	/workspace/20.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rw.110302631
Short name	T112
Test name
Test status
Simulation time	4669494500 ps
CPU time	625.94 seconds
Started	Aug 13 06:14:35 PM PDT 24
Finished	Aug 13 06:25:02 PM PDT 24
Peak memory	318312 kb
Host	smart-3acaf40f-ef52-4353-999e-8cb80da197b6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110302631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw.110302631
Directory	/workspace/1.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/10.flash_ctrl_invalid_op.425652641
Short name	T113
Test name
Test status
Simulation time	11565668400 ps
CPU time	79.78 seconds
Started	Aug 13 06:18:14 PM PDT 24
Finished	Aug 13 06:19:34 PM PDT 24
Peak memory	261176 kb
Host	smart-06278ea1-08f5-4630-bde5-df18cdfd0bf2
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425652641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.425652641
Directory	/workspace/10.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.851773493
Short name	T708
Test name
Test status
Simulation time	10032031100 ps
CPU time	53.16 seconds
Started	Aug 13 06:14:58 PM PDT 24
Finished	Aug 13 06:15:52 PM PDT 24
Peak memory	282896 kb
Host	smart-3009a86d-3141-42cc-96ae-761abe63d30b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851773493 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.851773493
Directory	/workspace/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_lcmgr_intg.1342100494
Short name	T170
Test name
Test status
Simulation time	45203000 ps
CPU time	13.43 seconds
Started	Aug 13 06:14:20 PM PDT 24
Finished	Aug 13 06:14:34 PM PDT 24
Peak memory	265428 kb
Host	smart-f6a2d044-c66c-43d0-9840-5824443de5c4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342100494 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 0.flash_ctrl_lcmgr_intg.1342100494
Directory	/workspace/0.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.4117977921
Short name	T243
Test name
Test status
Simulation time	19412900 ps
CPU time	13.43 seconds
Started	Aug 13 06:30:06 PM PDT 24
Finished	Aug 13 06:30:20 PM PDT 24
Peak memory	263280 kb
Host	smart-89fc97f8-1909-4c2a-89ad-249b7f8ef5f1
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117977921 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.fla sh_ctrl_mem_partial_access.4117977921
Directory	/workspace/1.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/default/11.flash_ctrl_re_evict.1764807575
Short name	T394
Test name
Test status
Simulation time	681640600 ps
CPU time	32.73 seconds
Started	Aug 13 06:18:30 PM PDT 24
Finished	Aug 13 06:19:03 PM PDT 24
Peak memory	274260 kb
Host	smart-09636a72-95f5-48ad-a61f-5cea1c385fc7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764807575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl ash_ctrl_re_evict.1764807575
Directory	/workspace/11.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.2780498347
Short name	T263
Test name
Test status
Simulation time	128016000 ps
CPU time	19.3 seconds
Started	Aug 13 06:30:33 PM PDT 24
Finished	Aug 13 06:30:52 PM PDT 24
Peak memory	264188 kb
Host	smart-edd7515f-665b-473e-b013-c6ccfaa7a343
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780498347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors. 2780498347
Directory	/workspace/13.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/1.flash_ctrl_wr_intg.2199069100
Short name	T230
Test name
Test status
Simulation time	82460200 ps
CPU time	15.13 seconds
Started	Aug 13 06:14:52 PM PDT 24
Finished	Aug 13 06:15:07 PM PDT 24
Peak memory	261028 kb
Host	smart-1157f8d8-5709-4bfd-80db-fd91192d1e17
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199069100 -assert nopostproc +UV M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wr_intg.2199069100
Directory	/workspace/1.flash_ctrl_wr_intg/latest

Test location	/workspace/coverage/default/3.flash_ctrl_fs_sup.796826774
Short name	T399
Test name
Test status
Simulation time	628737600 ps
CPU time	41.79 seconds
Started	Aug 13 06:16:06 PM PDT 24
Finished	Aug 13 06:16:48 PM PDT 24
Peak memory	263584 kb
Host	smart-4aba02d8-93f4-428c-82b7-87c1e34a748a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796826774 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 3.flash_ctrl_fs_sup.796826774
Directory	/workspace/3.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/default/7.flash_ctrl_re_evict.208796938
Short name	T407
Test name
Test status
Simulation time	267286900 ps
CPU time	34.31 seconds
Started	Aug 13 06:17:36 PM PDT 24
Finished	Aug 13 06:18:10 PM PDT 24
Peak memory	276404 kb
Host	smart-ccc75662-b4fe-416c-bff0-369dc0953a1f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208796938 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas h_ctrl_re_evict.208796938
Directory	/workspace/7.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/34.flash_ctrl_otp_reset.4266631242
Short name	T427
Test name
Test status
Simulation time	155826100 ps
CPU time	135.04 seconds
Started	Aug 13 06:21:20 PM PDT 24
Finished	Aug 13 06:23:35 PM PDT 24
Peak memory	260700 kb
Host	smart-09e7a8a2-8c60-429f-9e91-7c510b8ede2e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266631242 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_o tp_reset.4266631242
Directory	/workspace/34.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/2.flash_ctrl_phy_ack_consistency.4266954884
Short name	T53
Test name
Test status
Simulation time	16086300 ps
CPU time	14.45 seconds
Started	Aug 13 06:15:36 PM PDT 24
Finished	Aug 13 06:15:51 PM PDT 24
Peak memory	277692 kb
Host	smart-20358a95-35ac-45b9-9870-a5b81d5ea8c2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_ check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=4266954884 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.4266954884
Directory	/workspace/2.flash_ctrl_phy_ack_consistency/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1286794795
Short name	T277
Test name
Test status
Simulation time	1755923600 ps
CPU time	389.67 seconds
Started	Aug 13 06:30:24 PM PDT 24
Finished	Aug 13 06:36:54 PM PDT 24
Peak memory	261556 kb
Host	smart-7fc61bd4-35d4-437e-bda6-4f0143a77afa
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286794795 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl _tl_intg_err.1286794795
Directory	/workspace/4.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/18.flash_ctrl_lcmgr_intg.3470786536
Short name	T713
Test name
Test status
Simulation time	16183400 ps
CPU time	13.3 seconds
Started	Aug 13 06:19:56 PM PDT 24
Finished	Aug 13 06:20:09 PM PDT 24
Peak memory	260788 kb
Host	smart-599c2c06-b1eb-4fe8-83bc-8648f8b28294
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470786536 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 18.flash_ctrl_lcmgr_intg.3470786536
Directory	/workspace/18.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/0.flash_ctrl_sec_info_access.4198580739
Short name	T353
Test name
Test status
Simulation time	3088792200 ps
CPU time	77.31 seconds
Started	Aug 13 06:14:16 PM PDT 24
Finished	Aug 13 06:15:33 PM PDT 24
Peak memory	264348 kb
Host	smart-8b007261-9142-470c-a241-bf79ef49cd50
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4198580739 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.4198580739
Directory	/workspace/0.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/2.flash_ctrl_phy_host_grant_err.2317919431
Short name	T12
Test name
Test status
Simulation time	44163300 ps
CPU time	13.57 seconds
Started	Aug 13 06:15:36 PM PDT 24
Finished	Aug 13 06:15:50 PM PDT 24
Peak memory	263168 kb
Host	smart-7dc127d9-58f4-4a60-928b-2fe0cb558480
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317919431 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.2317919431
Directory	/workspace/2.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.2103751880
Short name	T294
Test name
Test status
Simulation time	1311075000 ps
CPU time	19.45 seconds
Started	Aug 13 06:30:05 PM PDT 24
Finished	Aug 13 06:30:25 PM PDT 24
Peak memory	272604 kb
Host	smart-9d3896fc-57f6-4f04-a257-f59fdff5e75b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103751880 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.2103751880
Directory	/workspace/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.700960112
Short name	T217
Test name
Test status
Simulation time	50523638200 ps
CPU time	289.9 seconds
Started	Aug 13 06:21:35 PM PDT 24
Finished	Aug 13 06:26:25 PM PDT 24
Peak memory	285720 kb
Host	smart-c438bab9-f043-478e-846e-0a8c7739e8de
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700960112 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd_slow_flash.700960112
Directory	/workspace/37.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/0.flash_ctrl_integrity.259600893
Short name	T389
Test name
Test status
Simulation time	4693915900 ps
CPU time	460.33 seconds
Started	Aug 13 06:14:03 PM PDT 24
Finished	Aug 13 06:21:43 PM PDT 24
Peak memory	323832 kb
Host	smart-7c53df75-d6ec-4f05-9297-99d532fe60e8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259600893 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.flash_ctrl_integrity.259600893
Directory	/workspace/0.flash_ctrl_integrity/latest

Test location	/workspace/coverage/default/0.flash_ctrl_phy_arb_redun.1032255196
Short name	T154
Test name
Test status
Simulation time	942268500 ps
CPU time	15.22 seconds
Started	Aug 13 06:14:11 PM PDT 24
Finished	Aug 13 06:14:27 PM PDT 24
Peak memory	263724 kb
Host	smart-598f4fd0-1fd7-4dcf-88f2-af3dd6c727b7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032255196 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.1032255196
Directory	/workspace/0.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/default/11.flash_ctrl_mp_regions.4241091417
Short name	T115
Test name
Test status
Simulation time	3997048500 ps
CPU time	355.34 seconds
Started	Aug 13 06:18:21 PM PDT 24
Finished	Aug 13 06:24:17 PM PDT 24
Peak memory	274232 kb
Host	smart-344fd28a-78cc-42dc-b5f6-58bf872ee90c
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241091417 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_mp_regions.4241091417
Directory	/workspace/11.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/22.flash_ctrl_rw_evict_all_en.495751168
Short name	T224
Test name
Test status
Simulation time	34099300 ps
CPU time	29.3 seconds
Started	Aug 13 06:20:25 PM PDT 24
Finished	Aug 13 06:20:54 PM PDT 24
Peak memory	275576 kb
Host	smart-cb4e376e-0a98-4526-8dd0-34cf0235e35c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495751168 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict_all_en.495751168
Directory	/workspace/22.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1984241457
Short name	T60
Test name
Test status
Simulation time	68573400 ps
CPU time	16.75 seconds
Started	Aug 13 06:29:54 PM PDT 24
Finished	Aug 13 06:30:11 PM PDT 24
Peak memory	264116 kb
Host	smart-1e9256a3-162b-4ac8-828b-2d9305e27e5c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984241457 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 0.flash_ctrl_csr_rw.1984241457
Directory	/workspace/0.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.1573399719
Short name	T313
Test name
Test status
Simulation time	33033500 ps
CPU time	13.5 seconds
Started	Aug 13 06:30:25 PM PDT 24
Finished	Aug 13 06:30:39 PM PDT 24
Peak memory	261684 kb
Host	smart-2785dd2a-6175-4ff2-8197-3f296e420377
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573399719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test. 1573399719
Directory	/workspace/14.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.1211114555
Short name	T1094
Test name
Test status
Simulation time	15680300 ps
CPU time	14.3 seconds
Started	Aug 13 06:18:30 PM PDT 24
Finished	Aug 13 06:18:44 PM PDT 24
Peak memory	260668 kb
Host	smart-d1fb7d00-7d52-486e-872b-820a1b14e466
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211114555 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_read_seed_err.1211114555
Directory	/workspace/11.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/47.flash_ctrl_connect.963746372
Short name	T108
Test name
Test status
Simulation time	24284400 ps
CPU time	15.91 seconds
Started	Aug 13 06:22:54 PM PDT 24
Finished	Aug 13 06:23:10 PM PDT 24
Peak memory	283468 kb
Host	smart-71d21774-6ea1-437b-998c-71e475eebd9f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=963746372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.963746372
Directory	/workspace/47.flash_ctrl_connect/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.3561470863
Short name	T1227
Test name
Test status
Simulation time	65328600 ps
CPU time	21.73 seconds
Started	Aug 13 06:30:21 PM PDT 24
Finished	Aug 13 06:30:43 PM PDT 24
Peak memory	264260 kb
Host	smart-58a1ab3c-4b2c-4e32-94e2-0c57284ab9ee
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561470863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors. 3561470863
Directory	/workspace/17.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/6.flash_ctrl_ro_derr.2317800225
Short name	T208
Test name
Test status
Simulation time	2389771000 ps
CPU time	140.16 seconds
Started	Aug 13 06:17:06 PM PDT 24
Finished	Aug 13 06:19:26 PM PDT 24
Peak memory	282448 kb
Host	smart-46a64c01-1191-4961-8225-03a3aa581da0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2317800225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.2317800225
Directory	/workspace/6.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/15.flash_ctrl_disable.3339908266
Short name	T99
Test name
Test status
Simulation time	53477500 ps
CPU time	21.64 seconds
Started	Aug 13 06:19:26 PM PDT 24
Finished	Aug 13 06:19:48 PM PDT 24
Peak memory	266828 kb
Host	smart-63e6cf9a-3d51-4143-9837-ddb59846cdeb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339908266 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_disable.3339908266
Directory	/workspace/15.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/0.flash_ctrl_error_prog_type.884909921
Short name	T79
Test name
Test status
Simulation time	5325246600 ps
CPU time	3582.7 seconds
Started	Aug 13 06:13:45 PM PDT 24
Finished	Aug 13 07:13:28 PM PDT 24
Peak memory	262640 kb
Host	smart-dd479d90-a81c-4179-8ecc-94686c68cfab
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884909921 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.flash_ctrl_error_prog_type.884909921
Directory	/workspace/0.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/0.flash_ctrl_error_prog_win.3808195508
Short name	T197
Test name
Test status
Simulation time	311509800 ps
CPU time	755.06 seconds
Started	Aug 13 06:13:44 PM PDT 24
Finished	Aug 13 06:26:19 PM PDT 24
Peak memory	274184 kb
Host	smart-92750891-99a5-47aa-b0e8-ad6c528a5a2e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3808195508 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.3808195508
Directory	/workspace/0.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/12.flash_ctrl_otp_reset.2655181874
Short name	T377
Test name
Test status
Simulation time	42141000 ps
CPU time	132.3 seconds
Started	Aug 13 06:18:40 PM PDT 24
Finished	Aug 13 06:20:53 PM PDT 24
Peak memory	260512 kb
Host	smart-f3c236aa-f261-4536-9f45-665bcbe42f41
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655181874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_o tp_reset.2655181874
Directory	/workspace/12.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.914153811
Short name	T176
Test name
Test status
Simulation time	10097713500 ps
CPU time	37.17 seconds
Started	Aug 13 06:14:20 PM PDT 24
Finished	Aug 13 06:14:57 PM PDT 24
Peak memory	265900 kb
Host	smart-9f5a3156-3ac5-47c1-a42a-9bfbc92caa9c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914153811 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.914153811
Directory	/workspace/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_read_seed_err.738039760
Short name	T598
Test name
Test status
Simulation time	15318100 ps
CPU time	13.33 seconds
Started	Aug 13 06:14:18 PM PDT 24
Finished	Aug 13 06:14:31 PM PDT 24
Peak memory	265276 kb
Host	smart-39e4048b-1a20-4bc3-9c0f-da8fd7e54f0e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738039760 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_read_seed_err.738039760
Directory	/workspace/0.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2294987161
Short name	T297
Test name
Test status
Simulation time	1581393100 ps
CPU time	459.51 seconds
Started	Aug 13 06:30:23 PM PDT 24
Finished	Aug 13 06:38:03 PM PDT 24
Peak memory	264204 kb
Host	smart-b5e81928-f938-4adc-a089-4f28116d1bbd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294987161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctr l_tl_intg_err.2294987161
Directory	/workspace/16.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/10.flash_ctrl_sec_info_access.390794713
Short name	T1071
Test name
Test status
Simulation time	3543592500 ps
CPU time	70.87 seconds
Started	Aug 13 06:18:10 PM PDT 24
Finished	Aug 13 06:19:21 PM PDT 24
Peak memory	264352 kb
Host	smart-9e262590-8b77-4229-9b2f-c142c8d66db8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=390794713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.390794713
Directory	/workspace/10.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/17.flash_ctrl_rw_evict_all_en.1772787057
Short name	T406
Test name
Test status
Simulation time	54981500 ps
CPU time	30.6 seconds
Started	Aug 13 06:19:40 PM PDT 24
Finished	Aug 13 06:20:11 PM PDT 24
Peak memory	274156 kb
Host	smart-e25ae7ab-3c0c-4b1b-84d0-dbb3190d6396
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772787057 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict_all_en.1772787057
Directory	/workspace/17.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/43.flash_ctrl_sec_info_access.3236565743
Short name	T350
Test name
Test status
Simulation time	1722035400 ps
CPU time	75.3 seconds
Started	Aug 13 06:22:29 PM PDT 24
Finished	Aug 13 06:23:44 PM PDT 24
Peak memory	265368 kb
Host	smart-2003731e-5ce4-4bd0-8780-e72bec2976ce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3236565743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.3236565743
Directory	/workspace/43.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rw.2206755640
Short name	T225
Test name
Test status
Simulation time	12472604200 ps
CPU time	494.54 seconds
Started	Aug 13 06:16:49 PM PDT 24
Finished	Aug 13 06:25:03 PM PDT 24
Peak memory	318364 kb
Host	smart-d124e7e3-7560-4a4b-aac6-f607ae478be4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206755640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 5.flash_ctrl_rw.2206755640
Directory	/workspace/5.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/2.flash_ctrl_access_after_disable.3697287799
Short name	T37
Test name
Test status
Simulation time	70056700 ps
CPU time	13.54 seconds
Started	Aug 13 06:15:35 PM PDT 24
Finished	Aug 13 06:15:49 PM PDT 24
Peak memory	265592 kb
Host	smart-056d625a-9011-437f-a196-00e9b80afd80
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697287799 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.3697287799
Directory	/workspace/2.flash_ctrl_access_after_disable/latest

Test location	/workspace/coverage/default/1.flash_ctrl_host_dir_rd.3818950107
Short name	T127
Test name
Test status
Simulation time	260972100 ps
CPU time	80.8 seconds
Started	Aug 13 06:14:18 PM PDT 24
Finished	Aug 13 06:15:39 PM PDT 24
Peak memory	265820 kb
Host	smart-0f1e3605-dd44-4243-a7c6-cac53df2efc8
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3818950107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.3818950107
Directory	/workspace/1.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/18.flash_ctrl_hw_rma_reset.3109318018
Short name	T56
Test name
Test status
Simulation time	80137407400 ps
CPU time	820.91 seconds
Started	Aug 13 06:19:51 PM PDT 24
Finished	Aug 13 06:33:32 PM PDT 24
Peak memory	265524 kb
Host	smart-77c3b56e-a057-4ee7-9c9b-58252c63b6ea
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109318018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 18.flash_ctrl_hw_rma_reset.3109318018
Directory	/workspace/18.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/15.flash_ctrl_invalid_op.151373003
Short name	T153
Test name
Test status
Simulation time	1908941000 ps
CPU time	58.29 seconds
Started	Aug 13 06:19:18 PM PDT 24
Finished	Aug 13 06:20:17 PM PDT 24
Peak memory	261376 kb
Host	smart-a120e4c6-b705-4259-bef0-1dc62208c6b9
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151373003 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.151373003
Directory	/workspace/15.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/4.flash_ctrl_config_regwen.1139811331
Short name	T260
Test name
Test status
Simulation time	67326500 ps
CPU time	14.21 seconds
Started	Aug 13 06:16:41 PM PDT 24
Finished	Aug 13 06:16:55 PM PDT 24
Peak memory	262088 kb
Host	smart-f0aab58a-fcb2-48ba-b24e-5e1e9826e743
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139811331 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 .flash_ctrl_config_regwen.1139811331
Directory	/workspace/4.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.1299542713
Short name	T341
Test name
Test status
Simulation time	1446906000 ps
CPU time	903.05 seconds
Started	Aug 13 06:30:20 PM PDT 24
Finished	Aug 13 06:45:23 PM PDT 24
Peak memory	264252 kb
Host	smart-13b727b7-9d76-4388-ab96-30ed1fc1f7d2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299542713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctr l_tl_intg_err.1299542713
Directory	/workspace/14.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.524655739
Short name	T334
Test name
Test status
Simulation time	1323687500 ps
CPU time	912.3 seconds
Started	Aug 13 06:30:29 PM PDT 24
Finished	Aug 13 06:45:42 PM PDT 24
Peak memory	264184 kb
Host	smart-957ee055-fd5a-4cf9-b6dc-33a3ac5cc839
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524655739 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl _tl_intg_err.524655739
Directory	/workspace/18.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2558363201
Short name	T333
Test name
Test status
Simulation time	1966149100 ps
CPU time	919.1 seconds
Started	Aug 13 06:30:06 PM PDT 24
Finished	Aug 13 06:45:25 PM PDT 24
Peak memory	264184 kb
Host	smart-0761eb7a-d8bc-447d-a375-67b0a06e1c73
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558363201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl _tl_intg_err.2558363201
Directory	/workspace/8.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/1.flash_ctrl_disable.3838433435
Short name	T379
Test name
Test status
Simulation time	12924900 ps
CPU time	22.08 seconds
Started	Aug 13 06:14:50 PM PDT 24
Finished	Aug 13 06:15:12 PM PDT 24
Peak memory	274000 kb
Host	smart-364b2dad-db28-40e0-9d8e-fca88b764b40
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838433435 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_disable.3838433435
Directory	/workspace/1.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/10.flash_ctrl_disable.945812139
Short name	T967
Test name
Test status
Simulation time	101653800 ps
CPU time	22.4 seconds
Started	Aug 13 06:18:09 PM PDT 24
Finished	Aug 13 06:18:32 PM PDT 24
Peak memory	267020 kb
Host	smart-a9dd7cdc-301e-479f-9e8e-b00bd8041ab2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945812139 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_disable.945812139
Directory	/workspace/10.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/11.flash_ctrl_rw_evict_all_en.295544548
Short name	T596
Test name
Test status
Simulation time	30261900 ps
CPU time	28.77 seconds
Started	Aug 13 06:18:27 PM PDT 24
Finished	Aug 13 06:18:56 PM PDT 24
Peak memory	268056 kb
Host	smart-ca099a5e-4db3-4a88-8271-d21ed7d4b577
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295544548 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict_all_en.295544548
Directory	/workspace/11.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/12.flash_ctrl_disable.3692862013
Short name	T345
Test name
Test status
Simulation time	113136800 ps
CPU time	21.7 seconds
Started	Aug 13 06:18:38 PM PDT 24
Finished	Aug 13 06:18:59 PM PDT 24
Peak memory	274120 kb
Host	smart-54ce8b5e-c387-423d-a65d-788c0001875b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692862013 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_disable.3692862013
Directory	/workspace/12.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/23.flash_ctrl_sec_info_access.3599087568
Short name	T386
Test name
Test status
Simulation time	2443393000 ps
CPU time	62.31 seconds
Started	Aug 13 06:20:30 PM PDT 24
Finished	Aug 13 06:21:32 PM PDT 24
Peak memory	264400 kb
Host	smart-b5f21fbb-9451-4c6d-b8e8-4d7303269506
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3599087568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.3599087568
Directory	/workspace/23.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/25.flash_ctrl_sec_info_access.4205621725
Short name	T382
Test name
Test status
Simulation time	2144726200 ps
CPU time	58.37 seconds
Started	Aug 13 06:20:42 PM PDT 24
Finished	Aug 13 06:21:40 PM PDT 24
Peak memory	264232 kb
Host	smart-4bb54f0d-a5bf-442f-a937-6cab9b7cda3a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4205621725 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.4205621725
Directory	/workspace/25.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/27.flash_ctrl_disable.1225471241
Short name	T873
Test name
Test status
Simulation time	10133700 ps
CPU time	21.73 seconds
Started	Aug 13 06:20:57 PM PDT 24
Finished	Aug 13 06:21:18 PM PDT 24
Peak memory	274120 kb
Host	smart-1f8bdc18-1243-47ea-a8ce-d628697af1f3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225471241 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_disable.1225471241
Directory	/workspace/27.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/27.flash_ctrl_sec_info_access.4139290749
Short name	T25
Test name
Test status
Simulation time	520144900 ps
CPU time	66.59 seconds
Started	Aug 13 06:20:56 PM PDT 24
Finished	Aug 13 06:22:03 PM PDT 24
Peak memory	265452 kb
Host	smart-9f298cb0-fc5b-4f28-a9cd-a67bac9161c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4139290749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.4139290749
Directory	/workspace/27.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/3.flash_ctrl_disable.3300208034
Short name	T344
Test name
Test status
Simulation time	15731200 ps
CPU time	22.18 seconds
Started	Aug 13 06:16:03 PM PDT 24
Finished	Aug 13 06:16:26 PM PDT 24
Peak memory	274028 kb
Host	smart-fe72dff3-1200-46fa-9b02-6495f0bbc6be
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300208034 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_disable.3300208034
Directory	/workspace/3.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rw_evict.3947688076
Short name	T403
Test name
Test status
Simulation time	36578300 ps
CPU time	31.77 seconds
Started	Aug 13 06:17:14 PM PDT 24
Finished	Aug 13 06:17:46 PM PDT 24
Peak memory	274244 kb
Host	smart-0e292c74-0e31-4b7b-bf20-882d4a7d4745
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947688076 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.fla sh_ctrl_rw_evict.3947688076
Directory	/workspace/6.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/1.flash_ctrl_intr_wr_slow_flash.1929060123
Short name	T441
Test name
Test status
Simulation time	406170952600 ps
CPU time	332.03 seconds
Started	Aug 13 06:14:41 PM PDT 24
Finished	Aug 13 06:20:13 PM PDT 24
Peak memory	261300 kb
Host	smart-9be71101-ea68-4fc9-a08e-718ed95a668b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192 9060123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.1929060123
Directory	/workspace/1.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/1.flash_ctrl_phy_ack_consistency.1791462707
Short name	T8
Test name
Test status
Simulation time	27943900 ps
CPU time	14.33 seconds
Started	Aug 13 06:15:00 PM PDT 24
Finished	Aug 13 06:15:15 PM PDT 24
Peak memory	266104 kb
Host	smart-30226b22-3151-44d1-89be-e4fe7e048a26
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_ check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1791462707 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.1791462707
Directory	/workspace/1.flash_ctrl_phy_ack_consistency/latest

Test location	/workspace/coverage/default/2.flash_ctrl_phy_arb_redun.3091116532
Short name	T66
Test name
Test status
Simulation time	856620700 ps
CPU time	23.53 seconds
Started	Aug 13 06:15:36 PM PDT 24
Finished	Aug 13 06:16:00 PM PDT 24
Peak memory	266088 kb
Host	smart-993199a8-ebc3-4d81-9537-5c768ab35a87
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091116532 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.3091116532
Directory	/workspace/2.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/default/4.flash_ctrl_hw_rma_reset.2792872333
Short name	T174
Test name
Test status
Simulation time	40126532300 ps
CPU time	888.3 seconds
Started	Aug 13 06:16:21 PM PDT 24
Finished	Aug 13 06:31:10 PM PDT 24
Peak memory	265076 kb
Host	smart-c25f5f3f-e20d-46f7-aded-2126a2d2c43f
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792872333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 4.flash_ctrl_hw_rma_reset.2792872333
Directory	/workspace/4.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/12.flash_ctrl_ro.2199476429
Short name	T214
Test name
Test status
Simulation time	687453900 ps
CPU time	109.31 seconds
Started	Aug 13 06:18:36 PM PDT 24
Finished	Aug 13 06:20:25 PM PDT 24
Peak memory	282432 kb
Host	smart-57d1bc70-bff9-443d-ad1b-a788478c0edb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199476429 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 12.flash_ctrl_ro.2199476429
Directory	/workspace/12.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/14.flash_ctrl_ro.621854684
Short name	T84
Test name
Test status
Simulation time	606657500 ps
CPU time	117.71 seconds
Started	Aug 13 06:19:02 PM PDT 24
Finished	Aug 13 06:21:00 PM PDT 24
Peak memory	290568 kb
Host	smart-a680ab45-2f1a-413f-bad6-e9eb318a3b69
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621854684 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 14.flash_ctrl_ro.621854684
Directory	/workspace/14.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rw_derr.3569917571
Short name	T48
Test name
Test status
Simulation time	3120623300 ps
CPU time	198.49 seconds
Started	Aug 13 06:16:22 PM PDT 24
Finished	Aug 13 06:19:40 PM PDT 24
Peak memory	291092 kb
Host	smart-dc37b315-5af7-4ce1-ac5e-b956b38153df
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569917571 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_derr.3569917571
Directory	/workspace/4.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw_derr.4191011287
Short name	T155
Test name
Test status
Simulation time	2005685200 ps
CPU time	276.84 seconds
Started	Aug 13 06:17:46 PM PDT 24
Finished	Aug 13 06:22:23 PM PDT 24
Peak memory	283552 kb
Host	smart-6318b061-06e2-45a3-91fa-5e43868bf7ff
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191011287 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_derr.4191011287
Directory	/workspace/8.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.663824469
Short name	T268
Test name
Test status
Simulation time	68477700 ps
CPU time	20.45 seconds
Started	Aug 13 06:30:22 PM PDT 24
Finished	Aug 13 06:30:48 PM PDT 24
Peak memory	264268 kb
Host	smart-c6caa41c-7e85-414f-93e5-b434281bc4a2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663824469 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.663824469
Directory	/workspace/10.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/default/0.flash_ctrl_error_mp.374996670
Short name	T910
Test name
Test status
Simulation time	17400962800 ps
CPU time	2228.94 seconds
Started	Aug 13 06:13:45 PM PDT 24
Finished	Aug 13 06:50:54 PM PDT 24
Peak memory	263416 kb
Host	smart-4dad3c95-7b18-4266-8ba3-84f3f0132c16
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=374996670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_mp.374996670
Directory	/workspace/0.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/0.flash_ctrl_full_mem_access.2131240023
Short name	T140
Test name
Test status
Simulation time	649767875700 ps
CPU time	3263.04 seconds
Started	Aug 13 06:13:44 PM PDT 24
Finished	Aug 13 07:08:07 PM PDT 24
Peak memory	264932 kb
Host	smart-fdd54049-d12e-418d-a7bb-b7bdc5fa6375
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131240023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_c trl_full_mem_access.2131240023
Directory	/workspace/0.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/1.flash_ctrl_host_ctrl_arb.3151016008
Short name	T194
Test name
Test status
Simulation time	226390186000 ps
CPU time	2461.25 seconds
Started	Aug 13 06:14:26 PM PDT 24
Finished	Aug 13 06:55:27 PM PDT 24
Peak memory	264528 kb
Host	smart-c545bf8a-4d56-4e48-bc9f-c7b022f113a9
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151016008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.flash_ctrl_host_ctrl_arb.3151016008
Directory	/workspace/1.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/default/3.flash_ctrl_host_ctrl_arb.4024609935
Short name	T186
Test name
Test status
Simulation time	255199640400 ps
CPU time	2487.18 seconds
Started	Aug 13 06:15:46 PM PDT 24
Finished	Aug 13 06:57:14 PM PDT 24
Peak memory	265848 kb
Host	smart-9327f749-cf97-4f3c-b983-81368a478d86
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024609935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 3.flash_ctrl_host_ctrl_arb.4024609935
Directory	/workspace/3.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/default/5.flash_ctrl_ro_derr.1099295339
Short name	T215
Test name
Test status
Simulation time	6325504300 ps
CPU time	145.13 seconds
Started	Aug 13 06:16:50 PM PDT 24
Finished	Aug 13 06:19:16 PM PDT 24
Peak memory	282484 kb
Host	smart-8ca8687a-ebf3-4c57-aa6d-1d71dc6b0b7b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1099295339 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.1099295339
Directory	/workspace/5.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rw_derr.3401880106
Short name	T209
Test name
Test status
Simulation time	7935263000 ps
CPU time	198.43 seconds
Started	Aug 13 06:17:39 PM PDT 24
Finished	Aug 13 06:20:58 PM PDT 24
Peak memory	290180 kb
Host	smart-9e81c014-b257-4cfb-a3a4-9dd0bd5e3346
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401880106 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_derr.3401880106
Directory	/workspace/7.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_ro_serr.1208266241
Short name	T213
Test name
Test status
Simulation time	733432000 ps
CPU time	131.9 seconds
Started	Aug 13 06:17:45 PM PDT 24
Finished	Aug 13 06:19:57 PM PDT 24
Peak memory	282404 kb
Host	smart-742eef35-ffcf-4fd1-bbb2-cf94e4c4f9c4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208266241 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 8.flash_ctrl_ro_serr.1208266241
Directory	/workspace/8.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.2208981377
Short name	T1169
Test name
Test status
Simulation time	4146035700 ps
CPU time	65.96 seconds
Started	Aug 13 06:30:01 PM PDT 24
Finished	Aug 13 06:31:07 PM PDT 24
Peak memory	261572 kb
Host	smart-0e6faded-4d3d-4d78-9036-d93c053ced65
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208981377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 0.flash_ctrl_csr_aliasing.2208981377
Directory	/workspace/0.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1644164423
Short name	T1256
Test name
Test status
Simulation time	18242214200 ps
CPU time	83.37 seconds
Started	Aug 13 06:29:56 PM PDT 24
Finished	Aug 13 06:31:19 PM PDT 24
Peak memory	261728 kb
Host	smart-f0d34bc2-1c42-44cc-a2b5-e9c5806bb0ba
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644164423 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 0.flash_ctrl_csr_bit_bash.1644164423
Directory	/workspace/0.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3288910341
Short name	T1142
Test name
Test status
Simulation time	24987900 ps
CPU time	31.29 seconds
Started	Aug 13 06:30:02 PM PDT 24
Finished	Aug 13 06:30:33 PM PDT 24
Peak memory	261576 kb
Host	smart-ca89a554-c75a-437e-b18a-a1be7ce4b5f7
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288910341 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 0.flash_ctrl_csr_hw_reset.3288910341
Directory	/workspace/0.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.2232190435
Short name	T1160
Test name
Test status
Simulation time	48847100 ps
CPU time	13.76 seconds
Started	Aug 13 06:30:02 PM PDT 24
Finished	Aug 13 06:30:16 PM PDT 24
Peak memory	261760 kb
Host	smart-0a4d9305-d01e-4bf1-ba8e-82b402bb723a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232190435 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.2 232190435
Directory	/workspace/0.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2797696243
Short name	T1204
Test name
Test status
Simulation time	15431100 ps
CPU time	13.82 seconds
Started	Aug 13 06:30:07 PM PDT 24
Finished	Aug 13 06:30:21 PM PDT 24
Peak memory	262424 kb
Host	smart-6f57c8c4-d4a6-4d75-8652-a7d8f9125965
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797696243 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.fla sh_ctrl_mem_partial_access.2797696243
Directory	/workspace/0.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1617453164
Short name	T1132
Test name
Test status
Simulation time	14361100 ps
CPU time	13.85 seconds
Started	Aug 13 06:30:01 PM PDT 24
Finished	Aug 13 06:30:15 PM PDT 24
Peak memory	261496 kb
Host	smart-012847a4-6ec1-4ce2-8d9e-e296e0c42a45
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617453164 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_me m_walk.1617453164
Directory	/workspace/0.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3352588028
Short name	T1187
Test name
Test status
Simulation time	642391100 ps
CPU time	18.68 seconds
Started	Aug 13 06:30:03 PM PDT 24
Finished	Aug 13 06:30:21 PM PDT 24
Peak memory	263048 kb
Host	smart-2a267d84-6ab5-4bb9-a731-510605dc7ced
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352588028 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 0.flash_ctrl_same_csr_outstanding.3352588028
Directory	/workspace/0.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.923482268
Short name	T1151
Test name
Test status
Simulation time	23883600 ps
CPU time	13.52 seconds
Started	Aug 13 06:30:02 PM PDT 24
Finished	Aug 13 06:30:16 PM PDT 24
Peak memory	253500 kb
Host	smart-a5f31547-64ee-4be9-8a0f-d925e033d84a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923482268 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors.923482268
Directory	/workspace/0.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.3269806088
Short name	T1120
Test name
Test status
Simulation time	16661600 ps
CPU time	15.9 seconds
Started	Aug 13 06:30:19 PM PDT 24
Finished	Aug 13 06:30:35 PM PDT 24
Peak memory	253504 kb
Host	smart-eb6f2361-e329-4e07-9609-e23bf470980a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269806088 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_shadow_reg_errors_with_csr_rw.3269806088
Directory	/workspace/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.614763369
Short name	T340
Test name
Test status
Simulation time	3071786900 ps
CPU time	906.24 seconds
Started	Aug 13 06:30:01 PM PDT 24
Finished	Aug 13 06:45:08 PM PDT 24
Peak memory	264128 kb
Host	smart-e87baaff-2289-4c44-95dd-825d279fcca9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614763369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ tl_intg_err.614763369
Directory	/workspace/0.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2486324871
Short name	T1186
Test name
Test status
Simulation time	1818225100 ps
CPU time	56.24 seconds
Started	Aug 13 06:30:06 PM PDT 24
Finished	Aug 13 06:31:02 PM PDT 24
Peak memory	261760 kb
Host	smart-34b7c199-ed6f-43d6-a450-90350fa1893f
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486324871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 1.flash_ctrl_csr_aliasing.2486324871
Directory	/workspace/1.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3676464355
Short name	T1183
Test name
Test status
Simulation time	9096265700 ps
CPU time	80.32 seconds
Started	Aug 13 06:30:17 PM PDT 24
Finished	Aug 13 06:31:37 PM PDT 24
Peak memory	261720 kb
Host	smart-88313a7a-1da4-4b43-81fc-8299c2ad3462
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676464355 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 1.flash_ctrl_csr_bit_bash.3676464355
Directory	/workspace/1.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.3636194260
Short name	T301
Test name
Test status
Simulation time	118870800 ps
CPU time	30.7 seconds
Started	Aug 13 06:30:05 PM PDT 24
Finished	Aug 13 06:30:35 PM PDT 24
Peak memory	261704 kb
Host	smart-5ed17b07-af22-4bce-a0a3-f6b544d6c799
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636194260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 1.flash_ctrl_csr_hw_reset.3636194260
Directory	/workspace/1.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.1748406077
Short name	T102
Test name
Test status
Simulation time	50347800 ps
CPU time	15.38 seconds
Started	Aug 13 06:30:04 PM PDT 24
Finished	Aug 13 06:30:19 PM PDT 24
Peak memory	271900 kb
Host	smart-22489fb8-c8e0-4af4-aaab-006fc3991d54
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748406077 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.1748406077
Directory	/workspace/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.3192416807
Short name	T1246
Test name
Test status
Simulation time	142169300 ps
CPU time	16.66 seconds
Started	Aug 13 06:30:06 PM PDT 24
Finished	Aug 13 06:30:22 PM PDT 24
Peak memory	261704 kb
Host	smart-ea94c212-a9b4-4e96-a9a4-ba5de9ebd9d8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192416807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 1.flash_ctrl_csr_rw.3192416807
Directory	/workspace/1.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.646296565
Short name	T1162
Test name
Test status
Simulation time	69879600 ps
CPU time	13.27 seconds
Started	Aug 13 06:30:04 PM PDT 24
Finished	Aug 13 06:30:18 PM PDT 24
Peak memory	261864 kb
Host	smart-a78cc882-4665-445e-91a1-7f18bc7be343
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646296565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.646296565
Directory	/workspace/1.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.1324790437
Short name	T1233
Test name
Test status
Simulation time	108883100 ps
CPU time	13.45 seconds
Started	Aug 13 06:30:05 PM PDT 24
Finished	Aug 13 06:30:18 PM PDT 24
Peak memory	261768 kb
Host	smart-0d0eebea-cc89-4666-8806-4c48e961d500
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324790437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_me m_walk.1324790437
Directory	/workspace/1.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2375937558
Short name	T1149
Test name
Test status
Simulation time	177198900 ps
CPU time	18 seconds
Started	Aug 13 06:30:06 PM PDT 24
Finished	Aug 13 06:30:24 PM PDT 24
Peak memory	263004 kb
Host	smart-279aa866-dbbc-467f-99eb-f33ac1258880
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375937558 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 1.flash_ctrl_same_csr_outstanding.2375937558
Directory	/workspace/1.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2485290323
Short name	T1122
Test name
Test status
Simulation time	40840800 ps
CPU time	15.65 seconds
Started	Aug 13 06:30:05 PM PDT 24
Finished	Aug 13 06:30:21 PM PDT 24
Peak memory	253560 kb
Host	smart-494561ee-cd3c-4a29-9dc6-3bdccc32d02c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485290323 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors.2485290323
Directory	/workspace/1.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.1606381402
Short name	T1245
Test name
Test status
Simulation time	59693100 ps
CPU time	15.6 seconds
Started	Aug 13 06:30:04 PM PDT 24
Finished	Aug 13 06:30:19 PM PDT 24
Peak memory	253620 kb
Host	smart-77915cce-cfde-4902-a56d-091e82cf9f1b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606381402 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shadow_reg_errors_with_csr_rw.1606381402
Directory	/workspace/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3321868757
Short name	T276
Test name
Test status
Simulation time	54367700 ps
CPU time	18.56 seconds
Started	Aug 13 06:29:54 PM PDT 24
Finished	Aug 13 06:30:13 PM PDT 24
Peak memory	264220 kb
Host	smart-e19c224c-1770-45a8-95fc-68f5ad6df73b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321868757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.3 321868757
Directory	/workspace/1.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3656238463
Short name	T234
Test name
Test status
Simulation time	41961900 ps
CPU time	16.39 seconds
Started	Aug 13 06:30:12 PM PDT 24
Finished	Aug 13 06:30:28 PM PDT 24
Peak memory	272348 kb
Host	smart-a513a5de-387f-4e82-837b-9088fe70adef
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656238463 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.3656238463
Directory	/workspace/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.3960447897
Short name	T1213
Test name
Test status
Simulation time	37992100 ps
CPU time	16.6 seconds
Started	Aug 13 06:30:16 PM PDT 24
Finished	Aug 13 06:30:33 PM PDT 24
Peak memory	264108 kb
Host	smart-8b7e093a-3b11-49d3-92e6-32fb71c3f148
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960447897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 10.flash_ctrl_csr_rw.3960447897
Directory	/workspace/10.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.1981563351
Short name	T1133
Test name
Test status
Simulation time	128416000 ps
CPU time	13.33 seconds
Started	Aug 13 06:30:25 PM PDT 24
Finished	Aug 13 06:30:38 PM PDT 24
Peak memory	261660 kb
Host	smart-6b09acd1-93bb-4bbb-95c5-2be02d70f6ac
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981563351 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test. 1981563351
Directory	/workspace/10.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3445006124
Short name	T1238
Test name
Test status
Simulation time	140807200 ps
CPU time	18.06 seconds
Started	Aug 13 06:30:09 PM PDT 24
Finished	Aug 13 06:30:32 PM PDT 24
Peak memory	261764 kb
Host	smart-6b81ceb6-2f94-43a7-b170-40a2619e9d17
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445006124 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 10.flash_ctrl_same_csr_outstanding.3445006124
Directory	/workspace/10.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2681648976
Short name	T1119
Test name
Test status
Simulation time	23404400 ps
CPU time	13.24 seconds
Started	Aug 13 06:30:12 PM PDT 24
Finished	Aug 13 06:30:25 PM PDT 24
Peak memory	252888 kb
Host	smart-eba21592-f7f4-4fa0-8211-8aff0a4c3aa0
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681648976 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors.2681648976
Directory	/workspace/10.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.428032244
Short name	T1131
Test name
Test status
Simulation time	28881800 ps
CPU time	15.62 seconds
Started	Aug 13 06:30:25 PM PDT 24
Finished	Aug 13 06:30:40 PM PDT 24
Peak memory	253464 kb
Host	smart-7589c50b-a208-4442-898e-cbc066996d43
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428032244 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 10.flash_ctrl_shadow_reg_errors_with_csr_rw.428032244
Directory	/workspace/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.2490459487
Short name	T338
Test name
Test status
Simulation time	3933223400 ps
CPU time	760.55 seconds
Started	Aug 13 06:30:25 PM PDT 24
Finished	Aug 13 06:43:05 PM PDT 24
Peak memory	272404 kb
Host	smart-3d57c9a9-77c6-466d-b516-2c895a993d3c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490459487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctr l_tl_intg_err.2490459487
Directory	/workspace/10.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1061635921
Short name	T332
Test name
Test status
Simulation time	46681200 ps
CPU time	17.26 seconds
Started	Aug 13 06:30:10 PM PDT 24
Finished	Aug 13 06:30:27 PM PDT 24
Peak memory	264240 kb
Host	smart-2d866688-ec1b-4797-a1dc-5dcf9028e0dd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061635921 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.1061635921
Directory	/workspace/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1726791048
Short name	T1222
Test name
Test status
Simulation time	113674000 ps
CPU time	13.99 seconds
Started	Aug 13 06:30:07 PM PDT 24
Finished	Aug 13 06:30:21 PM PDT 24
Peak memory	261776 kb
Host	smart-6c389ed3-143b-4fe5-bb0d-6fb8665f6e85
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726791048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 11.flash_ctrl_csr_rw.1726791048
Directory	/workspace/11.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.971494003
Short name	T1214
Test name
Test status
Simulation time	17225700 ps
CPU time	13.7 seconds
Started	Aug 13 06:30:22 PM PDT 24
Finished	Aug 13 06:30:35 PM PDT 24
Peak memory	261672 kb
Host	smart-883d14b3-8f5d-4e40-a3f9-30f3cbecc0af
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971494003 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.971494003
Directory	/workspace/11.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.1559397686
Short name	T295
Test name
Test status
Simulation time	200672000 ps
CPU time	35.69 seconds
Started	Aug 13 06:30:10 PM PDT 24
Finished	Aug 13 06:30:45 PM PDT 24
Peak memory	261764 kb
Host	smart-4fc5f23a-92c1-4293-9148-f91537f719eb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559397686 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 11.flash_ctrl_same_csr_outstanding.1559397686
Directory	/workspace/11.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2379186805
Short name	T1163
Test name
Test status
Simulation time	49089500 ps
CPU time	15.96 seconds
Started	Aug 13 06:30:21 PM PDT 24
Finished	Aug 13 06:30:37 PM PDT 24
Peak memory	253544 kb
Host	smart-256f024c-26ac-4971-805c-2c46e906e905
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379186805 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors.2379186805
Directory	/workspace/11.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2571952872
Short name	T1128
Test name
Test status
Simulation time	45993700 ps
CPU time	15.65 seconds
Started	Aug 13 06:30:15 PM PDT 24
Finished	Aug 13 06:30:31 PM PDT 24
Peak memory	253544 kb
Host	smart-e062c2c1-3c14-4e16-934e-93d61ac4f65a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571952872 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_shadow_reg_errors_with_csr_rw.2571952872
Directory	/workspace/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.317672088
Short name	T272
Test name
Test status
Simulation time	149830500 ps
CPU time	17.31 seconds
Started	Aug 13 06:30:08 PM PDT 24
Finished	Aug 13 06:30:26 PM PDT 24
Peak memory	264264 kb
Host	smart-17b4ae26-ae52-4455-a93c-a7749c59480b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317672088 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.317672088
Directory	/workspace/11.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.4012415651
Short name	T238
Test name
Test status
Simulation time	337063600 ps
CPU time	468.3 seconds
Started	Aug 13 06:30:15 PM PDT 24
Finished	Aug 13 06:38:03 PM PDT 24
Peak memory	264168 kb
Host	smart-c4c00883-ae7e-4385-9209-e0873235a2f2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012415651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctr l_tl_intg_err.4012415651
Directory	/workspace/11.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1372479642
Short name	T1250
Test name
Test status
Simulation time	195367500 ps
CPU time	15.18 seconds
Started	Aug 13 06:30:22 PM PDT 24
Finished	Aug 13 06:30:38 PM PDT 24
Peak memory	272368 kb
Host	smart-41859f04-1064-4af0-aaed-da84534e98be
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372479642 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.1372479642
Directory	/workspace/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1806137866
Short name	T250
Test name
Test status
Simulation time	37297500 ps
CPU time	16.74 seconds
Started	Aug 13 06:30:24 PM PDT 24
Finished	Aug 13 06:30:41 PM PDT 24
Peak memory	264100 kb
Host	smart-01a4eb35-edd9-47c7-ab1f-221b408fa2e2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806137866 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 12.flash_ctrl_csr_rw.1806137866
Directory	/workspace/12.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.3549390861
Short name	T1188
Test name
Test status
Simulation time	16012900 ps
CPU time	13.43 seconds
Started	Aug 13 06:30:25 PM PDT 24
Finished	Aug 13 06:30:38 PM PDT 24
Peak memory	261756 kb
Host	smart-e03defc7-0e95-4c83-8bf7-d72f95caa3e1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549390861 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test. 3549390861
Directory	/workspace/12.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.3454228978
Short name	T1231
Test name
Test status
Simulation time	61594100 ps
CPU time	19.15 seconds
Started	Aug 13 06:30:23 PM PDT 24
Finished	Aug 13 06:30:42 PM PDT 24
Peak memory	261836 kb
Host	smart-33a9e1a0-7315-431c-91f6-bf106f85c5d6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454228978 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 12.flash_ctrl_same_csr_outstanding.3454228978
Directory	/workspace/12.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.2521076164
Short name	T1158
Test name
Test status
Simulation time	12280500 ps
CPU time	16.66 seconds
Started	Aug 13 06:30:07 PM PDT 24
Finished	Aug 13 06:30:23 PM PDT 24
Peak memory	253412 kb
Host	smart-bf6e0ed9-b843-4842-8d70-b029e2db2250
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521076164 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors.2521076164
Directory	/workspace/12.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.533094301
Short name	T1126
Test name
Test status
Simulation time	15694600 ps
CPU time	16.28 seconds
Started	Aug 13 06:30:28 PM PDT 24
Finished	Aug 13 06:30:44 PM PDT 24
Peak memory	253472 kb
Host	smart-50ae51fa-ee54-4a01-ba13-7eba8ea8e10b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533094301 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 12.flash_ctrl_shadow_reg_errors_with_csr_rw.533094301
Directory	/workspace/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.1033921676
Short name	T1255
Test name
Test status
Simulation time	68470800 ps
CPU time	19.94 seconds
Started	Aug 13 06:30:06 PM PDT 24
Finished	Aug 13 06:30:26 PM PDT 24
Peak memory	264284 kb
Host	smart-26f74b3b-29c2-4a68-b766-157264677342
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033921676 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors. 1033921676
Directory	/workspace/12.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3335163356
Short name	T271
Test name
Test status
Simulation time	346288600 ps
CPU time	761.84 seconds
Started	Aug 13 06:30:08 PM PDT 24
Finished	Aug 13 06:42:50 PM PDT 24
Peak memory	262568 kb
Host	smart-3d5bfc49-48c8-4ac2-970c-4e286dd5c536
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335163356 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctr l_tl_intg_err.3335163356
Directory	/workspace/12.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.1489294036
Short name	T1189
Test name
Test status
Simulation time	728418600 ps
CPU time	18.78 seconds
Started	Aug 13 06:30:16 PM PDT 24
Finished	Aug 13 06:30:35 PM PDT 24
Peak memory	272448 kb
Host	smart-fd1113bf-212a-4eac-93f8-335991c63f19
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489294036 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.1489294036
Directory	/workspace/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.3920711075
Short name	T1150
Test name
Test status
Simulation time	261146600 ps
CPU time	14.25 seconds
Started	Aug 13 06:30:22 PM PDT 24
Finished	Aug 13 06:30:37 PM PDT 24
Peak memory	264044 kb
Host	smart-607e8384-7a62-466d-b2cd-ef5baf421cbd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920711075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 13.flash_ctrl_csr_rw.3920711075
Directory	/workspace/13.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.1444375511
Short name	T1170
Test name
Test status
Simulation time	108026300 ps
CPU time	13.79 seconds
Started	Aug 13 06:30:36 PM PDT 24
Finished	Aug 13 06:30:49 PM PDT 24
Peak memory	261580 kb
Host	smart-8bd189ad-1539-460e-964f-5ceda355ba5f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444375511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test. 1444375511
Directory	/workspace/13.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.3483498833
Short name	T299
Test name
Test status
Simulation time	111863500 ps
CPU time	16.12 seconds
Started	Aug 13 06:30:23 PM PDT 24
Finished	Aug 13 06:30:40 PM PDT 24
Peak memory	263132 kb
Host	smart-d99f4ab9-1bc6-4010-853f-28bbd461d84c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483498833 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 13.flash_ctrl_same_csr_outstanding.3483498833
Directory	/workspace/13.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.2179651334
Short name	T1237
Test name
Test status
Simulation time	49263600 ps
CPU time	16.31 seconds
Started	Aug 13 06:30:22 PM PDT 24
Finished	Aug 13 06:30:39 PM PDT 24
Peak memory	253568 kb
Host	smart-b4484235-9297-47cc-9f32-6f9cc1800e6f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179651334 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors.2179651334
Directory	/workspace/13.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3794083927
Short name	T1210
Test name
Test status
Simulation time	17818600 ps
CPU time	15.89 seconds
Started	Aug 13 06:30:22 PM PDT 24
Finished	Aug 13 06:30:38 PM PDT 24
Peak memory	253484 kb
Host	smart-09257d8d-f0ab-421c-bd8d-595f0410d7ac
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794083927 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_shadow_reg_errors_with_csr_rw.3794083927
Directory	/workspace/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3817818814
Short name	T298
Test name
Test status
Simulation time	414917600 ps
CPU time	464.71 seconds
Started	Aug 13 06:30:23 PM PDT 24
Finished	Aug 13 06:38:08 PM PDT 24
Peak memory	264108 kb
Host	smart-e7ab3ddd-3d37-42f7-bf5c-69f37e4c2f7d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817818814 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctr l_tl_intg_err.3817818814
Directory	/workspace/13.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.522236454
Short name	T1253
Test name
Test status
Simulation time	310301700 ps
CPU time	19.62 seconds
Started	Aug 13 06:30:22 PM PDT 24
Finished	Aug 13 06:30:42 PM PDT 24
Peak memory	272480 kb
Host	smart-8c6a31f9-90c7-4322-8294-aa9e0e143a80
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522236454 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.522236454
Directory	/workspace/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.803195433
Short name	T1205
Test name
Test status
Simulation time	20322900 ps
CPU time	16.61 seconds
Started	Aug 13 06:30:26 PM PDT 24
Finished	Aug 13 06:30:43 PM PDT 24
Peak memory	264096 kb
Host	smart-851fdc2e-f6d9-4f2a-bcb1-611a509ae2dc
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803195433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 14.flash_ctrl_csr_rw.803195433
Directory	/workspace/14.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.276360797
Short name	T300
Test name
Test status
Simulation time	198854700 ps
CPU time	17.85 seconds
Started	Aug 13 06:30:24 PM PDT 24
Finished	Aug 13 06:30:42 PM PDT 24
Peak memory	262976 kb
Host	smart-f35621a9-975f-48ea-b44c-78b762fee0b1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276360797 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 14.flash_ctrl_same_csr_outstanding.276360797
Directory	/workspace/14.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.721212769
Short name	T1247
Test name
Test status
Simulation time	17565000 ps
CPU time	15.65 seconds
Started	Aug 13 06:30:25 PM PDT 24
Finished	Aug 13 06:30:41 PM PDT 24
Peak memory	253348 kb
Host	smart-1978fa0e-2901-48bd-87f2-8904f3d10754
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721212769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors.721212769
Directory	/workspace/14.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.3315913498
Short name	T1147
Test name
Test status
Simulation time	15055200 ps
CPU time	13.32 seconds
Started	Aug 13 06:30:20 PM PDT 24
Finished	Aug 13 06:30:33 PM PDT 24
Peak memory	253436 kb
Host	smart-8304f205-2980-419a-917f-2b655bef2f50
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315913498 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_shadow_reg_errors_with_csr_rw.3315913498
Directory	/workspace/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2232503576
Short name	T270
Test name
Test status
Simulation time	69461700 ps
CPU time	20 seconds
Started	Aug 13 06:30:21 PM PDT 24
Finished	Aug 13 06:30:42 PM PDT 24
Peak memory	264324 kb
Host	smart-2b0a918f-5a0a-4bdb-ba52-9cb6dd5b8031
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232503576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors. 2232503576
Directory	/workspace/14.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.1731771803
Short name	T275
Test name
Test status
Simulation time	461997200 ps
CPU time	19.07 seconds
Started	Aug 13 06:30:23 PM PDT 24
Finished	Aug 13 06:30:43 PM PDT 24
Peak memory	272392 kb
Host	smart-97de62f7-ac29-4342-b60d-03cd1b9e6027
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731771803 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.1731771803
Directory	/workspace/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.138963578
Short name	T1243
Test name
Test status
Simulation time	34571700 ps
CPU time	13.73 seconds
Started	Aug 13 06:30:21 PM PDT 24
Finished	Aug 13 06:30:34 PM PDT 24
Peak memory	264128 kb
Host	smart-e3b470c3-6787-4514-a0c6-c46459708553
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138963578 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 15.flash_ctrl_csr_rw.138963578
Directory	/workspace/15.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.4246227277
Short name	T1173
Test name
Test status
Simulation time	26599400 ps
CPU time	13.66 seconds
Started	Aug 13 06:30:18 PM PDT 24
Finished	Aug 13 06:30:32 PM PDT 24
Peak memory	261648 kb
Host	smart-a92f650d-affc-46af-9fa8-e8a9a82ab3f1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246227277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test. 4246227277
Directory	/workspace/15.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.334233015
Short name	T248
Test name
Test status
Simulation time	86096500 ps
CPU time	18.86 seconds
Started	Aug 13 06:30:23 PM PDT 24
Finished	Aug 13 06:30:42 PM PDT 24
Peak memory	261756 kb
Host	smart-9b1bf72a-4714-4a23-95d2-2bc06055e9e7
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334233015 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 15.flash_ctrl_same_csr_outstanding.334233015
Directory	/workspace/15.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2262654258
Short name	T1118
Test name
Test status
Simulation time	18789700 ps
CPU time	15.65 seconds
Started	Aug 13 06:30:27 PM PDT 24
Finished	Aug 13 06:30:43 PM PDT 24
Peak memory	253420 kb
Host	smart-36b41baf-c30d-4689-924c-4bcde59c9f26
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262654258 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors.2262654258
Directory	/workspace/15.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1426862839
Short name	T1153
Test name
Test status
Simulation time	22280500 ps
CPU time	13.5 seconds
Started	Aug 13 06:30:27 PM PDT 24
Finished	Aug 13 06:30:41 PM PDT 24
Peak memory	253496 kb
Host	smart-2ab30671-a15c-4cbc-aa1d-7fa672def1fa
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426862839 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_shadow_reg_errors_with_csr_rw.1426862839
Directory	/workspace/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.3704950496
Short name	T274
Test name
Test status
Simulation time	185048800 ps
CPU time	18.35 seconds
Started	Aug 13 06:30:28 PM PDT 24
Finished	Aug 13 06:30:47 PM PDT 24
Peak memory	264308 kb
Host	smart-4b3e32b2-9d5a-4607-a784-48a6a933a653
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704950496 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors. 3704950496
Directory	/workspace/15.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.969664555
Short name	T1185
Test name
Test status
Simulation time	343880300 ps
CPU time	465.13 seconds
Started	Aug 13 06:30:25 PM PDT 24
Finished	Aug 13 06:38:10 PM PDT 24
Peak memory	264188 kb
Host	smart-3f22fc27-7e52-4819-8b75-c2337c56212f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969664555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl _tl_intg_err.969664555
Directory	/workspace/15.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.581392482
Short name	T302
Test name
Test status
Simulation time	338399400 ps
CPU time	16.46 seconds
Started	Aug 13 06:30:29 PM PDT 24
Finished	Aug 13 06:30:46 PM PDT 24
Peak memory	272488 kb
Host	smart-2e5d2b2b-487f-441d-a8dc-1edbbc451279
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581392482 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.581392482
Directory	/workspace/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.2948205038
Short name	T1228
Test name
Test status
Simulation time	87962800 ps
CPU time	16.47 seconds
Started	Aug 13 06:30:29 PM PDT 24
Finished	Aug 13 06:30:46 PM PDT 24
Peak memory	264052 kb
Host	smart-6f32ded0-d7c1-40e8-afdc-32176aa2c132
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948205038 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 16.flash_ctrl_csr_rw.2948205038
Directory	/workspace/16.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2416939045
Short name	T317
Test name
Test status
Simulation time	24160800 ps
CPU time	13.19 seconds
Started	Aug 13 06:30:27 PM PDT 24
Finished	Aug 13 06:30:40 PM PDT 24
Peak memory	261532 kb
Host	smart-c52ca342-64dc-4fa5-965e-750c2fb73758
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416939045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test. 2416939045
Directory	/workspace/16.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.4051576232
Short name	T1155
Test name
Test status
Simulation time	175481800 ps
CPU time	30.7 seconds
Started	Aug 13 06:30:22 PM PDT 24
Finished	Aug 13 06:30:53 PM PDT 24
Peak memory	263156 kb
Host	smart-c4b12715-beec-4ad5-8add-04cc1352323d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051576232 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 16.flash_ctrl_same_csr_outstanding.4051576232
Directory	/workspace/16.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1845089375
Short name	T1180
Test name
Test status
Simulation time	14632200 ps
CPU time	15.57 seconds
Started	Aug 13 06:30:21 PM PDT 24
Finished	Aug 13 06:30:37 PM PDT 24
Peak memory	253268 kb
Host	smart-2799edeb-caf5-4aec-9afc-d0fae51c7c49
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845089375 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors.1845089375
Directory	/workspace/16.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2178831212
Short name	T1182
Test name
Test status
Simulation time	36262000 ps
CPU time	15.73 seconds
Started	Aug 13 06:30:24 PM PDT 24
Finished	Aug 13 06:30:40 PM PDT 24
Peak memory	253456 kb
Host	smart-113343c5-5123-4a1b-a2af-1e3898948cce
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178831212 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_shadow_reg_errors_with_csr_rw.2178831212
Directory	/workspace/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1905311093
Short name	T269
Test name
Test status
Simulation time	155464400 ps
CPU time	17.08 seconds
Started	Aug 13 06:30:20 PM PDT 24
Finished	Aug 13 06:30:37 PM PDT 24
Peak memory	264312 kb
Host	smart-6501cc4c-09d6-4ca5-b6d9-e9ae9b360f05
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905311093 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors. 1905311093
Directory	/workspace/16.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.4007557403
Short name	T1249
Test name
Test status
Simulation time	110974900 ps
CPU time	17.36 seconds
Started	Aug 13 06:30:20 PM PDT 24
Finished	Aug 13 06:30:38 PM PDT 24
Peak memory	262696 kb
Host	smart-2d251659-8ab2-42fd-9fdb-5318a3c85f8f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007557403 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.4007557403
Directory	/workspace/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.4279645406
Short name	T1145
Test name
Test status
Simulation time	226316500 ps
CPU time	14.95 seconds
Started	Aug 13 06:30:28 PM PDT 24
Finished	Aug 13 06:30:44 PM PDT 24
Peak memory	264072 kb
Host	smart-2ae20c12-3b34-4ba0-a9cf-b165ef11053f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279645406 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 17.flash_ctrl_csr_rw.4279645406
Directory	/workspace/17.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.4005176492
Short name	T314
Test name
Test status
Simulation time	71453600 ps
CPU time	13.57 seconds
Started	Aug 13 06:30:24 PM PDT 24
Finished	Aug 13 06:30:37 PM PDT 24
Peak memory	261668 kb
Host	smart-c65cb639-8b60-45a2-83a0-e024c4b0274f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005176492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test. 4005176492
Directory	/workspace/17.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.3197408500
Short name	T59
Test name
Test status
Simulation time	85824600 ps
CPU time	18.25 seconds
Started	Aug 13 06:30:25 PM PDT 24
Finished	Aug 13 06:30:44 PM PDT 24
Peak memory	261716 kb
Host	smart-4bba31e1-552d-458e-b2fd-a32579e91b12
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197408500 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 17.flash_ctrl_same_csr_outstanding.3197408500
Directory	/workspace/17.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2992731845
Short name	T1224
Test name
Test status
Simulation time	12391100 ps
CPU time	15.73 seconds
Started	Aug 13 06:30:25 PM PDT 24
Finished	Aug 13 06:30:41 PM PDT 24
Peak memory	253568 kb
Host	smart-f1bc96b2-6145-4840-83d7-89addd68e73a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992731845 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors.2992731845
Directory	/workspace/17.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.968388237
Short name	T1218
Test name
Test status
Simulation time	26686300 ps
CPU time	13.24 seconds
Started	Aug 13 06:30:22 PM PDT 24
Finished	Aug 13 06:30:36 PM PDT 24
Peak memory	253376 kb
Host	smart-f0d4fb5e-7c81-4f49-91e6-a30840ccdc8b
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968388237 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 17.flash_ctrl_shadow_reg_errors_with_csr_rw.968388237
Directory	/workspace/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.783279731
Short name	T1181
Test name
Test status
Simulation time	45783700 ps
CPU time	20.22 seconds
Started	Aug 13 06:30:33 PM PDT 24
Finished	Aug 13 06:30:53 PM PDT 24
Peak memory	278652 kb
Host	smart-7a9fea97-dddf-43fe-9a2c-4435621a7b44
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783279731 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.783279731
Directory	/workspace/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.4119259063
Short name	T1203
Test name
Test status
Simulation time	37563400 ps
CPU time	17.36 seconds
Started	Aug 13 06:30:30 PM PDT 24
Finished	Aug 13 06:30:47 PM PDT 24
Peak memory	264104 kb
Host	smart-5db7f373-4259-44f4-b6ec-6833becfb95e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119259063 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 18.flash_ctrl_csr_rw.4119259063
Directory	/workspace/18.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.4053007657
Short name	T1166
Test name
Test status
Simulation time	16990100 ps
CPU time	13.81 seconds
Started	Aug 13 06:30:21 PM PDT 24
Finished	Aug 13 06:30:35 PM PDT 24
Peak memory	261636 kb
Host	smart-8f93e224-a995-435c-9c3a-8f7ff662e1f3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053007657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test. 4053007657
Directory	/workspace/18.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.3538017465
Short name	T1195
Test name
Test status
Simulation time	71190100 ps
CPU time	17.8 seconds
Started	Aug 13 06:30:22 PM PDT 24
Finished	Aug 13 06:30:40 PM PDT 24
Peak memory	263288 kb
Host	smart-3af3e341-fcef-45ad-a65f-74d28465557b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538017465 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 18.flash_ctrl_same_csr_outstanding.3538017465
Directory	/workspace/18.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.4185555272
Short name	T1248
Test name
Test status
Simulation time	39512900 ps
CPU time	13.59 seconds
Started	Aug 13 06:30:22 PM PDT 24
Finished	Aug 13 06:30:36 PM PDT 24
Peak memory	253392 kb
Host	smart-a16535ea-8867-43a6-a3d3-bb39a72b83ea
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185555272 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors.4185555272
Directory	/workspace/18.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.327049985
Short name	T1165
Test name
Test status
Simulation time	45496400 ps
CPU time	13.83 seconds
Started	Aug 13 06:30:22 PM PDT 24
Finished	Aug 13 06:30:36 PM PDT 24
Peak memory	253500 kb
Host	smart-c8353a0a-2854-47e5-af5e-1ee4baa2f099
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327049985 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 18.flash_ctrl_shadow_reg_errors_with_csr_rw.327049985
Directory	/workspace/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.4028599602
Short name	T1240
Test name
Test status
Simulation time	386995800 ps
CPU time	20.13 seconds
Started	Aug 13 06:30:26 PM PDT 24
Finished	Aug 13 06:30:46 PM PDT 24
Peak memory	264304 kb
Host	smart-02820358-f8d4-4e16-9683-2fde310795a8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028599602 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors. 4028599602
Directory	/workspace/18.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1633401351
Short name	T1230
Test name
Test status
Simulation time	74741400 ps
CPU time	16.39 seconds
Started	Aug 13 06:30:31 PM PDT 24
Finished	Aug 13 06:30:47 PM PDT 24
Peak memory	270848 kb
Host	smart-aba0eada-b35b-42fa-b6ac-55541fef2b9e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633401351 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.1633401351
Directory	/workspace/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1660590517
Short name	T1223
Test name
Test status
Simulation time	31174600 ps
CPU time	14.15 seconds
Started	Aug 13 06:30:20 PM PDT 24
Finished	Aug 13 06:30:35 PM PDT 24
Peak memory	261412 kb
Host	smart-457af53c-f054-4b9c-a8c2-09d83e7dd2bb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660590517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 19.flash_ctrl_csr_rw.1660590517
Directory	/workspace/19.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.2181134781
Short name	T1232
Test name
Test status
Simulation time	15402600 ps
CPU time	13.58 seconds
Started	Aug 13 06:30:20 PM PDT 24
Finished	Aug 13 06:30:34 PM PDT 24
Peak memory	261712 kb
Host	smart-f9da14a3-8fdb-4be2-8002-9f4641d770c9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181134781 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test. 2181134781
Directory	/workspace/19.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.2191852424
Short name	T1251
Test name
Test status
Simulation time	118189300 ps
CPU time	17.29 seconds
Started	Aug 13 06:30:40 PM PDT 24
Finished	Aug 13 06:30:58 PM PDT 24
Peak memory	263628 kb
Host	smart-d4fbe54c-2f1f-4edc-9004-9ff83a9d5e1f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191852424 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 19.flash_ctrl_same_csr_outstanding.2191852424
Directory	/workspace/19.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3508688644
Short name	T1121
Test name
Test status
Simulation time	46691900 ps
CPU time	16.6 seconds
Started	Aug 13 06:30:19 PM PDT 24
Finished	Aug 13 06:30:36 PM PDT 24
Peak memory	253516 kb
Host	smart-771aa69d-e03b-4d77-a6c3-39f523153b19
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508688644 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors.3508688644
Directory	/workspace/19.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.286896809
Short name	T1225
Test name
Test status
Simulation time	57402900 ps
CPU time	16.48 seconds
Started	Aug 13 06:30:21 PM PDT 24
Finished	Aug 13 06:30:37 PM PDT 24
Peak memory	253456 kb
Host	smart-d21d0447-4121-4f7e-913c-00a1c25dd63f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286896809 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 19.flash_ctrl_shadow_reg_errors_with_csr_rw.286896809
Directory	/workspace/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.1004080138
Short name	T206
Test name
Test status
Simulation time	56283300 ps
CPU time	15.42 seconds
Started	Aug 13 06:30:25 PM PDT 24
Finished	Aug 13 06:30:41 PM PDT 24
Peak memory	263384 kb
Host	smart-e7abcc8d-f89e-4b99-bd26-51e9c1a8be5c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004080138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors. 1004080138
Directory	/workspace/19.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.2769460788
Short name	T337
Test name
Test status
Simulation time	691742900 ps
CPU time	387.53 seconds
Started	Aug 13 06:30:20 PM PDT 24
Finished	Aug 13 06:36:48 PM PDT 24
Peak memory	264164 kb
Host	smart-1fbcaad1-a032-4589-91df-84ab05c7fb44
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769460788 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctr l_tl_intg_err.2769460788
Directory	/workspace/19.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.1781979695
Short name	T61
Test name
Test status
Simulation time	891529400 ps
CPU time	33.82 seconds
Started	Aug 13 06:30:14 PM PDT 24
Finished	Aug 13 06:30:48 PM PDT 24
Peak memory	261576 kb
Host	smart-96f354b0-9736-4386-95e1-779147a15825
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781979695 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 2.flash_ctrl_csr_aliasing.1781979695
Directory	/workspace/2.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.2930347274
Short name	T1138
Test name
Test status
Simulation time	2972919000 ps
CPU time	46.25 seconds
Started	Aug 13 06:30:03 PM PDT 24
Finished	Aug 13 06:30:49 PM PDT 24
Peak memory	261764 kb
Host	smart-24c39728-dfe9-453a-9fa3-781e2f721734
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930347274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 2.flash_ctrl_csr_bit_bash.2930347274
Directory	/workspace/2.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.1513919455
Short name	T1135
Test name
Test status
Simulation time	81152500 ps
CPU time	45.4 seconds
Started	Aug 13 06:30:03 PM PDT 24
Finished	Aug 13 06:30:49 PM PDT 24
Peak memory	261528 kb
Host	smart-4c17642e-1c25-42ec-b27a-1637ece09736
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513919455 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 2.flash_ctrl_csr_hw_reset.1513919455
Directory	/workspace/2.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.3858843782
Short name	T235
Test name
Test status
Simulation time	82628700 ps
CPU time	16.64 seconds
Started	Aug 13 06:30:18 PM PDT 24
Finished	Aug 13 06:30:35 PM PDT 24
Peak memory	270988 kb
Host	smart-25887399-c209-4221-b7f4-bcac481d011c
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858843782 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.3858843782
Directory	/workspace/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.2772623207
Short name	T1234
Test name
Test status
Simulation time	91830000 ps
CPU time	13.92 seconds
Started	Aug 13 06:30:03 PM PDT 24
Finished	Aug 13 06:30:18 PM PDT 24
Peak memory	264008 kb
Host	smart-605698ba-06e7-4457-b689-680021b33b40
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772623207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 2.flash_ctrl_csr_rw.2772623207
Directory	/workspace/2.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.1598570619
Short name	T1177
Test name
Test status
Simulation time	81946200 ps
CPU time	13.5 seconds
Started	Aug 13 06:30:06 PM PDT 24
Finished	Aug 13 06:30:20 PM PDT 24
Peak memory	261748 kb
Host	smart-e9d7583e-113a-46d5-b1c2-68bd6a4bad6a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598570619 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.1 598570619
Directory	/workspace/2.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.647105344
Short name	T241
Test name
Test status
Simulation time	60665000 ps
CPU time	14.41 seconds
Started	Aug 13 06:30:00 PM PDT 24
Finished	Aug 13 06:30:15 PM PDT 24
Peak memory	262540 kb
Host	smart-090cb46d-23eb-482e-bc2b-f3d9ca5adccb
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647105344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl ash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flas h_ctrl_mem_partial_access.647105344
Directory	/workspace/2.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.4071151096
Short name	T1154
Test name
Test status
Simulation time	17197400 ps
CPU time	13.59 seconds
Started	Aug 13 06:30:03 PM PDT 24
Finished	Aug 13 06:30:17 PM PDT 24
Peak memory	261600 kb
Host	smart-0f25e8d7-f320-46ce-bbd3-4981e6c38ef2
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071151096 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_me m_walk.4071151096
Directory	/workspace/2.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.2986500049
Short name	T246
Test name
Test status
Simulation time	36248400 ps
CPU time	17.28 seconds
Started	Aug 13 06:30:02 PM PDT 24
Finished	Aug 13 06:30:19 PM PDT 24
Peak memory	261556 kb
Host	smart-62aeb729-ffa2-4445-b73a-45f89f272f1d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986500049 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 2.flash_ctrl_same_csr_outstanding.2986500049
Directory	/workspace/2.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2737420702
Short name	T1171
Test name
Test status
Simulation time	13217100 ps
CPU time	13.41 seconds
Started	Aug 13 06:30:03 PM PDT 24
Finished	Aug 13 06:30:16 PM PDT 24
Peak memory	253376 kb
Host	smart-687d4943-3cc8-48ed-b648-a7d3f8292787
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737420702 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors.2737420702
Directory	/workspace/2.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.4061392145
Short name	T1229
Test name
Test status
Simulation time	19330100 ps
CPU time	15.57 seconds
Started	Aug 13 06:30:06 PM PDT 24
Finished	Aug 13 06:30:21 PM PDT 24
Peak memory	253412 kb
Host	smart-5ab413b9-7636-4ac7-a870-2529841b8806
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061392145 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_shadow_reg_errors_with_csr_rw.4061392145
Directory	/workspace/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.1840642567
Short name	T1201
Test name
Test status
Simulation time	34380900 ps
CPU time	15.72 seconds
Started	Aug 13 06:29:57 PM PDT 24
Finished	Aug 13 06:30:13 PM PDT 24
Peak memory	263588 kb
Host	smart-31c82692-4ed6-42a0-92e9-3adab2a4d047
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840642567 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.1 840642567
Directory	/workspace/2.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3694110509
Short name	T293
Test name
Test status
Simulation time	1613792100 ps
CPU time	460.41 seconds
Started	Aug 13 06:29:56 PM PDT 24
Finished	Aug 13 06:37:37 PM PDT 24
Peak memory	264200 kb
Host	smart-e4056795-bc53-48e3-a2c8-12d93bbf045f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694110509 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl _tl_intg_err.3694110509
Directory	/workspace/2.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.1837093284
Short name	T1212
Test name
Test status
Simulation time	41729800 ps
CPU time	13.77 seconds
Started	Aug 13 06:30:31 PM PDT 24
Finished	Aug 13 06:30:45 PM PDT 24
Peak memory	261648 kb
Host	smart-5bfeea25-1398-4f1e-96e4-1f8eb6c0e8df
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837093284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test. 1837093284
Directory	/workspace/20.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.3296381699
Short name	T1139
Test name
Test status
Simulation time	47959100 ps
CPU time	13.68 seconds
Started	Aug 13 06:30:39 PM PDT 24
Finished	Aug 13 06:30:53 PM PDT 24
Peak memory	261636 kb
Host	smart-eeb133f4-b9a0-4342-91a8-cde582642cfb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296381699 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test. 3296381699
Directory	/workspace/21.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.2123437188
Short name	T266
Test name
Test status
Simulation time	14868700 ps
CPU time	13.56 seconds
Started	Aug 13 06:30:29 PM PDT 24
Finished	Aug 13 06:30:43 PM PDT 24
Peak memory	261584 kb
Host	smart-4e074ef2-b331-4f17-aa67-f784a8d9a1fe
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123437188 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test. 2123437188
Directory	/workspace/22.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.3225472834
Short name	T265
Test name
Test status
Simulation time	17131300 ps
CPU time	13.79 seconds
Started	Aug 13 06:30:29 PM PDT 24
Finished	Aug 13 06:30:43 PM PDT 24
Peak memory	261616 kb
Host	smart-e194131d-8595-4f77-8306-7bda51548c0b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225472834 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test. 3225472834
Directory	/workspace/23.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.2126822315
Short name	T1164
Test name
Test status
Simulation time	28387300 ps
CPU time	13.48 seconds
Started	Aug 13 06:30:28 PM PDT 24
Finished	Aug 13 06:30:42 PM PDT 24
Peak memory	261604 kb
Host	smart-156c127d-b2a8-4aca-a1e8-8560009b2322
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126822315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test. 2126822315
Directory	/workspace/24.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.480150784
Short name	T1216
Test name
Test status
Simulation time	155988500 ps
CPU time	13.53 seconds
Started	Aug 13 06:30:34 PM PDT 24
Finished	Aug 13 06:30:48 PM PDT 24
Peak memory	261596 kb
Host	smart-af06b34f-32ef-433b-b2cc-6ccb666d9023
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480150784 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.480150784
Directory	/workspace/26.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3170101990
Short name	T1127
Test name
Test status
Simulation time	14839600 ps
CPU time	13.48 seconds
Started	Aug 13 06:30:29 PM PDT 24
Finished	Aug 13 06:30:42 PM PDT 24
Peak memory	261620 kb
Host	smart-ee400fe1-fdaa-43d6-88f3-80ad388f3750
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170101990 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test. 3170101990
Directory	/workspace/27.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.2698156369
Short name	T1254
Test name
Test status
Simulation time	53968200 ps
CPU time	13.43 seconds
Started	Aug 13 06:30:40 PM PDT 24
Finished	Aug 13 06:30:54 PM PDT 24
Peak memory	261768 kb
Host	smart-70a402bf-928a-4483-9d0d-64e06371c47a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698156369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test. 2698156369
Directory	/workspace/28.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.758000009
Short name	T1148
Test name
Test status
Simulation time	24907400 ps
CPU time	13.52 seconds
Started	Aug 13 06:30:35 PM PDT 24
Finished	Aug 13 06:30:49 PM PDT 24
Peak memory	261664 kb
Host	smart-c1808281-b281-4a22-ae3d-a89148f630fb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758000009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.758000009
Directory	/workspace/29.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.3457140931
Short name	T1161
Test name
Test status
Simulation time	2535196400 ps
CPU time	39.61 seconds
Started	Aug 13 06:30:02 PM PDT 24
Finished	Aug 13 06:30:42 PM PDT 24
Peak memory	261728 kb
Host	smart-3a5261e4-bc35-4645-a1c9-c7fb0c3f82ac
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457140931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 3.flash_ctrl_csr_aliasing.3457140931
Directory	/workspace/3.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1906662608
Short name	T1192
Test name
Test status
Simulation time	1790384900 ps
CPU time	36.9 seconds
Started	Aug 13 06:30:02 PM PDT 24
Finished	Aug 13 06:30:39 PM PDT 24
Peak memory	264056 kb
Host	smart-007ed81c-45eb-431f-baf5-60d856da0d63
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906662608 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 3.flash_ctrl_csr_bit_bash.1906662608
Directory	/workspace/3.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2759340286
Short name	T1220
Test name
Test status
Simulation time	87688200 ps
CPU time	31.54 seconds
Started	Aug 13 06:29:58 PM PDT 24
Finished	Aug 13 06:30:30 PM PDT 24
Peak memory	261524 kb
Host	smart-add297db-958b-4d74-8496-6456d82132df
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759340286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 3.flash_ctrl_csr_hw_reset.2759340286
Directory	/workspace/3.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.285856793
Short name	T103
Test name
Test status
Simulation time	173659000 ps
CPU time	19.14 seconds
Started	Aug 13 06:30:02 PM PDT 24
Finished	Aug 13 06:30:22 PM PDT 24
Peak memory	272476 kb
Host	smart-6f4fc3ac-c58f-4cf4-a4c9-a1671c2e99eb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285856793 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.285856793
Directory	/workspace/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2631764108
Short name	T1242
Test name
Test status
Simulation time	57510900 ps
CPU time	17.35 seconds
Started	Aug 13 06:30:02 PM PDT 24
Finished	Aug 13 06:30:20 PM PDT 24
Peak memory	264124 kb
Host	smart-d6e16709-1d7c-48c8-907c-d83b7ef72c05
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631764108 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 3.flash_ctrl_csr_rw.2631764108
Directory	/workspace/3.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.1275207053
Short name	T1235
Test name
Test status
Simulation time	18615500 ps
CPU time	13.54 seconds
Started	Aug 13 06:30:01 PM PDT 24
Finished	Aug 13 06:30:15 PM PDT 24
Peak memory	261596 kb
Host	smart-4d63e7d0-dbd0-46f1-ae60-293907facc02
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275207053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.1 275207053
Directory	/workspace/3.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.2312951986
Short name	T240
Test name
Test status
Simulation time	25499300 ps
CPU time	13.55 seconds
Started	Aug 13 06:30:00 PM PDT 24
Finished	Aug 13 06:30:14 PM PDT 24
Peak memory	262600 kb
Host	smart-73dab704-aae1-4092-a7be-77f13a991525
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312951986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fla sh_ctrl_mem_partial_access.2312951986
Directory	/workspace/3.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1091434032
Short name	T1117
Test name
Test status
Simulation time	17396300 ps
CPU time	13.6 seconds
Started	Aug 13 06:30:03 PM PDT 24
Finished	Aug 13 06:30:17 PM PDT 24
Peak memory	261496 kb
Host	smart-d671f324-77a4-4940-8d4a-90c0b55bf73e
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091434032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_me m_walk.1091434032
Directory	/workspace/3.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3376636989
Short name	T1184
Test name
Test status
Simulation time	90648800 ps
CPU time	18.12 seconds
Started	Aug 13 06:30:02 PM PDT 24
Finished	Aug 13 06:30:20 PM PDT 24
Peak memory	264148 kb
Host	smart-f923d045-c751-42c5-a7e5-3d8635aff296
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376636989 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 3.flash_ctrl_same_csr_outstanding.3376636989
Directory	/workspace/3.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.468242674
Short name	T1244
Test name
Test status
Simulation time	44265900 ps
CPU time	13.4 seconds
Started	Aug 13 06:30:08 PM PDT 24
Finished	Aug 13 06:30:21 PM PDT 24
Peak memory	253456 kb
Host	smart-72fa599b-9705-4b54-9ac1-844292c1dc98
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468242674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors.468242674
Directory	/workspace/3.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.703434196
Short name	T1217
Test name
Test status
Simulation time	41509700 ps
CPU time	13.39 seconds
Started	Aug 13 06:30:02 PM PDT 24
Finished	Aug 13 06:30:15 PM PDT 24
Peak memory	253424 kb
Host	smart-40a07698-88af-4b23-8a04-4c46f67b3a41
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703434196 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 3.flash_ctrl_shadow_reg_errors_with_csr_rw.703434196
Directory	/workspace/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.661651535
Short name	T1211
Test name
Test status
Simulation time	41441300 ps
CPU time	16.9 seconds
Started	Aug 13 06:30:00 PM PDT 24
Finished	Aug 13 06:30:17 PM PDT 24
Peak memory	264312 kb
Host	smart-1cdcdd0c-16f5-4299-b0d5-cf6519a05296
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661651535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.661651535
Directory	/workspace/3.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1147820120
Short name	T339
Test name
Test status
Simulation time	1350967300 ps
CPU time	911.22 seconds
Started	Aug 13 06:30:02 PM PDT 24
Finished	Aug 13 06:45:13 PM PDT 24
Peak memory	264112 kb
Host	smart-fcdd3324-6681-461d-b6e0-f8213e14fcd4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147820120 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl _tl_intg_err.1147820120
Directory	/workspace/3.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.2838101309
Short name	T1140
Test name
Test status
Simulation time	15855800 ps
CPU time	13.57 seconds
Started	Aug 13 06:30:38 PM PDT 24
Finished	Aug 13 06:30:52 PM PDT 24
Peak memory	261732 kb
Host	smart-4ffd1ef5-e4f3-487e-ab6c-f523fc07e6c4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838101309 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test. 2838101309
Directory	/workspace/30.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.4095314821
Short name	T1241
Test name
Test status
Simulation time	55231700 ps
CPU time	13.55 seconds
Started	Aug 13 06:30:40 PM PDT 24
Finished	Aug 13 06:30:54 PM PDT 24
Peak memory	261628 kb
Host	smart-1daf9505-9ea6-4ed4-b4e1-590fd1eecb99
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095314821 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test. 4095314821
Directory	/workspace/31.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2408480236
Short name	T1197
Test name
Test status
Simulation time	102602800 ps
CPU time	13.54 seconds
Started	Aug 13 06:30:37 PM PDT 24
Finished	Aug 13 06:30:51 PM PDT 24
Peak memory	261696 kb
Host	smart-ee996f84-df8c-4858-b88d-2eeaca092cfc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408480236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test. 2408480236
Directory	/workspace/32.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.2823677297
Short name	T1199
Test name
Test status
Simulation time	47522100 ps
CPU time	13.55 seconds
Started	Aug 13 06:30:39 PM PDT 24
Finished	Aug 13 06:30:53 PM PDT 24
Peak memory	261756 kb
Host	smart-1aed24bc-4252-43d1-a6c0-2627a24c9116
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823677297 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test. 2823677297
Directory	/workspace/33.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.176473381
Short name	T1202
Test name
Test status
Simulation time	15182700 ps
CPU time	13.5 seconds
Started	Aug 13 06:30:33 PM PDT 24
Finished	Aug 13 06:30:46 PM PDT 24
Peak memory	261636 kb
Host	smart-52291728-2a73-48f4-b169-e422b999fc97
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176473381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.176473381
Directory	/workspace/34.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.2880767515
Short name	T1137
Test name
Test status
Simulation time	29378900 ps
CPU time	13.34 seconds
Started	Aug 13 06:30:31 PM PDT 24
Finished	Aug 13 06:30:44 PM PDT 24
Peak memory	261764 kb
Host	smart-b2b86b45-8df2-41bb-ac06-d9fe0eb84964
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880767515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test. 2880767515
Directory	/workspace/35.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1044494619
Short name	T1136
Test name
Test status
Simulation time	39421600 ps
CPU time	13.29 seconds
Started	Aug 13 06:30:31 PM PDT 24
Finished	Aug 13 06:30:44 PM PDT 24
Peak memory	261764 kb
Host	smart-09b0acbb-6674-4579-9153-acfad524677a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044494619 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test. 1044494619
Directory	/workspace/36.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.3797173541
Short name	T312
Test name
Test status
Simulation time	18530400 ps
CPU time	13.58 seconds
Started	Aug 13 06:30:28 PM PDT 24
Finished	Aug 13 06:30:41 PM PDT 24
Peak memory	261544 kb
Host	smart-bfc47c88-8732-4c0f-b282-2a455d0a3b4a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797173541 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test. 3797173541
Directory	/workspace/37.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.243612858
Short name	T1221
Test name
Test status
Simulation time	32101200 ps
CPU time	13.26 seconds
Started	Aug 13 06:30:46 PM PDT 24
Finished	Aug 13 06:30:59 PM PDT 24
Peak memory	261672 kb
Host	smart-13c897ef-07cf-47a5-bdb9-ea36d9de02ed
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243612858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.243612858
Directory	/workspace/38.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.3264655265
Short name	T1196
Test name
Test status
Simulation time	14720800 ps
CPU time	13.38 seconds
Started	Aug 13 06:30:50 PM PDT 24
Finished	Aug 13 06:31:04 PM PDT 24
Peak memory	261768 kb
Host	smart-0fa1052b-8cb4-45e6-9e6b-7ff6437a1839
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264655265 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test. 3264655265
Directory	/workspace/39.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.4057871711
Short name	T1207
Test name
Test status
Simulation time	3610474300 ps
CPU time	37.74 seconds
Started	Aug 13 06:30:06 PM PDT 24
Finished	Aug 13 06:30:44 PM PDT 24
Peak memory	261700 kb
Host	smart-27883f4f-335b-4d85-b2a5-7a8e526e1471
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057871711 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 4.flash_ctrl_csr_aliasing.4057871711
Directory	/workspace/4.flash_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.1710022393
Short name	T1156
Test name
Test status
Simulation time	2277447900 ps
CPU time	36.83 seconds
Started	Aug 13 06:30:05 PM PDT 24
Finished	Aug 13 06:30:42 PM PDT 24
Peak memory	261472 kb
Host	smart-6b3554f8-6666-423b-8103-ecfe9a1771c2
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710022393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 4.flash_ctrl_csr_bit_bash.1710022393
Directory	/workspace/4.flash_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3875486212
Short name	T262
Test name
Test status
Simulation time	340233900 ps
CPU time	26.54 seconds
Started	Aug 13 06:30:06 PM PDT 24
Finished	Aug 13 06:30:33 PM PDT 24
Peak memory	261668 kb
Host	smart-15df276f-6138-488d-9831-efdc101f7bd4
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875486212 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu ll -cm_name 4.flash_ctrl_csr_hw_reset.3875486212
Directory	/workspace/4.flash_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.2328042620
Short name	T1209
Test name
Test status
Simulation time	51227200 ps
CPU time	17.14 seconds
Started	Aug 13 06:30:06 PM PDT 24
Finished	Aug 13 06:30:23 PM PDT 24
Peak memory	272484 kb
Host	smart-b7c3e29a-21f1-4222-bb40-1dcfda7ce923
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328042620 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.2328042620
Directory	/workspace/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.3959195860
Short name	T305
Test name
Test status
Simulation time	325311100 ps
CPU time	14.96 seconds
Started	Aug 13 06:30:23 PM PDT 24
Finished	Aug 13 06:30:38 PM PDT 24
Peak memory	264096 kb
Host	smart-53c76269-2536-4767-9a27-d50282bde0b9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959195860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 4.flash_ctrl_csr_rw.3959195860
Directory	/workspace/4.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.657311003
Short name	T1190
Test name
Test status
Simulation time	43354500 ps
CPU time	13.4 seconds
Started	Aug 13 06:30:21 PM PDT 24
Finished	Aug 13 06:30:34 PM PDT 24
Peak memory	261732 kb
Host	smart-f2265dbb-d520-4087-b88e-406a3b90f24c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657311003 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.657311003
Directory	/workspace/4.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.2414118387
Short name	T242
Test name
Test status
Simulation time	23565900 ps
CPU time	13.43 seconds
Started	Aug 13 06:30:04 PM PDT 24
Finished	Aug 13 06:30:18 PM PDT 24
Peak memory	262432 kb
Host	smart-c0fcdc61-1765-4b62-b850-55a0e1695221
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414118387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=f lash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.fla sh_ctrl_mem_partial_access.2414118387
Directory	/workspace/4.flash_ctrl_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.4152223154
Short name	T1175
Test name
Test status
Simulation time	15229100 ps
CPU time	13.68 seconds
Started	Aug 13 06:30:05 PM PDT 24
Finished	Aug 13 06:30:19 PM PDT 24
Peak memory	261460 kb
Host	smart-4c9be202-4e60-4335-ac21-390d0da5f65a
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152223154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_me m_walk.4152223154
Directory	/workspace/4.flash_ctrl_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.4039459064
Short name	T1168
Test name
Test status
Simulation time	68666800 ps
CPU time	18.35 seconds
Started	Aug 13 06:30:08 PM PDT 24
Finished	Aug 13 06:30:26 PM PDT 24
Peak memory	261824 kb
Host	smart-1c5f5333-869b-4a4c-a7a9-7a7cb02caeca
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039459064 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 4.flash_ctrl_same_csr_outstanding.4039459064
Directory	/workspace/4.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.916101290
Short name	T1219
Test name
Test status
Simulation time	11429500 ps
CPU time	15.42 seconds
Started	Aug 13 06:30:07 PM PDT 24
Finished	Aug 13 06:30:23 PM PDT 24
Peak memory	253360 kb
Host	smart-b77abefd-ec2e-4e36-99c7-f1fa5af8305c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916101290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors.916101290
Directory	/workspace/4.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3736441532
Short name	T1124
Test name
Test status
Simulation time	51239100 ps
CPU time	13.52 seconds
Started	Aug 13 06:30:07 PM PDT 24
Finished	Aug 13 06:30:26 PM PDT 24
Peak memory	253472 kb
Host	smart-e6a64943-c60b-46c9-9c72-dc6dde332566
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736441532 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_shadow_reg_errors_with_csr_rw.3736441532
Directory	/workspace/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3624143479
Short name	T233
Test name
Test status
Simulation time	44769000 ps
CPU time	17.09 seconds
Started	Aug 13 06:30:05 PM PDT 24
Finished	Aug 13 06:30:22 PM PDT 24
Peak memory	264260 kb
Host	smart-e8d5c179-a590-4f10-8cb5-f8096edd79d8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624143479 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.3 624143479
Directory	/workspace/4.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2594910521
Short name	T1143
Test name
Test status
Simulation time	25222800 ps
CPU time	13.5 seconds
Started	Aug 13 06:30:31 PM PDT 24
Finished	Aug 13 06:30:45 PM PDT 24
Peak memory	261624 kb
Host	smart-65755003-76ff-44c6-810d-af822c5430ee
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594910521 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test. 2594910521
Directory	/workspace/40.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3190462106
Short name	T1129
Test name
Test status
Simulation time	58696600 ps
CPU time	13.56 seconds
Started	Aug 13 06:30:27 PM PDT 24
Finished	Aug 13 06:30:41 PM PDT 24
Peak memory	261748 kb
Host	smart-c2ed3cbd-2b75-44f5-8c7c-14185eccbd97
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190462106 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test. 3190462106
Directory	/workspace/41.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.2116699718
Short name	T1167
Test name
Test status
Simulation time	96331200 ps
CPU time	13.64 seconds
Started	Aug 13 06:30:34 PM PDT 24
Finished	Aug 13 06:30:48 PM PDT 24
Peak memory	261736 kb
Host	smart-fb57d53a-cef7-4e01-a669-64ea98a9ca6b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116699718 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test. 2116699718
Directory	/workspace/42.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.3116297983
Short name	T264
Test name
Test status
Simulation time	120407100 ps
CPU time	13.38 seconds
Started	Aug 13 06:30:39 PM PDT 24
Finished	Aug 13 06:30:53 PM PDT 24
Peak memory	261512 kb
Host	smart-d5f29b43-ab71-4ed8-a73c-6f595c7b71a8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116297983 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test. 3116297983
Directory	/workspace/43.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.263647224
Short name	T1144
Test name
Test status
Simulation time	104605100 ps
CPU time	13.62 seconds
Started	Aug 13 06:30:30 PM PDT 24
Finished	Aug 13 06:30:43 PM PDT 24
Peak memory	261744 kb
Host	smart-7efc687e-dc99-4d59-bc7d-d88224e9286e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263647224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.263647224
Directory	/workspace/44.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3986460037
Short name	T1176
Test name
Test status
Simulation time	126948100 ps
CPU time	13.26 seconds
Started	Aug 13 06:30:34 PM PDT 24
Finished	Aug 13 06:30:48 PM PDT 24
Peak memory	261752 kb
Host	smart-77497526-0e3c-4d8c-9116-8b3d2480168b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986460037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test. 3986460037
Directory	/workspace/45.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3211969121
Short name	T315
Test name
Test status
Simulation time	45018100 ps
CPU time	13.43 seconds
Started	Aug 13 06:30:34 PM PDT 24
Finished	Aug 13 06:30:48 PM PDT 24
Peak memory	261692 kb
Host	smart-609f3d40-95f9-4fa4-a18a-4e03cdde870c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211969121 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test. 3211969121
Directory	/workspace/46.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.1325174694
Short name	T1208
Test name
Test status
Simulation time	62636200 ps
CPU time	13.57 seconds
Started	Aug 13 06:30:28 PM PDT 24
Finished	Aug 13 06:30:42 PM PDT 24
Peak memory	261640 kb
Host	smart-5e5d1fa0-4bbc-489a-8cd8-a1250842627f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325174694 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test. 1325174694
Directory	/workspace/47.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.1495764471
Short name	T1215
Test name
Test status
Simulation time	178330600 ps
CPU time	13.78 seconds
Started	Aug 13 06:30:31 PM PDT 24
Finished	Aug 13 06:30:44 PM PDT 24
Peak memory	261644 kb
Host	smart-d6d000ec-6afb-45a8-a8c9-8869937694a3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495764471 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test. 1495764471
Directory	/workspace/48.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.288051177
Short name	T1236
Test name
Test status
Simulation time	29711900 ps
CPU time	13.55 seconds
Started	Aug 13 06:30:43 PM PDT 24
Finished	Aug 13 06:30:57 PM PDT 24
Peak memory	261644 kb
Host	smart-fe796195-cf8b-4f3c-a78d-7c6b5516b02a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288051177 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.288051177
Directory	/workspace/49.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.332010770
Short name	T303
Test name
Test status
Simulation time	243861300 ps
CPU time	19.07 seconds
Started	Aug 13 06:30:16 PM PDT 24
Finished	Aug 13 06:30:35 PM PDT 24
Peak memory	279208 kb
Host	smart-b0bb9236-8228-4be6-bb24-9ba9e0cefeaf
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332010770 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.332010770
Directory	/workspace/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3643160692
Short name	T1174
Test name
Test status
Simulation time	88923800 ps
CPU time	17.05 seconds
Started	Aug 13 06:30:07 PM PDT 24
Finished	Aug 13 06:30:25 PM PDT 24
Peak memory	261576 kb
Host	smart-f7cd8eee-f3a6-4b54-a7fe-3f54935e201a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643160692 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 5.flash_ctrl_csr_rw.3643160692
Directory	/workspace/5.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.3607028211
Short name	T1206
Test name
Test status
Simulation time	186265300 ps
CPU time	13.36 seconds
Started	Aug 13 06:30:05 PM PDT 24
Finished	Aug 13 06:30:19 PM PDT 24
Peak memory	261696 kb
Host	smart-6178ce01-d9cc-4ef0-899f-3ceee3bd3457
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607028211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.3 607028211
Directory	/workspace/5.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1233972202
Short name	T1157
Test name
Test status
Simulation time	629458600 ps
CPU time	21.34 seconds
Started	Aug 13 06:30:13 PM PDT 24
Finished	Aug 13 06:30:34 PM PDT 24
Peak memory	263308 kb
Host	smart-a5bddd4d-9569-434a-a038-b4c36c792cd2
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233972202 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 5.flash_ctrl_same_csr_outstanding.1233972202
Directory	/workspace/5.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.1507945029
Short name	T1130
Test name
Test status
Simulation time	13240200 ps
CPU time	13.88 seconds
Started	Aug 13 06:30:04 PM PDT 24
Finished	Aug 13 06:30:18 PM PDT 24
Peak memory	253420 kb
Host	smart-6a1032a6-88e1-4002-963d-be57a9181bf4
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507945029 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors.1507945029
Directory	/workspace/5.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.2203683732
Short name	T1226
Test name
Test status
Simulation time	13560100 ps
CPU time	13.57 seconds
Started	Aug 13 06:30:06 PM PDT 24
Finished	Aug 13 06:30:20 PM PDT 24
Peak memory	253580 kb
Host	smart-0a03cef8-d30a-46e3-b58c-3c935297fe12
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203683732 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_shadow_reg_errors_with_csr_rw.2203683732
Directory	/workspace/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.2260061559
Short name	T267
Test name
Test status
Simulation time	163023600 ps
CPU time	17.34 seconds
Started	Aug 13 06:30:06 PM PDT 24
Finished	Aug 13 06:30:24 PM PDT 24
Peak memory	264176 kb
Host	smart-a46a6779-1718-4c25-bea6-e7dca8038877
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260061559 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.2 260061559
Directory	/workspace/5.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.1426748276
Short name	T1198
Test name
Test status
Simulation time	815253600 ps
CPU time	465.23 seconds
Started	Aug 13 06:30:05 PM PDT 24
Finished	Aug 13 06:37:51 PM PDT 24
Peak memory	264188 kb
Host	smart-35806ace-8584-4654-8fac-11094a052d5f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426748276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl _tl_intg_err.1426748276
Directory	/workspace/5.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.93208456
Short name	T1159
Test name
Test status
Simulation time	114044400 ps
CPU time	18.92 seconds
Started	Aug 13 06:30:08 PM PDT 24
Finished	Aug 13 06:30:27 PM PDT 24
Peak memory	278076 kb
Host	smart-4260c3d6-bbcd-4a2e-abc0-a3520134dace
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93208456 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.93208456
Directory	/workspace/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1720272367
Short name	T251
Test name
Test status
Simulation time	159560100 ps
CPU time	16.56 seconds
Started	Aug 13 06:30:24 PM PDT 24
Finished	Aug 13 06:30:41 PM PDT 24
Peak memory	264088 kb
Host	smart-3930d19d-02e6-44c5-b9d3-38ca343db474
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720272367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 6.flash_ctrl_csr_rw.1720272367
Directory	/workspace/6.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.200871820
Short name	T1194
Test name
Test status
Simulation time	16472600 ps
CPU time	13.76 seconds
Started	Aug 13 06:30:09 PM PDT 24
Finished	Aug 13 06:30:23 PM PDT 24
Peak memory	261532 kb
Host	smart-40344a2c-a429-49e0-b80b-cb93a045bd7d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200871820 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.200871820
Directory	/workspace/6.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2485378152
Short name	T247
Test name
Test status
Simulation time	84332900 ps
CPU time	18.23 seconds
Started	Aug 13 06:30:05 PM PDT 24
Finished	Aug 13 06:30:24 PM PDT 24
Peak memory	263304 kb
Host	smart-b2f13066-f490-4fe1-bee1-6e80e660ef46
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485378152 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 6.flash_ctrl_same_csr_outstanding.2485378152
Directory	/workspace/6.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.3198897403
Short name	T1146
Test name
Test status
Simulation time	14321000 ps
CPU time	15.23 seconds
Started	Aug 13 06:30:06 PM PDT 24
Finished	Aug 13 06:30:21 PM PDT 24
Peak memory	253688 kb
Host	smart-605f4ed1-7679-4f64-84c4-36cda7868756
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198897403 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors.3198897403
Directory	/workspace/6.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.2904645754
Short name	T1141
Test name
Test status
Simulation time	36409800 ps
CPU time	16.01 seconds
Started	Aug 13 06:30:09 PM PDT 24
Finished	Aug 13 06:30:26 PM PDT 24
Peak memory	253444 kb
Host	smart-abcbe7e2-8ea4-4565-9c4f-ad97e01c3fab
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904645754 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_shadow_reg_errors_with_csr_rw.2904645754
Directory	/workspace/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1576745865
Short name	T104
Test name
Test status
Simulation time	62289100 ps
CPU time	15.42 seconds
Started	Aug 13 06:30:18 PM PDT 24
Finished	Aug 13 06:30:33 PM PDT 24
Peak memory	264280 kb
Host	smart-9b21d78f-dfe2-4dfb-ade6-e0359e3ab02a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576745865 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.1 576745865
Directory	/workspace/6.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.1785032390
Short name	T1239
Test name
Test status
Simulation time	366716400 ps
CPU time	390.67 seconds
Started	Aug 13 06:30:13 PM PDT 24
Finished	Aug 13 06:36:44 PM PDT 24
Peak memory	264172 kb
Host	smart-d9251c1a-0fc6-4227-b538-55f3afba818f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785032390 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl _tl_intg_err.1785032390
Directory	/workspace/6.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.3245423016
Short name	T1152
Test name
Test status
Simulation time	43967700 ps
CPU time	19.93 seconds
Started	Aug 13 06:30:23 PM PDT 24
Finished	Aug 13 06:30:43 PM PDT 24
Peak memory	272500 kb
Host	smart-c0f56d33-b0cc-485e-bbd6-340e2967af8f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245423016 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.3245423016
Directory	/workspace/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.321247308
Short name	T244
Test name
Test status
Simulation time	37837100 ps
CPU time	17.32 seconds
Started	Aug 13 06:30:12 PM PDT 24
Finished	Aug 13 06:30:30 PM PDT 24
Peak memory	261724 kb
Host	smart-27e02b4f-14b3-4e8d-9b68-20c1bbd12bd6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321247308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_ TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 7.flash_ctrl_csr_rw.321247308
Directory	/workspace/7.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.1904158483
Short name	T1252
Test name
Test status
Simulation time	92173900 ps
CPU time	13.55 seconds
Started	Aug 13 06:30:06 PM PDT 24
Finished	Aug 13 06:30:20 PM PDT 24
Peak memory	261628 kb
Host	smart-29b2ee43-e523-4fe2-8619-a081a3740557
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904158483 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.1 904158483
Directory	/workspace/7.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1284666467
Short name	T249
Test name
Test status
Simulation time	140996600 ps
CPU time	19.09 seconds
Started	Aug 13 06:30:18 PM PDT 24
Finished	Aug 13 06:30:37 PM PDT 24
Peak memory	261644 kb
Host	smart-d17a3843-c1b7-4e8a-ab52-e090a8db887c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284666467 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 7.flash_ctrl_same_csr_outstanding.1284666467
Directory	/workspace/7.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.1026278960
Short name	T1134
Test name
Test status
Simulation time	11365200 ps
CPU time	13.42 seconds
Started	Aug 13 06:30:18 PM PDT 24
Finished	Aug 13 06:30:32 PM PDT 24
Peak memory	253432 kb
Host	smart-7943276e-e4b3-47f6-80c4-94ad1cdee9e3
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026278960 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors.1026278960
Directory	/workspace/7.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.2875396929
Short name	T1193
Test name
Test status
Simulation time	14087700 ps
CPU time	16.41 seconds
Started	Aug 13 06:30:19 PM PDT 24
Finished	Aug 13 06:30:36 PM PDT 24
Peak memory	253580 kb
Host	smart-ade5fbf3-aa24-42ab-b5d0-1dff6eac1761
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875396929 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shadow_reg_errors_with_csr_rw.2875396929
Directory	/workspace/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2930179642
Short name	T204
Test name
Test status
Simulation time	563605400 ps
CPU time	17.33 seconds
Started	Aug 13 06:30:08 PM PDT 24
Finished	Aug 13 06:30:25 PM PDT 24
Peak memory	264260 kb
Host	smart-34013659-003d-411c-be60-d5e817a2137b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930179642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.2 930179642
Directory	/workspace/7.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.3149387580
Short name	T336
Test name
Test status
Simulation time	354691500 ps
CPU time	386.16 seconds
Started	Aug 13 06:30:21 PM PDT 24
Finished	Aug 13 06:36:49 PM PDT 24
Peak memory	264172 kb
Host	smart-bafadd26-a9aa-4fa5-9bff-e16744cd4303
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149387580 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl _tl_intg_err.3149387580
Directory	/workspace/7.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.4219625224
Short name	T304
Test name
Test status
Simulation time	303096000 ps
CPU time	18.17 seconds
Started	Aug 13 06:30:06 PM PDT 24
Finished	Aug 13 06:30:24 PM PDT 24
Peak memory	272368 kb
Host	smart-dc7ab540-31fa-4f86-b2de-7f1e37086895
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219625224 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.4219625224
Directory	/workspace/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2386230802
Short name	T245
Test name
Test status
Simulation time	43891700 ps
CPU time	17.33 seconds
Started	Aug 13 06:30:05 PM PDT 24
Finished	Aug 13 06:30:23 PM PDT 24
Peak memory	261656 kb
Host	smart-ab74a459-c4d7-48b7-8645-5b37f526410e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386230802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 8.flash_ctrl_csr_rw.2386230802
Directory	/workspace/8.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.4096681
Short name	T1191
Test name
Test status
Simulation time	45880600 ps
CPU time	13.56 seconds
Started	Aug 13 06:30:19 PM PDT 24
Finished	Aug 13 06:30:33 PM PDT 24
Peak memory	261580 kb
Host	smart-dbccac9d-ce35-4dc9-881f-b962a20e9b97
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.4096681
Directory	/workspace/8.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.563896980
Short name	T1200
Test name
Test status
Simulation time	113031500 ps
CPU time	19.81 seconds
Started	Aug 13 06:30:05 PM PDT 24
Finished	Aug 13 06:30:25 PM PDT 24
Peak memory	263476 kb
Host	smart-ec77fec4-5178-46ac-b8b5-cf4cd9566c87
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563896980 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.flash_ctrl_same_csr_outstanding.563896980
Directory	/workspace/8.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.629497574
Short name	T1125
Test name
Test status
Simulation time	29237500 ps
CPU time	13.32 seconds
Started	Aug 13 06:30:19 PM PDT 24
Finished	Aug 13 06:30:34 PM PDT 24
Peak memory	253500 kb
Host	smart-493841c9-b3dc-41b3-b0dc-641db99ccce7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629497574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors.629497574
Directory	/workspace/8.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1163296395
Short name	T1178
Test name
Test status
Simulation time	36742500 ps
CPU time	15.62 seconds
Started	Aug 13 06:30:27 PM PDT 24
Finished	Aug 13 06:30:42 PM PDT 24
Peak memory	253468 kb
Host	smart-2e7220f5-b7a6-4452-b67e-290ad379ac4f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163296395 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shadow_reg_errors_with_csr_rw.1163296395
Directory	/workspace/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.511724271
Short name	T237
Test name
Test status
Simulation time	47407600 ps
CPU time	17.93 seconds
Started	Aug 13 06:30:18 PM PDT 24
Finished	Aug 13 06:30:38 PM PDT 24
Peak memory	264252 kb
Host	smart-0248150f-cddd-44e3-902b-ad1e43ce2f09
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511724271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.511724271
Directory	/workspace/8.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.3304740853
Short name	T1257
Test name
Test status
Simulation time	95736900 ps
CPU time	18.72 seconds
Started	Aug 13 06:30:12 PM PDT 24
Finished	Aug 13 06:30:31 PM PDT 24
Peak memory	272408 kb
Host	smart-68679d4d-b565-4a00-bfe0-6be4de96d707
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304740853 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.3304740853
Directory	/workspace/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2363918090
Short name	T296
Test name
Test status
Simulation time	137062700 ps
CPU time	14.26 seconds
Started	Aug 13 06:30:15 PM PDT 24
Finished	Aug 13 06:30:29 PM PDT 24
Peak memory	264116 kb
Host	smart-5f310454-08c1-441b-9f32-7cb836811caa
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363918090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM _TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 9.flash_ctrl_csr_rw.2363918090
Directory	/workspace/9.flash_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.3876445858
Short name	T318
Test name
Test status
Simulation time	16818600 ps
CPU time	13.49 seconds
Started	Aug 13 06:30:16 PM PDT 24
Finished	Aug 13 06:30:29 PM PDT 24
Peak memory	261608 kb
Host	smart-56b92824-0c58-4b01-9f85-dc987e6aa200
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876445858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.3 876445858
Directory	/workspace/9.flash_ctrl_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2511431998
Short name	T1172
Test name
Test status
Simulation time	63915100 ps
CPU time	14.96 seconds
Started	Aug 13 06:30:27 PM PDT 24
Finished	Aug 13 06:30:42 PM PDT 24
Peak memory	264180 kb
Host	smart-18b31521-e5dc-4776-a3b9-47e891482ab9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511431998 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 9.flash_ctrl_same_csr_outstanding.2511431998
Directory	/workspace/9.flash_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.1360265313
Short name	T1123
Test name
Test status
Simulation time	18695100 ps
CPU time	15.52 seconds
Started	Aug 13 06:30:21 PM PDT 24
Finished	Aug 13 06:30:36 PM PDT 24
Peak memory	253448 kb
Host	smart-c3ee964d-9bab-4a68-b937-39ab92ab9db4
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360265313 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo g /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors.1360265313
Directory	/workspace/9.flash_ctrl_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2376587637
Short name	T1179
Test name
Test status
Simulation time	21095700 ps
CPU time	15.9 seconds
Started	Aug 13 06:30:12 PM PDT 24
Finished	Aug 13 06:30:28 PM PDT 24
Peak memory	253420 kb
Host	smart-3faf0f9d-2f28-4ef3-b6df-1c13ff4c0ec8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376587637 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_shadow_reg_errors_with_csr_rw.2376587637
Directory	/workspace/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.4025310916
Short name	T273
Test name
Test status
Simulation time	287934000 ps
CPU time	16.26 seconds
Started	Aug 13 06:30:14 PM PDT 24
Finished	Aug 13 06:30:30 PM PDT 24
Peak memory	264212 kb
Host	smart-e1c43b3c-cbb7-41d9-a9d7-34365fcbae3b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025310916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.4 025310916
Directory	/workspace/9.flash_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.2963900123
Short name	T335
Test name
Test status
Simulation time	1448038000 ps
CPU time	770.88 seconds
Started	Aug 13 06:30:06 PM PDT 24
Finished	Aug 13 06:42:57 PM PDT 24
Peak memory	264104 kb
Host	smart-184a187d-2499-4e8c-b7ac-0177031a6077
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963900123 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl _tl_intg_err.2963900123
Directory	/workspace/9.flash_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/default/0.flash_ctrl_access_after_disable.3642713333
Short name	T38
Test name
Test status
Simulation time	34358600 ps
CPU time	13.55 seconds
Started	Aug 13 06:14:15 PM PDT 24
Finished	Aug 13 06:14:29 PM PDT 24
Peak memory	262056 kb
Host	smart-723bf4ca-7483-4123-a894-154e911dec8d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642713333 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.3642713333
Directory	/workspace/0.flash_ctrl_access_after_disable/latest

Test location	/workspace/coverage/default/0.flash_ctrl_alert_test.2247564327
Short name	T450
Test name
Test status
Simulation time	141695900 ps
CPU time	13.76 seconds
Started	Aug 13 06:14:21 PM PDT 24
Finished	Aug 13 06:14:35 PM PDT 24
Peak memory	258808 kb
Host	smart-042fe2d7-4b1d-4db1-b8b0-ec846302cf2c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247564327 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.2 247564327
Directory	/workspace/0.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/0.flash_ctrl_config_regwen.1212793884
Short name	T342
Test name
Test status
Simulation time	19523800 ps
CPU time	13.66 seconds
Started	Aug 13 06:14:12 PM PDT 24
Finished	Aug 13 06:14:26 PM PDT 24
Peak memory	261836 kb
Host	smart-7f104f3b-2ca2-404e-bffd-7a86987ace8b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212793884 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .flash_ctrl_config_regwen.1212793884
Directory	/workspace/0.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/0.flash_ctrl_connect.2148069663
Short name	T1116
Test name
Test status
Simulation time	16200700 ps
CPU time	15.77 seconds
Started	Aug 13 06:14:12 PM PDT 24
Finished	Aug 13 06:14:28 PM PDT 24
Peak memory	284688 kb
Host	smart-b5c6137a-32e0-40f3-895f-9f0489d1f3a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2148069663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.2148069663
Directory	/workspace/0.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/0.flash_ctrl_derr_detect.3826217231
Short name	T600
Test name
Test status
Simulation time	1309121700 ps
CPU time	183.34 seconds
Started	Aug 13 06:14:04 PM PDT 24
Finished	Aug 13 06:17:08 PM PDT 24
Peak memory	282436 kb
Host	smart-d9fa1a53-043d-4b21-8b26-64eea964fc37
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826217231 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_derr_detect.3826217231
Directory	/workspace/0.flash_ctrl_derr_detect/latest

Test location	/workspace/coverage/default/0.flash_ctrl_disable.795473121
Short name	T651
Test name
Test status
Simulation time	55616300 ps
CPU time	21.88 seconds
Started	Aug 13 06:14:02 PM PDT 24
Finished	Aug 13 06:14:24 PM PDT 24
Peak memory	274080 kb
Host	smart-2ed468a3-25f4-4bf6-8aa6-3c8f06e4db55
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795473121 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_disable.795473121
Directory	/workspace/0.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/0.flash_ctrl_erase_suspend.340246775
Short name	T845
Test name
Test status
Simulation time	1452439200 ps
CPU time	341.3 seconds
Started	Aug 13 06:13:40 PM PDT 24
Finished	Aug 13 06:19:21 PM PDT 24
Peak memory	263940 kb
Host	smart-a06057a2-e51d-40b1-9b6e-c4b449b1b5c6
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=340246775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.340246775
Directory	/workspace/0.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/0.flash_ctrl_fetch_code.2815290849
Short name	T42
Test name
Test status
Simulation time	106677700 ps
CPU time	19.82 seconds
Started	Aug 13 06:13:45 PM PDT 24
Finished	Aug 13 06:14:05 PM PDT 24
Peak memory	264200 kb
Host	smart-01c29f5d-0d48-4b44-ae09-4394a21299db
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815290849 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetch_code.2815290849
Directory	/workspace/0.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/0.flash_ctrl_fs_sup.4075855991
Short name	T77
Test name
Test status
Simulation time	1468547900 ps
CPU time	39.3 seconds
Started	Aug 13 06:14:16 PM PDT 24
Finished	Aug 13 06:14:55 PM PDT 24
Peak memory	263648 kb
Host	smart-e857c116-682c-4955-94b7-2fcd4217014d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075855991 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.flash_ctrl_fs_sup.4075855991
Directory	/workspace/0.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/default/0.flash_ctrl_host_addr_infection.2308944963
Short name	T587
Test name
Test status
Simulation time	27620700 ps
CPU time	27.96 seconds
Started	Aug 13 06:14:19 PM PDT 24
Finished	Aug 13 06:14:47 PM PDT 24
Peak memory	273948 kb
Host	smart-aea1288e-a594-439b-9fbf-f844d93de2e2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308944963 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.flash_ctrl_host_addr_infection.2308944963
Directory	/workspace/0.flash_ctrl_host_addr_infection/latest

Test location	/workspace/coverage/default/0.flash_ctrl_host_ctrl_arb.1168289644
Short name	T106
Test name
Test status
Simulation time	359862156700 ps
CPU time	2245.84 seconds
Started	Aug 13 06:13:44 PM PDT 24
Finished	Aug 13 06:51:10 PM PDT 24
Peak memory	264648 kb
Host	smart-b9239573-85b2-4456-864c-e43d53992cbc
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168289644 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.flash_ctrl_host_ctrl_arb.1168289644
Directory	/workspace/0.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/default/0.flash_ctrl_host_dir_rd.759202292
Short name	T75
Test name
Test status
Simulation time	182508600 ps
CPU time	89.54 seconds
Started	Aug 13 06:13:41 PM PDT 24
Finished	Aug 13 06:15:11 PM PDT 24
Peak memory	265732 kb
Host	smart-8d86b708-0920-4f32-8452-3f4ef5bf0ee5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=759202292 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.759202292
Directory	/workspace/0.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_rma.1030936224
Short name	T475
Test name
Test status
Simulation time	397580732700 ps
CPU time	1872.37 seconds
Started	Aug 13 06:13:44 PM PDT 24
Finished	Aug 13 06:44:57 PM PDT 24
Peak memory	261476 kb
Host	smart-167254bd-4221-4779-bc4e-4c2467e26b71
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030936224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.flash_ctrl_hw_rma.1030936224
Directory	/workspace/0.flash_ctrl_hw_rma/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_rma_reset.1599387720
Short name	T486
Test name
Test status
Simulation time	40123489300 ps
CPU time	866.12 seconds
Started	Aug 13 06:13:44 PM PDT 24
Finished	Aug 13 06:28:11 PM PDT 24
Peak memory	264936 kb
Host	smart-66347322-5818-456b-9c9b-ac9e7bf75487
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599387720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.flash_ctrl_hw_rma_reset.1599387720
Directory	/workspace/0.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/0.flash_ctrl_hw_sec_otp.818999201
Short name	T307
Test name
Test status
Simulation time	2008836800 ps
CPU time	158.31 seconds
Started	Aug 13 06:13:45 PM PDT 24
Finished	Aug 13 06:16:24 PM PDT 24
Peak memory	263864 kb
Host	smart-75581bf9-f4a4-416c-b7b0-7b3936533343
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818999201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw _sec_otp.818999201
Directory	/workspace/0.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/0.flash_ctrl_intr_rd.3914526351
Short name	T321
Test name
Test status
Simulation time	2982024300 ps
CPU time	201.84 seconds
Started	Aug 13 06:14:03 PM PDT 24
Finished	Aug 13 06:17:25 PM PDT 24
Peak memory	285500 kb
Host	smart-646d258d-9113-4c09-b5e0-b6253dcf9343
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914526351 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas h_ctrl_intr_rd.3914526351
Directory	/workspace/0.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/0.flash_ctrl_intr_rd_slow_flash.1225680485
Short name	T488
Test name
Test status
Simulation time	24220118300 ps
CPU time	155.07 seconds
Started	Aug 13 06:14:04 PM PDT 24
Finished	Aug 13 06:16:39 PM PDT 24
Peak memory	293784 kb
Host	smart-a4f5e97e-eb7a-41e7-8a0b-7a2820b4a5ae
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225680485 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd_slow_flash.1225680485
Directory	/workspace/0.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/0.flash_ctrl_intr_wr.2556347315
Short name	T972
Test name
Test status
Simulation time	2832658200 ps
CPU time	70.37 seconds
Started	Aug 13 06:14:04 PM PDT 24
Finished	Aug 13 06:15:15 PM PDT 24
Peak memory	261188 kb
Host	smart-77200e0c-ff55-4329-a42e-ce02f78631ff
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556347315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.flash_ctrl_intr_wr.2556347315
Directory	/workspace/0.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_intr_wr_slow_flash.808267213
Short name	T757
Test name
Test status
Simulation time	20592733100 ps
CPU time	168.41 seconds
Started	Aug 13 06:13:59 PM PDT 24
Finished	Aug 13 06:16:47 PM PDT 24
Peak memory	261116 kb
Host	smart-c27bbfc2-ebe3-48c3-9f48-6001fc9439c0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808 267213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.808267213
Directory	/workspace/0.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/0.flash_ctrl_invalid_op.2779314943
Short name	T736
Test name
Test status
Simulation time	3253776700 ps
CPU time	67.83 seconds
Started	Aug 13 06:13:41 PM PDT 24
Finished	Aug 13 06:14:49 PM PDT 24
Peak memory	264316 kb
Host	smart-b45cf81a-2d23-4661-9c6f-ce535ec18088
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779314943 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.2779314943
Directory	/workspace/0.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/0.flash_ctrl_mp_regions.2036734443
Short name	T490
Test name
Test status
Simulation time	11301300400 ps
CPU time	208.32 seconds
Started	Aug 13 06:13:45 PM PDT 24
Finished	Aug 13 06:17:13 PM PDT 24
Peak memory	265756 kb
Host	smart-dbd4cb12-35ff-4aaf-a23e-2676103972f7
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036734443 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mp_regions.2036734443
Directory	/workspace/0.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/0.flash_ctrl_otp_reset.515040692
Short name	T586
Test name
Test status
Simulation time	36808600 ps
CPU time	111.03 seconds
Started	Aug 13 06:13:46 PM PDT 24
Finished	Aug 13 06:15:37 PM PDT 24
Peak memory	260608 kb
Host	smart-2a3d49b1-408e-4405-81ff-2da664e8ccca
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515040692 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_otp _reset.515040692
Directory	/workspace/0.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/0.flash_ctrl_oversize_error.4106986244
Short name	T34
Test name
Test status
Simulation time	24912244100 ps
CPU time	239.55 seconds
Started	Aug 13 06:14:03 PM PDT 24
Finished	Aug 13 06:18:02 PM PDT 24
Peak memory	282392 kb
Host	smart-d82ab082-2e10-4451-9228-34c4a59e4d52
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106986244 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_oversize_error.4106986244
Directory	/workspace/0.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/0.flash_ctrl_phy_ack_consistency.1398855749
Short name	T203
Test name
Test status
Simulation time	15891900 ps
CPU time	13.67 seconds
Started	Aug 13 06:14:11 PM PDT 24
Finished	Aug 13 06:14:25 PM PDT 24
Peak memory	265636 kb
Host	smart-88eba0f4-95c8-4209-8d8b-d617879aa8a9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_ check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1398855749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.1398855749
Directory	/workspace/0.flash_ctrl_phy_ack_consistency/latest

Test location	/workspace/coverage/default/0.flash_ctrl_phy_arb.322137655
Short name	T752
Test name
Test status
Simulation time	951187500 ps
CPU time	296.53 seconds
Started	Aug 13 06:13:40 PM PDT 24
Finished	Aug 13 06:18:37 PM PDT 24
Peak memory	263648 kb
Host	smart-34980bc2-8c7c-4135-b4a7-b5dc04cbc41b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=322137655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.322137655
Directory	/workspace/0.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/0.flash_ctrl_prog_reset.1716590861
Short name	T254
Test name
Test status
Simulation time	20487000 ps
CPU time	13.55 seconds
Started	Aug 13 06:14:02 PM PDT 24
Finished	Aug 13 06:14:16 PM PDT 24
Peak memory	265772 kb
Host	smart-d888b305-505a-456d-852a-23710dfae7d2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716590861 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 0.flash_ctrl_prog_reset.1716590861
Directory	/workspace/0.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rand_ops.3159668228
Short name	T827
Test name
Test status
Simulation time	133168100 ps
CPU time	917.06 seconds
Started	Aug 13 06:13:37 PM PDT 24
Finished	Aug 13 06:28:54 PM PDT 24
Peak memory	286880 kb
Host	smart-17a1a4c4-9218-49bc-ab6f-1c855b403eca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3159668228 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.3159668228
Directory	/workspace/0.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rd_buff_evict.3660012555
Short name	T945
Test name
Test status
Simulation time	1604691500 ps
CPU time	142.77 seconds
Started	Aug 13 06:13:36 PM PDT 24
Finished	Aug 13 06:15:59 PM PDT 24
Peak memory	263316 kb
Host	smart-9807d23c-0e90-41f3-a1d8-7c420f76f731
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3660012555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.3660012555
Directory	/workspace/0.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rd_intg.3458610559
Short name	T326
Test name
Test status
Simulation time	64472600 ps
CPU time	31.81 seconds
Started	Aug 13 06:14:11 PM PDT 24
Finished	Aug 13 06:14:43 PM PDT 24
Peak memory	276224 kb
Host	smart-e701f8c1-6788-4739-a587-d262fa048100
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458610559 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.flash_ctrl_rd_intg.3458610559
Directory	/workspace/0.flash_ctrl_rd_intg/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rd_ooo.525966234
Short name	T788
Test name
Test status
Simulation time	137749400 ps
CPU time	45.87 seconds
Started	Aug 13 06:14:16 PM PDT 24
Finished	Aug 13 06:15:02 PM PDT 24
Peak memory	276452 kb
Host	smart-34a873f4-e03f-4911-a97c-702a739a8cbb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525966234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.flash_ctrl_rd_ooo.525966234
Directory	/workspace/0.flash_ctrl_rd_ooo/latest

Test location	/workspace/coverage/default/0.flash_ctrl_re_evict.3716516279
Short name	T701
Test name
Test status
Simulation time	184849300 ps
CPU time	33.63 seconds
Started	Aug 13 06:14:03 PM PDT 24
Finished	Aug 13 06:14:36 PM PDT 24
Peak memory	274164 kb
Host	smart-bd5a6559-27d4-465f-9d81-13217d6dc1db
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716516279 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla sh_ctrl_re_evict.3716516279
Directory	/workspace/0.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/0.flash_ctrl_read_word_sweep.738699131
Short name	T957
Test name
Test status
Simulation time	83495900 ps
CPU time	14.35 seconds
Started	Aug 13 06:13:53 PM PDT 24
Finished	Aug 13 06:14:07 PM PDT 24
Peak memory	265584 kb
Host	smart-af3cefa9-9b40-4305-b17e-5a27a315f33b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=738699131 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep. 738699131
Directory	/workspace/0.flash_ctrl_read_word_sweep/latest

Test location	/workspace/coverage/default/0.flash_ctrl_read_word_sweep_derr.477985924
Short name	T484
Test name
Test status
Simulation time	87043800 ps
CPU time	21.46 seconds
Started	Aug 13 06:13:52 PM PDT 24
Finished	Aug 13 06:14:14 PM PDT 24
Peak memory	265552 kb
Host	smart-94427309-2268-424f-bad4-c1d9aaf5004a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477985924 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_derr.477985924
Directory	/workspace/0.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.1500024023
Short name	T652
Test name
Test status
Simulation time	46578800 ps
CPU time	22.7 seconds
Started	Aug 13 06:13:53 PM PDT 24
Finished	Aug 13 06:14:16 PM PDT 24
Peak memory	265940 kb
Host	smart-6e8faab9-07cf-4919-bb94-f0ff6ea6e13e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500024023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fl ash_ctrl_read_word_sweep_serr.1500024023
Directory	/workspace/0.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_ro.112178268
Short name	T750
Test name
Test status
Simulation time	3211651700 ps
CPU time	116.4 seconds
Started	Aug 13 06:13:53 PM PDT 24
Finished	Aug 13 06:15:49 PM PDT 24
Peak memory	290652 kb
Host	smart-0ad936db-2b67-4657-b8b6-18af3b2202ce
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112178268 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.flash_ctrl_ro.112178268
Directory	/workspace/0.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/0.flash_ctrl_ro_derr.2128926289
Short name	T156
Test name
Test status
Simulation time	2499606600 ps
CPU time	140.14 seconds
Started	Aug 13 06:13:55 PM PDT 24
Finished	Aug 13 06:16:15 PM PDT 24
Peak memory	282372 kb
Host	smart-e2caa417-8bbb-44f6-9213-0f0c1609f051
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2128926289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.2128926289
Directory	/workspace/0.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_ro_serr.969864559
Short name	T807
Test name
Test status
Simulation time	2646788500 ps
CPU time	139.99 seconds
Started	Aug 13 06:13:53 PM PDT 24
Finished	Aug 13 06:16:13 PM PDT 24
Peak memory	295832 kb
Host	smart-8a4a3d2c-2b37-4e0a-9477-43d007b6ca7a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969864559 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.flash_ctrl_ro_serr.969864559
Directory	/workspace/0.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rw.2549625504
Short name	T1102
Test name
Test status
Simulation time	4789673100 ps
CPU time	436.48 seconds
Started	Aug 13 06:13:52 PM PDT 24
Finished	Aug 13 06:21:09 PM PDT 24
Peak memory	310228 kb
Host	smart-5857558c-8db1-4bc4-bb44-920156cdf29c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549625504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.flash_ctrl_rw.2549625504
Directory	/workspace/0.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rw_derr.2003463141
Short name	T257
Test name
Test status
Simulation time	8813661700 ps
CPU time	222.3 seconds
Started	Aug 13 06:13:52 PM PDT 24
Finished	Aug 13 06:17:35 PM PDT 24
Peak memory	288808 kb
Host	smart-115091e1-c245-4cb3-bd65-ffa02defb95d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003463141 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_derr.2003463141
Directory	/workspace/0.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rw_evict.2624848515
Short name	T512
Test name
Test status
Simulation time	149475500 ps
CPU time	31.4 seconds
Started	Aug 13 06:14:02 PM PDT 24
Finished	Aug 13 06:14:34 PM PDT 24
Peak memory	274152 kb
Host	smart-78717098-2d48-4818-b031-ebacbde16fe9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624848515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.fla sh_ctrl_rw_evict.2624848515
Directory	/workspace/0.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/0.flash_ctrl_rw_serr.1816920924
Short name	T253
Test name
Test status
Simulation time	2776273400 ps
CPU time	174.74 seconds
Started	Aug 13 06:13:48 PM PDT 24
Finished	Aug 13 06:16:43 PM PDT 24
Peak memory	295684 kb
Host	smart-4de79ef4-cb83-4e0d-8ddb-c4a799255faf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816920924 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.flash_ctrl_rw_serr.1816920924
Directory	/workspace/0.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/0.flash_ctrl_sec_cm.3401403921
Short name	T111
Test name
Test status
Simulation time	1425615500 ps
CPU time	4856 seconds
Started	Aug 13 06:14:01 PM PDT 24
Finished	Aug 13 07:34:58 PM PDT 24
Peak memory	287892 kb
Host	smart-647c2f47-7d33-436c-9d50-3f713b510ef2
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401403921 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.3401403921
Directory	/workspace/0.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/0.flash_ctrl_serr_address.1119519730
Short name	T789
Test name
Test status
Simulation time	660381800 ps
CPU time	64.16 seconds
Started	Aug 13 06:13:51 PM PDT 24
Finished	Aug 13 06:14:56 PM PDT 24
Peak memory	265916 kb
Host	smart-1a5aa72e-d650-470c-b362-f40479ca97ae
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119519730 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.flash_ctrl_serr_address.1119519730
Directory	/workspace/0.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/0.flash_ctrl_serr_counter.2905217904
Short name	T689
Test name
Test status
Simulation time	509269200 ps
CPU time	62.97 seconds
Started	Aug 13 06:13:52 PM PDT 24
Finished	Aug 13 06:14:55 PM PDT 24
Peak memory	274276 kb
Host	smart-2b72c681-0a47-4946-953f-664f45a7084c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905217904 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.flash_ctrl_serr_counter.2905217904
Directory	/workspace/0.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/0.flash_ctrl_smoke.760516155
Short name	T744
Test name
Test status
Simulation time	45280100 ps
CPU time	100.92 seconds
Started	Aug 13 06:13:40 PM PDT 24
Finished	Aug 13 06:15:21 PM PDT 24
Peak memory	277448 kb
Host	smart-f0edd2d6-766e-4438-a970-920f9db8edc8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=760516155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.760516155
Directory	/workspace/0.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/0.flash_ctrl_smoke_hw.1845573612
Short name	T211
Test name
Test status
Simulation time	82553300 ps
CPU time	26.18 seconds
Started	Aug 13 06:13:41 PM PDT 24
Finished	Aug 13 06:14:08 PM PDT 24
Peak memory	260284 kb
Host	smart-dba3161d-33f1-4149-bcb7-6ca4e212dc87
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1845573612 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.1845573612
Directory	/workspace/0.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/0.flash_ctrl_stress_all.987381988
Short name	T1016
Test name
Test status
Simulation time	128625600 ps
CPU time	137.93 seconds
Started	Aug 13 06:14:13 PM PDT 24
Finished	Aug 13 06:16:31 PM PDT 24
Peak memory	278504 kb
Host	smart-2302055b-11fe-4c03-9866-8adeda02d4f9
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987381988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stress _all.987381988
Directory	/workspace/0.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/0.flash_ctrl_sw_op.3438598503
Short name	T612
Test name
Test status
Simulation time	104636200 ps
CPU time	26.44 seconds
Started	Aug 13 06:13:36 PM PDT 24
Finished	Aug 13 06:14:03 PM PDT 24
Peak memory	260164 kb
Host	smart-98ab5c9d-1ec9-4c1d-add5-a969cd0b7011
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3438598503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.3438598503
Directory	/workspace/0.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/0.flash_ctrl_wo.3369393804
Short name	T541
Test name
Test status
Simulation time	17375571400 ps
CPU time	204.7 seconds
Started	Aug 13 06:13:44 PM PDT 24
Finished	Aug 13 06:17:09 PM PDT 24
Peak memory	260036 kb
Host	smart-784cc46c-9d07-4b7f-ad83-a4351090a9c5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369393804 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.flash_ctrl_wo.3369393804
Directory	/workspace/0.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/0.flash_ctrl_write_word_sweep.4277072840
Short name	T934
Test name
Test status
Simulation time	147086700 ps
CPU time	15.08 seconds
Started	Aug 13 06:13:54 PM PDT 24
Finished	Aug 13 06:14:10 PM PDT 24
Peak memory	259216 kb
Host	smart-2151563a-f657-40b2-ac2a-f9d15703c9d2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4277072840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_swe ep.4277072840
Directory	/workspace/0.flash_ctrl_write_word_sweep/latest

Test location	/workspace/coverage/default/1.flash_ctrl_access_after_disable.1751074966
Short name	T7
Test name
Test status
Simulation time	15005700 ps
CPU time	13.79 seconds
Started	Aug 13 06:14:59 PM PDT 24
Finished	Aug 13 06:15:13 PM PDT 24
Peak memory	261992 kb
Host	smart-3328eccc-c5eb-4706-82e6-14608d9bee19
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751074966 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.1751074966
Directory	/workspace/1.flash_ctrl_access_after_disable/latest

Test location	/workspace/coverage/default/1.flash_ctrl_alert_test.1706890994
Short name	T958
Test name
Test status
Simulation time	35621300 ps
CPU time	13.5 seconds
Started	Aug 13 06:15:00 PM PDT 24
Finished	Aug 13 06:15:13 PM PDT 24
Peak memory	258832 kb
Host	smart-2ab6a4dc-c640-49bb-b563-40833f385a17
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706890994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.1 706890994
Directory	/workspace/1.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/1.flash_ctrl_config_regwen.2002413571
Short name	T1089
Test name
Test status
Simulation time	29271200 ps
CPU time	14.1 seconds
Started	Aug 13 06:15:00 PM PDT 24
Finished	Aug 13 06:15:14 PM PDT 24
Peak memory	262200 kb
Host	smart-1dea3e30-2b88-4da1-884c-300603796f65
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002413571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .flash_ctrl_config_regwen.2002413571
Directory	/workspace/1.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/1.flash_ctrl_connect.343132887
Short name	T976
Test name
Test status
Simulation time	114833800 ps
CPU time	15.75 seconds
Started	Aug 13 06:14:48 PM PDT 24
Finished	Aug 13 06:15:03 PM PDT 24
Peak memory	283672 kb
Host	smart-54543d03-d43a-478f-84fd-0db5b7eb2f7b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=343132887 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.343132887
Directory	/workspace/1.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/1.flash_ctrl_derr_detect.333627059
Short name	T706
Test name
Test status
Simulation time	996231800 ps
CPU time	186.77 seconds
Started	Aug 13 06:14:39 PM PDT 24
Finished	Aug 13 06:17:46 PM PDT 24
Peak memory	278688 kb
Host	smart-28cf4b62-514d-4471-ba87-46485f116e2d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333627059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_derr_detect.333627059
Directory	/workspace/1.flash_ctrl_derr_detect/latest

Test location	/workspace/coverage/default/1.flash_ctrl_error_mp.15941989
Short name	T5
Test name
Test status
Simulation time	23538593500 ps
CPU time	2318.82 seconds
Started	Aug 13 06:14:31 PM PDT 24
Finished	Aug 13 06:53:10 PM PDT 24
Peak memory	263352 kb
Host	smart-b569341d-c891-454b-9c35-3af280ec8c65
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=15941989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_mp.15941989
Directory	/workspace/1.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/1.flash_ctrl_error_prog_type.3280477344
Short name	T1065
Test name
Test status
Simulation time	3311027400 ps
CPU time	2852.92 seconds
Started	Aug 13 06:14:35 PM PDT 24
Finished	Aug 13 07:02:08 PM PDT 24
Peak memory	265756 kb
Host	smart-cc88e69c-0956-4d9a-9225-f1826f2ca1b4
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280477344 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.flash_ctrl_error_prog_type.3280477344
Directory	/workspace/1.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/1.flash_ctrl_error_prog_win.891451344
Short name	T907
Test name
Test status
Simulation time	1669333100 ps
CPU time	887.82 seconds
Started	Aug 13 06:14:37 PM PDT 24
Finished	Aug 13 06:29:25 PM PDT 24
Peak memory	273980 kb
Host	smart-f2200b9e-fc03-4f84-a5a9-de57ad84e14c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=891451344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.891451344
Directory	/workspace/1.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/1.flash_ctrl_fetch_code.2425483743
Short name	T45
Test name
Test status
Simulation time	1095464500 ps
CPU time	24.74 seconds
Started	Aug 13 06:14:28 PM PDT 24
Finished	Aug 13 06:14:52 PM PDT 24
Peak memory	263164 kb
Host	smart-4d3fcd8b-587a-48e1-a628-29c3cd91f9e8
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425483743 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetch_code.2425483743
Directory	/workspace/1.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/1.flash_ctrl_fs_sup.2467463470
Short name	T682
Test name
Test status
Simulation time	1211265200 ps
CPU time	38.9 seconds
Started	Aug 13 06:15:00 PM PDT 24
Finished	Aug 13 06:15:39 PM PDT 24
Peak memory	265520 kb
Host	smart-1b92b6f3-c75e-436e-8319-52c4cb763d41
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467463470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.flash_ctrl_fs_sup.2467463470
Directory	/workspace/1.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/default/1.flash_ctrl_full_mem_access.2671111487
Short name	T143
Test name
Test status
Simulation time	227211788300 ps
CPU time	2477.45 seconds
Started	Aug 13 06:14:37 PM PDT 24
Finished	Aug 13 06:55:55 PM PDT 24
Peak memory	265820 kb
Host	smart-79747968-a98d-4392-80cd-4ae2db87ef64
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671111487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_c trl_full_mem_access.2671111487
Directory	/workspace/1.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/1.flash_ctrl_host_addr_infection.2666324187
Short name	T664
Test name
Test status
Simulation time	252034900 ps
CPU time	31.14 seconds
Started	Aug 13 06:14:59 PM PDT 24
Finished	Aug 13 06:15:30 PM PDT 24
Peak memory	274032 kb
Host	smart-f90d36d0-1211-45c1-8aab-5b14dfd34d26
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666324187 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.flash_ctrl_host_addr_infection.2666324187
Directory	/workspace/1.flash_ctrl_host_addr_infection/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.3925313518
Short name	T278
Test name
Test status
Simulation time	15401700 ps
CPU time	13.4 seconds
Started	Aug 13 06:14:58 PM PDT 24
Finished	Aug 13 06:15:12 PM PDT 24
Peak memory	259024 kb
Host	smart-2483e5bc-dfa8-46f7-aeba-ae66da67d3fc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925313518 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_read_seed_err.3925313518
Directory	/workspace/1.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_rma.1820657377
Short name	T64
Test name
Test status
Simulation time	232765797100 ps
CPU time	1879.94 seconds
Started	Aug 13 06:14:27 PM PDT 24
Finished	Aug 13 06:45:47 PM PDT 24
Peak memory	265692 kb
Host	smart-7e6ac45b-f06c-46ee-8196-b1aacf055e7e
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820657377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.flash_ctrl_hw_rma.1820657377
Directory	/workspace/1.flash_ctrl_hw_rma/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_rma_reset.2862987751
Short name	T1113
Test name
Test status
Simulation time	160198177100 ps
CPU time	880.38 seconds
Started	Aug 13 06:14:25 PM PDT 24
Finished	Aug 13 06:29:05 PM PDT 24
Peak memory	261420 kb
Host	smart-cbbdda88-4ed4-45e9-a597-2b1995572b40
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862987751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.flash_ctrl_hw_rma_reset.2862987751
Directory	/workspace/1.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/1.flash_ctrl_hw_sec_otp.3806712448
Short name	T309
Test name
Test status
Simulation time	10902445100 ps
CPU time	214.03 seconds
Started	Aug 13 06:14:28 PM PDT 24
Finished	Aug 13 06:18:02 PM PDT 24
Peak memory	263876 kb
Host	smart-935cbffd-77ed-4789-a8d1-834e5aa59fe5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806712448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_h w_sec_otp.3806712448
Directory	/workspace/1.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/1.flash_ctrl_integrity.308262238
Short name	T1087
Test name
Test status
Simulation time	3593898200 ps
CPU time	589.21 seconds
Started	Aug 13 06:14:42 PM PDT 24
Finished	Aug 13 06:24:31 PM PDT 24
Peak memory	324824 kb
Host	smart-ae79d351-74b9-453b-868b-60d2690da0bf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308262238 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.flash_ctrl_integrity.308262238
Directory	/workspace/1.flash_ctrl_integrity/latest

Test location	/workspace/coverage/default/1.flash_ctrl_intr_rd.3166835214
Short name	T843
Test name
Test status
Simulation time	3443309700 ps
CPU time	309.24 seconds
Started	Aug 13 06:14:41 PM PDT 24
Finished	Aug 13 06:19:50 PM PDT 24
Peak memory	285472 kb
Host	smart-a34c1d7d-165d-4af6-9822-6028a104082d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166835214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas h_ctrl_intr_rd.3166835214
Directory	/workspace/1.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.2888935457
Short name	T563
Test name
Test status
Simulation time	47579214600 ps
CPU time	337.12 seconds
Started	Aug 13 06:14:41 PM PDT 24
Finished	Aug 13 06:20:18 PM PDT 24
Peak memory	285780 kb
Host	smart-b3ce9603-c90e-4e94-bbc1-e7a8e91597d2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888935457 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd_slow_flash.2888935457
Directory	/workspace/1.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/1.flash_ctrl_intr_wr.633735686
Short name	T629
Test name
Test status
Simulation time	2386454100 ps
CPU time	51.41 seconds
Started	Aug 13 06:14:42 PM PDT 24
Finished	Aug 13 06:15:33 PM PDT 24
Peak memory	260452 kb
Host	smart-2b3436f6-f7d4-417d-b69c-1e6b1b42774b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633735686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.flash_ctrl_intr_wr.633735686
Directory	/workspace/1.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_invalid_op.2061332630
Short name	T781
Test name
Test status
Simulation time	2219219400 ps
CPU time	59.4 seconds
Started	Aug 13 06:14:36 PM PDT 24
Finished	Aug 13 06:15:36 PM PDT 24
Peak memory	264220 kb
Host	smart-13ca82d3-adb3-40a0-8687-67ed3fe1379e
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061332630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.2061332630
Directory	/workspace/1.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/1.flash_ctrl_lcmgr_intg.1042281148
Short name	T973
Test name
Test status
Simulation time	16050000 ps
CPU time	13.3 seconds
Started	Aug 13 06:14:58 PM PDT 24
Finished	Aug 13 06:15:11 PM PDT 24
Peak memory	260788 kb
Host	smart-72e2b796-bb2b-4424-b103-0cfc7d8a9bff
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042281148 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 1.flash_ctrl_lcmgr_intg.1042281148
Directory	/workspace/1.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/1.flash_ctrl_mid_op_rst.1474524342
Short name	T167
Test name
Test status
Simulation time	3302657200 ps
CPU time	70.59 seconds
Started	Aug 13 06:14:34 PM PDT 24
Finished	Aug 13 06:15:45 PM PDT 24
Peak memory	261120 kb
Host	smart-7146a726-ff82-4579-936c-db8277537980
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1474524342 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.1474524342
Directory	/workspace/1.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/1.flash_ctrl_mp_regions.3333324980
Short name	T122
Test name
Test status
Simulation time	113168731600 ps
CPU time	517.89 seconds
Started	Aug 13 06:14:27 PM PDT 24
Finished	Aug 13 06:23:05 PM PDT 24
Peak memory	274596 kb
Host	smart-d9d39041-b186-456b-9bbb-fae378c5185e
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333324980 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mp_regions.3333324980
Directory	/workspace/1.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/1.flash_ctrl_otp_reset.2358432367
Short name	T503
Test name
Test status
Simulation time	147886100 ps
CPU time	130.52 seconds
Started	Aug 13 06:14:27 PM PDT 24
Finished	Aug 13 06:16:38 PM PDT 24
Peak memory	260532 kb
Host	smart-0da06304-c361-4338-91b8-9253b2ba8632
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358432367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ot p_reset.2358432367
Directory	/workspace/1.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/1.flash_ctrl_oversize_error.1400589496
Short name	T198
Test name
Test status
Simulation time	1396423300 ps
CPU time	197.27 seconds
Started	Aug 13 06:14:42 PM PDT 24
Finished	Aug 13 06:17:59 PM PDT 24
Peak memory	282448 kb
Host	smart-e284a88a-2c66-4b05-a679-8e67ac4894d9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400589496 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_oversize_error.1400589496
Directory	/workspace/1.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/1.flash_ctrl_phy_arb.3336798368
Short name	T442
Test name
Test status
Simulation time	156010100 ps
CPU time	319.78 seconds
Started	Aug 13 06:14:19 PM PDT 24
Finished	Aug 13 06:19:39 PM PDT 24
Peak memory	263600 kb
Host	smart-fe0e97b3-1143-4a6a-9a7d-c01917decf56
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3336798368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.3336798368
Directory	/workspace/1.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/1.flash_ctrl_phy_arb_redun.3370159461
Short name	T67
Test name
Test status
Simulation time	851772900 ps
CPU time	16.1 seconds
Started	Aug 13 06:14:59 PM PDT 24
Finished	Aug 13 06:15:16 PM PDT 24
Peak memory	263956 kb
Host	smart-ed0b5d33-3dc0-4555-b620-285729228fcb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370159461 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.3370159461
Directory	/workspace/1.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/default/1.flash_ctrl_phy_host_grant_err.3699378616
Short name	T743
Test name
Test status
Simulation time	43652100 ps
CPU time	14.17 seconds
Started	Aug 13 06:14:55 PM PDT 24
Finished	Aug 13 06:15:09 PM PDT 24
Peak memory	263660 kb
Host	smart-33eaa828-be1f-499b-983b-6b4912668631
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699378616 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.3699378616
Directory	/workspace/1.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/1.flash_ctrl_prog_reset.3664949953
Short name	T796
Test name
Test status
Simulation time	2766800000 ps
CPU time	235.73 seconds
Started	Aug 13 06:14:50 PM PDT 24
Finished	Aug 13 06:18:46 PM PDT 24
Peak memory	261128 kb
Host	smart-d8523ec1-443d-4047-b2e8-fac22c86e561
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664949953 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.flash_ctrl_prog_reset.3664949953
Directory	/workspace/1.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rand_ops.232138802
Short name	T1059
Test name
Test status
Simulation time	94653500 ps
CPU time	222.09 seconds
Started	Aug 13 06:14:20 PM PDT 24
Finished	Aug 13 06:18:02 PM PDT 24
Peak memory	274772 kb
Host	smart-ca765bad-e837-41fe-8740-9d74f939821f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=232138802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.232138802
Directory	/workspace/1.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rd_buff_evict.3905280887
Short name	T505
Test name
Test status
Simulation time	1807601900 ps
CPU time	139.08 seconds
Started	Aug 13 06:14:20 PM PDT 24
Finished	Aug 13 06:16:39 PM PDT 24
Peak memory	263444 kb
Host	smart-3ed7046c-e4cf-4fbe-8b58-44bc7638ddf5
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3905280887 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.3905280887
Directory	/workspace/1.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rd_intg.1810220973
Short name	T327
Test name
Test status
Simulation time	64485100 ps
CPU time	32.52 seconds
Started	Aug 13 06:14:52 PM PDT 24
Finished	Aug 13 06:15:24 PM PDT 24
Peak memory	276216 kb
Host	smart-3a00b6d7-9cdc-497a-aa14-ba139bc03b0b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810220973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.flash_ctrl_rd_intg.1810220973
Directory	/workspace/1.flash_ctrl_rd_intg/latest

Test location	/workspace/coverage/default/1.flash_ctrl_re_evict.1514736827
Short name	T556
Test name
Test status
Simulation time	68986000 ps
CPU time	33.78 seconds
Started	Aug 13 06:14:52 PM PDT 24
Finished	Aug 13 06:15:26 PM PDT 24
Peak memory	276572 kb
Host	smart-4d709c3c-d6c2-413f-b920-e62f96134408
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514736827 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fla sh_ctrl_re_evict.1514736827
Directory	/workspace/1.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/1.flash_ctrl_read_word_sweep_derr.3251649424
Short name	T1069
Test name
Test status
Simulation time	31518700 ps
CPU time	23.02 seconds
Started	Aug 13 06:14:43 PM PDT 24
Finished	Aug 13 06:15:06 PM PDT 24
Peak memory	265588 kb
Host	smart-c8441215-65f6-4de7-a989-784573a37276
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251649424 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_derr.3251649424
Directory	/workspace/1.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_read_word_sweep_serr.3334279954
Short name	T940
Test name
Test status
Simulation time	24396800 ps
CPU time	23.2 seconds
Started	Aug 13 06:14:35 PM PDT 24
Finished	Aug 13 06:14:58 PM PDT 24
Peak memory	265940 kb
Host	smart-28eda2a2-c13c-48aa-a918-d52a6fa16137
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334279954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.fl ash_ctrl_read_word_sweep_serr.3334279954
Directory	/workspace/1.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rma_err.1537409492
Short name	T188
Test name
Test status
Simulation time	83806140100 ps
CPU time	892.49 seconds
Started	Aug 13 06:14:58 PM PDT 24
Finished	Aug 13 06:29:51 PM PDT 24
Peak memory	261884 kb
Host	smart-ceff8c80-a4fa-4855-9244-5e2b2f0e4b09
User	root
Command	/workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537409492 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rma_err.1537409492
Directory	/workspace/1.flash_ctrl_rma_err/latest

Test location	/workspace/coverage/default/1.flash_ctrl_ro.2644777386
Short name	T819
Test name
Test status
Simulation time	964073400 ps
CPU time	95.94 seconds
Started	Aug 13 06:14:36 PM PDT 24
Finished	Aug 13 06:16:12 PM PDT 24
Peak memory	282408 kb
Host	smart-1976c94e-36a2-4b1b-ae75-be22ca90df07
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644777386 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.flash_ctrl_ro.2644777386
Directory	/workspace/1.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/1.flash_ctrl_ro_derr.2505066447
Short name	T158
Test name
Test status
Simulation time	644517100 ps
CPU time	155.06 seconds
Started	Aug 13 06:14:41 PM PDT 24
Finished	Aug 13 06:17:16 PM PDT 24
Peak memory	282416 kb
Host	smart-ba8ab0d0-f490-4ebe-bc58-64d77c7dee91
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2505066447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.2505066447
Directory	/workspace/1.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_ro_serr.1558842105
Short name	T14
Test name
Test status
Simulation time	2778329400 ps
CPU time	163.97 seconds
Started	Aug 13 06:14:36 PM PDT 24
Finished	Aug 13 06:17:20 PM PDT 24
Peak memory	291172 kb
Host	smart-1ea7b622-9f9b-4645-97be-90123bdec9f1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558842105 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.flash_ctrl_ro_serr.1558842105
Directory	/workspace/1.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rw_evict_all_en.2128183007
Short name	T282
Test name
Test status
Simulation time	44781300 ps
CPU time	31.27 seconds
Started	Aug 13 06:14:53 PM PDT 24
Finished	Aug 13 06:15:24 PM PDT 24
Peak memory	275496 kb
Host	smart-64f52f0a-c0a7-4fef-a9aa-82ad4ffffdd7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128183007 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict_all_en.2128183007
Directory	/workspace/1.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/1.flash_ctrl_rw_serr.3831930369
Short name	T979
Test name
Test status
Simulation time	8425557600 ps
CPU time	263.22 seconds
Started	Aug 13 06:14:35 PM PDT 24
Finished	Aug 13 06:18:58 PM PDT 24
Peak memory	297920 kb
Host	smart-47fa046b-ae28-493a-9753-42ea024abcf5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831930369 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.flash_ctrl_rw_serr.3831930369
Directory	/workspace/1.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/1.flash_ctrl_sec_cm.2703850773
Short name	T32
Test name
Test status
Simulation time	6326405000 ps
CPU time	4935.64 seconds
Started	Aug 13 06:14:50 PM PDT 24
Finished	Aug 13 07:37:06 PM PDT 24
Peak memory	287652 kb
Host	smart-bd236754-9fe4-4d0c-ad2e-d2b76ba00fcb
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703850773 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.2703850773
Directory	/workspace/1.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/1.flash_ctrl_sec_info_access.3763774841
Short name	T942
Test name
Test status
Simulation time	4028063400 ps
CPU time	70.44 seconds
Started	Aug 13 06:14:52 PM PDT 24
Finished	Aug 13 06:16:02 PM PDT 24
Peak memory	264296 kb
Host	smart-80d5a71b-b0ea-410d-b626-34562b7509b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3763774841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.3763774841
Directory	/workspace/1.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/1.flash_ctrl_serr_address.3661331719
Short name	T962
Test name
Test status
Simulation time	2060288400 ps
CPU time	67.62 seconds
Started	Aug 13 06:14:42 PM PDT 24
Finished	Aug 13 06:15:49 PM PDT 24
Peak memory	265928 kb
Host	smart-9bbd5323-ddba-46c1-be74-6aed63b4f5d0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661331719 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.flash_ctrl_serr_address.3661331719
Directory	/workspace/1.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/1.flash_ctrl_serr_counter.10987695
Short name	T1103
Test name
Test status
Simulation time	1475552100 ps
CPU time	75.82 seconds
Started	Aug 13 06:14:34 PM PDT 24
Finished	Aug 13 06:15:50 PM PDT 24
Peak memory	274216 kb
Host	smart-c6d5fb08-80ef-49d1-94e6-73601d3dd2fa
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10987695 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_serr_counter.10987695
Directory	/workspace/1.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/1.flash_ctrl_smoke.1924255227
Short name	T229
Test name
Test status
Simulation time	111606200 ps
CPU time	119.58 seconds
Started	Aug 13 06:14:18 PM PDT 24
Finished	Aug 13 06:16:18 PM PDT 24
Peak memory	277020 kb
Host	smart-da8793a9-a1e6-47a1-a787-c3dbf985a71a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1924255227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.1924255227
Directory	/workspace/1.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/1.flash_ctrl_smoke_hw.2088076283
Short name	T693
Test name
Test status
Simulation time	64672200 ps
CPU time	26.27 seconds
Started	Aug 13 06:14:15 PM PDT 24
Finished	Aug 13 06:14:41 PM PDT 24
Peak memory	260268 kb
Host	smart-f0fae767-52fd-40ed-b010-ca1055b450e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2088076283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.2088076283
Directory	/workspace/1.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/1.flash_ctrl_stress_all.2634759468
Short name	T1004
Test name
Test status
Simulation time	3334522400 ps
CPU time	894.92 seconds
Started	Aug 13 06:14:50 PM PDT 24
Finished	Aug 13 06:29:45 PM PDT 24
Peak memory	287172 kb
Host	smart-85ac3cc3-4179-42d7-905e-7368ccad8827
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634759468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stres s_all.2634759468
Directory	/workspace/1.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/1.flash_ctrl_sw_op.4071367370
Short name	T1034
Test name
Test status
Simulation time	23631700 ps
CPU time	26.5 seconds
Started	Aug 13 06:14:18 PM PDT 24
Finished	Aug 13 06:14:45 PM PDT 24
Peak memory	260120 kb
Host	smart-4f979ce0-220b-44d9-a5c3-8c156643bfd3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4071367370 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.4071367370
Directory	/workspace/1.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/1.flash_ctrl_wo.2799985043
Short name	T901
Test name
Test status
Simulation time	9016643800 ps
CPU time	165.48 seconds
Started	Aug 13 06:14:35 PM PDT 24
Finished	Aug 13 06:17:20 PM PDT 24
Peak memory	260528 kb
Host	smart-31c20aa8-262a-4748-bd23-4f63d411a442
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799985043 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.flash_ctrl_wo.2799985043
Directory	/workspace/1.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/10.flash_ctrl_alert_test.2835634380
Short name	T1002
Test name
Test status
Simulation time	22042500 ps
CPU time	13.49 seconds
Started	Aug 13 06:18:14 PM PDT 24
Finished	Aug 13 06:18:27 PM PDT 24
Peak memory	258652 kb
Host	smart-0992109e-4c59-4615-909f-914ce2e5277a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835634380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test. 2835634380
Directory	/workspace/10.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/10.flash_ctrl_connect.1885184613
Short name	T1035
Test name
Test status
Simulation time	15973800 ps
CPU time	15.69 seconds
Started	Aug 13 06:18:14 PM PDT 24
Finished	Aug 13 06:18:29 PM PDT 24
Peak memory	283500 kb
Host	smart-9556e238-4763-4e91-bd8c-d18734bc64d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1885184613 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.1885184613
Directory	/workspace/10.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.4121171890
Short name	T80
Test name
Test status
Simulation time	10012092100 ps
CPU time	326.89 seconds
Started	Aug 13 06:18:12 PM PDT 24
Finished	Aug 13 06:23:39 PM PDT 24
Peak memory	326604 kb
Host	smart-a032f3e8-9f17-496e-8361-69e8f5944d4f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121171890 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.4121171890
Directory	/workspace/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/10.flash_ctrl_hw_read_seed_err.943597188
Short name	T168
Test name
Test status
Simulation time	128188500 ps
CPU time	13.38 seconds
Started	Aug 13 06:18:13 PM PDT 24
Finished	Aug 13 06:18:26 PM PDT 24
Peak memory	258900 kb
Host	smart-9180768b-f161-4041-be15-9f3ed25cf3d5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943597188 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_read_seed_err.943597188
Directory	/workspace/10.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/10.flash_ctrl_hw_rma_reset.4135775962
Short name	T192
Test name
Test status
Simulation time	80135324700 ps
CPU time	806.4 seconds
Started	Aug 13 06:18:05 PM PDT 24
Finished	Aug 13 06:31:31 PM PDT 24
Peak memory	261504 kb
Host	smart-f3282650-53e8-4f5d-9b4d-768ea04ffd51
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135775962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 10.flash_ctrl_hw_rma_reset.4135775962
Directory	/workspace/10.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/10.flash_ctrl_hw_sec_otp.2215825570
Short name	T685
Test name
Test status
Simulation time	8880092800 ps
CPU time	124.35 seconds
Started	Aug 13 06:18:05 PM PDT 24
Finished	Aug 13 06:20:09 PM PDT 24
Peak memory	261008 kb
Host	smart-952243e4-7341-484f-9dbd-f7269a1f5de8
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215825570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_ hw_sec_otp.2215825570
Directory	/workspace/10.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/10.flash_ctrl_intr_rd.1717771542
Short name	T6
Test name
Test status
Simulation time	1530990300 ps
CPU time	154.58 seconds
Started	Aug 13 06:18:14 PM PDT 24
Finished	Aug 13 06:20:48 PM PDT 24
Peak memory	294744 kb
Host	smart-dc222d7c-4ab7-48cd-83bd-061c364d7320
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717771542 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla sh_ctrl_intr_rd.1717771542
Directory	/workspace/10.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/10.flash_ctrl_intr_rd_slow_flash.4137027345
Short name	T1086
Test name
Test status
Simulation time	40831434200 ps
CPU time	267.82 seconds
Started	Aug 13 06:18:14 PM PDT 24
Finished	Aug 13 06:22:42 PM PDT 24
Peak memory	291588 kb
Host	smart-0a1ba7c5-ee2f-4b04-831c-b652c9a68197
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137027345 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd_slow_flash.4137027345
Directory	/workspace/10.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/10.flash_ctrl_lcmgr_intg.3552770492
Short name	T1003
Test name
Test status
Simulation time	15808100 ps
CPU time	13.47 seconds
Started	Aug 13 06:18:12 PM PDT 24
Finished	Aug 13 06:18:25 PM PDT 24
Peak memory	260764 kb
Host	smart-52d174bf-fcaa-4cb3-8231-c514fafe5af8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552770492 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 10.flash_ctrl_lcmgr_intg.3552770492
Directory	/workspace/10.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/10.flash_ctrl_otp_reset.74377742
Short name	T978
Test name
Test status
Simulation time	38282400 ps
CPU time	133.48 seconds
Started	Aug 13 06:18:05 PM PDT 24
Finished	Aug 13 06:20:19 PM PDT 24
Peak memory	264936 kb
Host	smart-e0fd14d9-8999-4af4-8f19-c01091f95bb1
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74377742 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl _otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_otp _reset.74377742
Directory	/workspace/10.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/10.flash_ctrl_phy_arb.3673981373
Short name	T810
Test name
Test status
Simulation time	105439000 ps
CPU time	231.25 seconds
Started	Aug 13 06:18:06 PM PDT 24
Finished	Aug 13 06:21:58 PM PDT 24
Peak memory	263652 kb
Host	smart-33e52499-6584-47eb-a9f3-b1c4eb7af539
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3673981373 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.3673981373
Directory	/workspace/10.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/10.flash_ctrl_prog_reset.1799125128
Short name	T856
Test name
Test status
Simulation time	7379528400 ps
CPU time	160.42 seconds
Started	Aug 13 06:18:12 PM PDT 24
Finished	Aug 13 06:20:53 PM PDT 24
Peak memory	265836 kb
Host	smart-08455749-e1cf-4f6a-bc85-28b78f40e360
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799125128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 10.flash_ctrl_prog_reset.1799125128
Directory	/workspace/10.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/10.flash_ctrl_rand_ops.1222190169
Short name	T783
Test name
Test status
Simulation time	138706200 ps
CPU time	147.98 seconds
Started	Aug 13 06:18:06 PM PDT 24
Finished	Aug 13 06:20:34 PM PDT 24
Peak memory	277948 kb
Host	smart-4daa02e9-c04e-4610-b9fe-b57012c10a8f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1222190169 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.1222190169
Directory	/workspace/10.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/10.flash_ctrl_re_evict.1429371068
Short name	T398
Test name
Test status
Simulation time	68097700 ps
CPU time	34.69 seconds
Started	Aug 13 06:18:13 PM PDT 24
Finished	Aug 13 06:18:48 PM PDT 24
Peak memory	276564 kb
Host	smart-a0ad8370-121a-4c9f-a7cc-3b502e554852
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429371068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl ash_ctrl_re_evict.1429371068
Directory	/workspace/10.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/10.flash_ctrl_ro.1108231658
Short name	T1064
Test name
Test status
Simulation time	1044274300 ps
CPU time	108.79 seconds
Started	Aug 13 06:18:11 PM PDT 24
Finished	Aug 13 06:20:00 PM PDT 24
Peak memory	282384 kb
Host	smart-848a3a31-efd0-4722-be2f-dd57cd99587c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108231658 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 10.flash_ctrl_ro.1108231658
Directory	/workspace/10.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/10.flash_ctrl_rw.2505518453
Short name	T826
Test name
Test status
Simulation time	4111304500 ps
CPU time	552.18 seconds
Started	Aug 13 06:18:14 PM PDT 24
Finished	Aug 13 06:27:26 PM PDT 24
Peak memory	310220 kb
Host	smart-7e3b6a81-5c65-419c-b9e4-bc905aad56ef
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505518453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 10.flash_ctrl_rw.2505518453
Directory	/workspace/10.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/10.flash_ctrl_rw_evict.1155654747
Short name	T362
Test name
Test status
Simulation time	28173800 ps
CPU time	28.47 seconds
Started	Aug 13 06:18:13 PM PDT 24
Finished	Aug 13 06:18:41 PM PDT 24
Peak memory	274072 kb
Host	smart-46316707-cbb6-4ad4-ae2f-b03f671bbce7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155654747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.fl ash_ctrl_rw_evict.1155654747
Directory	/workspace/10.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/10.flash_ctrl_rw_evict_all_en.102076330
Short name	T862
Test name
Test status
Simulation time	28445200 ps
CPU time	31.46 seconds
Started	Aug 13 06:18:13 PM PDT 24
Finished	Aug 13 06:18:45 PM PDT 24
Peak memory	275568 kb
Host	smart-2d749a83-f820-4651-9056-88ced3c60b9a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102076330 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict_all_en.102076330
Directory	/workspace/10.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/10.flash_ctrl_smoke.1309370965
Short name	T492
Test name
Test status
Simulation time	38331100 ps
CPU time	143.87 seconds
Started	Aug 13 06:18:06 PM PDT 24
Finished	Aug 13 06:20:30 PM PDT 24
Peak memory	277480 kb
Host	smart-76202704-f951-4277-9a82-a47813b88ec9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1309370965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.1309370965
Directory	/workspace/10.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/10.flash_ctrl_wo.1321351280
Short name	T548
Test name
Test status
Simulation time	7604861300 ps
CPU time	173.23 seconds
Started	Aug 13 06:18:13 PM PDT 24
Finished	Aug 13 06:21:06 PM PDT 24
Peak memory	265820 kb
Host	smart-86fd08d3-c894-430c-8f08-7dbeb9df335d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321351280 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 10.flash_ctrl_wo.1321351280
Directory	/workspace/10.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/11.flash_ctrl_alert_test.4016806516
Short name	T1076
Test name
Test status
Simulation time	164471600 ps
CPU time	14.27 seconds
Started	Aug 13 06:18:29 PM PDT 24
Finished	Aug 13 06:18:43 PM PDT 24
Peak memory	258844 kb
Host	smart-124f9bf7-ccc4-47a6-89d7-711dd1c329d1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016806516 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test. 4016806516
Directory	/workspace/11.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/11.flash_ctrl_connect.2801566654
Short name	T864
Test name
Test status
Simulation time	21965900 ps
CPU time	16.11 seconds
Started	Aug 13 06:18:28 PM PDT 24
Finished	Aug 13 06:18:44 PM PDT 24
Peak memory	283440 kb
Host	smart-5784b83e-f4b0-4911-8af9-75485ef7d065
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2801566654 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.2801566654
Directory	/workspace/11.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/11.flash_ctrl_disable.840457696
Short name	T380
Test name
Test status
Simulation time	22081200 ps
CPU time	22.21 seconds
Started	Aug 13 06:18:31 PM PDT 24
Finished	Aug 13 06:18:53 PM PDT 24
Peak memory	274060 kb
Host	smart-082f1b2d-e242-408d-876d-3a845990115f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840457696 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_disable.840457696
Directory	/workspace/11.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.156569842
Short name	T287
Test name
Test status
Simulation time	10012229600 ps
CPU time	322.56 seconds
Started	Aug 13 06:18:28 PM PDT 24
Finished	Aug 13 06:23:51 PM PDT 24
Peak memory	331156 kb
Host	smart-a3c88269-fd7d-4354-b1ac-bbfdf776f81c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156569842 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.156569842
Directory	/workspace/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/11.flash_ctrl_hw_rma_reset.4222568882
Short name	T193
Test name
Test status
Simulation time	630452683800 ps
CPU time	1011.45 seconds
Started	Aug 13 06:18:22 PM PDT 24
Finished	Aug 13 06:35:14 PM PDT 24
Peak memory	261592 kb
Host	smart-9ce7f28f-dc14-4036-9f6f-f83885fe9193
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222568882 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 11.flash_ctrl_hw_rma_reset.4222568882
Directory	/workspace/11.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/11.flash_ctrl_hw_sec_otp.3751271922
Short name	T625
Test name
Test status
Simulation time	2069483900 ps
CPU time	49.24 seconds
Started	Aug 13 06:18:23 PM PDT 24
Finished	Aug 13 06:19:13 PM PDT 24
Peak memory	263304 kb
Host	smart-fe91c15f-e72e-4f1a-9b48-e64d45cacd84
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751271922 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_ hw_sec_otp.3751271922
Directory	/workspace/11.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/11.flash_ctrl_intr_rd.2184026352
Short name	T485
Test name
Test status
Simulation time	16746867000 ps
CPU time	226.92 seconds
Started	Aug 13 06:18:20 PM PDT 24
Finished	Aug 13 06:22:07 PM PDT 24
Peak memory	291520 kb
Host	smart-0ba96b7a-a99b-427d-a803-4bbb9b1b764c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184026352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla sh_ctrl_intr_rd.2184026352
Directory	/workspace/11.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/11.flash_ctrl_intr_rd_slow_flash.2804475621
Short name	T513
Test name
Test status
Simulation time	15804576800 ps
CPU time	208.87 seconds
Started	Aug 13 06:18:21 PM PDT 24
Finished	Aug 13 06:21:50 PM PDT 24
Peak memory	291584 kb
Host	smart-1b099ed3-8a75-4b82-8fa4-c837a01f98a1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804475621 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd_slow_flash.2804475621
Directory	/workspace/11.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/11.flash_ctrl_invalid_op.694721475
Short name	T516
Test name
Test status
Simulation time	11586235800 ps
CPU time	78.32 seconds
Started	Aug 13 06:18:23 PM PDT 24
Finished	Aug 13 06:19:41 PM PDT 24
Peak memory	261260 kb
Host	smart-efe75a53-24d3-42f4-8013-2f379e7f3a61
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694721475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.694721475
Directory	/workspace/11.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/11.flash_ctrl_lcmgr_intg.1102251084
Short name	T1104
Test name
Test status
Simulation time	15996200 ps
CPU time	13.75 seconds
Started	Aug 13 06:18:31 PM PDT 24
Finished	Aug 13 06:18:44 PM PDT 24
Peak memory	265760 kb
Host	smart-2cf15270-5b44-4ed7-ac22-709ff01cddfd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102251084 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 11.flash_ctrl_lcmgr_intg.1102251084
Directory	/workspace/11.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/11.flash_ctrl_otp_reset.3482926074
Short name	T857
Test name
Test status
Simulation time	258239900 ps
CPU time	131.69 seconds
Started	Aug 13 06:18:23 PM PDT 24
Finished	Aug 13 06:20:35 PM PDT 24
Peak memory	260660 kb
Host	smart-14a40043-5d98-43e9-ad69-46dda8554dfc
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482926074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_o tp_reset.3482926074
Directory	/workspace/11.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/11.flash_ctrl_phy_arb.360183185
Short name	T863
Test name
Test status
Simulation time	2777592700 ps
CPU time	404.75 seconds
Started	Aug 13 06:18:21 PM PDT 24
Finished	Aug 13 06:25:06 PM PDT 24
Peak memory	263724 kb
Host	smart-1c35ef6d-c3fc-422f-a575-a9826027114a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=360183185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.360183185
Directory	/workspace/11.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/11.flash_ctrl_prog_reset.3587807637
Short name	T482
Test name
Test status
Simulation time	42202300 ps
CPU time	13.7 seconds
Started	Aug 13 06:18:30 PM PDT 24
Finished	Aug 13 06:18:44 PM PDT 24
Peak memory	265612 kb
Host	smart-3b348633-e3d7-4e0d-b49b-88df12c8bd05
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587807637 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 11.flash_ctrl_prog_reset.3587807637
Directory	/workspace/11.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/11.flash_ctrl_rand_ops.3044916966
Short name	T132
Test name
Test status
Simulation time	193527700 ps
CPU time	1112.09 seconds
Started	Aug 13 06:18:21 PM PDT 24
Finished	Aug 13 06:36:54 PM PDT 24
Peak memory	287708 kb
Host	smart-afa48f6b-fa99-44cf-878d-9ffc613118dd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3044916966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.3044916966
Directory	/workspace/11.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/11.flash_ctrl_ro.2201969627
Short name	T909
Test name
Test status
Simulation time	587894100 ps
CPU time	126.18 seconds
Started	Aug 13 06:18:21 PM PDT 24
Finished	Aug 13 06:20:27 PM PDT 24
Peak memory	290600 kb
Host	smart-efcfaea7-18b5-48cc-a36e-70c294cfc3b5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201969627 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 11.flash_ctrl_ro.2201969627
Directory	/workspace/11.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/11.flash_ctrl_rw.4139013185
Short name	T872
Test name
Test status
Simulation time	10863709300 ps
CPU time	505.72 seconds
Started	Aug 13 06:18:22 PM PDT 24
Finished	Aug 13 06:26:48 PM PDT 24
Peak memory	318380 kb
Host	smart-55c92da4-ebdb-42db-84a2-a5c81777d2fd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139013185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 11.flash_ctrl_rw.4139013185
Directory	/workspace/11.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/11.flash_ctrl_rw_evict.3581043997
Short name	T414
Test name
Test status
Simulation time	91390500 ps
CPU time	31.44 seconds
Started	Aug 13 06:18:30 PM PDT 24
Finished	Aug 13 06:19:01 PM PDT 24
Peak memory	274228 kb
Host	smart-c6e542ea-42ff-416f-a2a8-d11a707a3970
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581043997 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.fl ash_ctrl_rw_evict.3581043997
Directory	/workspace/11.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/11.flash_ctrl_sec_info_access.3993716117
Short name	T717
Test name
Test status
Simulation time	10179147500 ps
CPU time	77.26 seconds
Started	Aug 13 06:18:28 PM PDT 24
Finished	Aug 13 06:19:45 PM PDT 24
Peak memory	262516 kb
Host	smart-fefac76f-6273-4973-977b-0a9cc1eb6cb9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3993716117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.3993716117
Directory	/workspace/11.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/11.flash_ctrl_smoke.683585329
Short name	T1042
Test name
Test status
Simulation time	75151500 ps
CPU time	98.11 seconds
Started	Aug 13 06:18:14 PM PDT 24
Finished	Aug 13 06:19:52 PM PDT 24
Peak memory	276540 kb
Host	smart-725914f5-0ef5-4eff-81c4-acef743af14b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=683585329 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.683585329
Directory	/workspace/11.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/11.flash_ctrl_wo.15611390
Short name	T594
Test name
Test status
Simulation time	5440347200 ps
CPU time	220.43 seconds
Started	Aug 13 06:18:21 PM PDT 24
Finished	Aug 13 06:22:02 PM PDT 24
Peak memory	265868 kb
Host	smart-459820e5-dd16-4e27-993e-07c5476b8470
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15611390 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 11.flash_ctrl_wo.15611390
Directory	/workspace/11.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/12.flash_ctrl_alert_test.3034246118
Short name	T517
Test name
Test status
Simulation time	44938400 ps
CPU time	13.8 seconds
Started	Aug 13 06:18:48 PM PDT 24
Finished	Aug 13 06:19:01 PM PDT 24
Peak memory	265788 kb
Host	smart-26a35c3b-ee7e-4616-8886-667d8f326b51
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034246118 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test. 3034246118
Directory	/workspace/12.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/12.flash_ctrl_connect.4220054721
Short name	T987
Test name
Test status
Simulation time	22326500 ps
CPU time	15.97 seconds
Started	Aug 13 06:18:46 PM PDT 24
Finished	Aug 13 06:19:02 PM PDT 24
Peak memory	275492 kb
Host	smart-cb0928ff-6cfd-4904-b8f2-b3f6e3d9a500
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4220054721 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.4220054721
Directory	/workspace/12.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.3056232678
Short name	T749
Test name
Test status
Simulation time	10012353200 ps
CPU time	115.17 seconds
Started	Aug 13 06:18:46 PM PDT 24
Finished	Aug 13 06:20:42 PM PDT 24
Peak memory	340708 kb
Host	smart-59054619-c1e8-41d7-b775-405e2c84e562
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056232678 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.3056232678
Directory	/workspace/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/12.flash_ctrl_hw_read_seed_err.4239641699
Short name	T329
Test name
Test status
Simulation time	15294300 ps
CPU time	13.48 seconds
Started	Aug 13 06:18:47 PM PDT 24
Finished	Aug 13 06:19:01 PM PDT 24
Peak memory	260640 kb
Host	smart-578b1083-e239-419e-b3e5-7fb577a74bb8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239641699 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_read_seed_err.4239641699
Directory	/workspace/12.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/12.flash_ctrl_hw_rma_reset.139331968
Short name	T691
Test name
Test status
Simulation time	80142837000 ps
CPU time	792.29 seconds
Started	Aug 13 06:18:39 PM PDT 24
Finished	Aug 13 06:31:51 PM PDT 24
Peak memory	265548 kb
Host	smart-9b7985dd-2f2b-452f-b7dd-5a05cce6e906
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139331968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 12.flash_ctrl_hw_rma_reset.139331968
Directory	/workspace/12.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/12.flash_ctrl_hw_sec_otp.27578418
Short name	T501
Test name
Test status
Simulation time	11853252300 ps
CPU time	222.73 seconds
Started	Aug 13 06:18:38 PM PDT 24
Finished	Aug 13 06:22:21 PM PDT 24
Peak memory	261344 kb
Host	smart-856f7ad6-c477-45fe-bfa2-605b9f1f6a43
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27578418 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl _hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw _sec_otp.27578418
Directory	/workspace/12.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/12.flash_ctrl_intr_rd.1289339843
Short name	T746
Test name
Test status
Simulation time	639493200 ps
CPU time	123.49 seconds
Started	Aug 13 06:18:40 PM PDT 24
Finished	Aug 13 06:20:44 PM PDT 24
Peak memory	295744 kb
Host	smart-033460ba-1f4b-47a9-b204-3e2c1569f221
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289339843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla sh_ctrl_intr_rd.1289339843
Directory	/workspace/12.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/12.flash_ctrl_intr_rd_slow_flash.63915395
Short name	T815
Test name
Test status
Simulation time	11601459800 ps
CPU time	128.62 seconds
Started	Aug 13 06:18:39 PM PDT 24
Finished	Aug 13 06:20:47 PM PDT 24
Peak memory	293432 kb
Host	smart-b19b9254-680a-480b-962e-ad448a473df7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63915395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd_slow_flash.63915395
Directory	/workspace/12.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/12.flash_ctrl_invalid_op.1691343173
Short name	T116
Test name
Test status
Simulation time	8339580500 ps
CPU time	70.71 seconds
Started	Aug 13 06:18:41 PM PDT 24
Finished	Aug 13 06:19:51 PM PDT 24
Peak memory	263432 kb
Host	smart-57efabe9-8c57-4817-a968-193df61b662b
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691343173 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.1 691343173
Directory	/workspace/12.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/12.flash_ctrl_lcmgr_intg.574118815
Short name	T565
Test name
Test status
Simulation time	16364700 ps
CPU time	13.49 seconds
Started	Aug 13 06:18:42 PM PDT 24
Finished	Aug 13 06:18:56 PM PDT 24
Peak memory	265312 kb
Host	smart-1a9c88b5-dbaf-45ec-9d10-81e8718fd3cf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574118815 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 12.flash_ctrl_lcmgr_intg.574118815
Directory	/workspace/12.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/12.flash_ctrl_mp_regions.3377911683
Short name	T768
Test name
Test status
Simulation time	73678286200 ps
CPU time	566.91 seconds
Started	Aug 13 06:18:38 PM PDT 24
Finished	Aug 13 06:28:05 PM PDT 24
Peak memory	275560 kb
Host	smart-2a9ef69c-514b-4e73-8a0f-58e7f0809f4a
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377911683 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_mp_regions.3377911683
Directory	/workspace/12.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/12.flash_ctrl_phy_arb.1558081407
Short name	T891
Test name
Test status
Simulation time	756460100 ps
CPU time	408.46 seconds
Started	Aug 13 06:18:30 PM PDT 24
Finished	Aug 13 06:25:18 PM PDT 24
Peak memory	263748 kb
Host	smart-ffb8b3bf-c426-433f-8157-8fadabc0fcf0
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1558081407 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.1558081407
Directory	/workspace/12.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/12.flash_ctrl_prog_reset.1006320197
Short name	T732
Test name
Test status
Simulation time	2454792800 ps
CPU time	176.28 seconds
Started	Aug 13 06:18:39 PM PDT 24
Finished	Aug 13 06:21:36 PM PDT 24
Peak memory	260584 kb
Host	smart-90b0414e-5643-40db-a8e9-c8a394e8a7d0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006320197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 12.flash_ctrl_prog_reset.1006320197
Directory	/workspace/12.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/12.flash_ctrl_rand_ops.3676355619
Short name	T131
Test name
Test status
Simulation time	322089100 ps
CPU time	835.34 seconds
Started	Aug 13 06:18:30 PM PDT 24
Finished	Aug 13 06:32:26 PM PDT 24
Peak memory	284060 kb
Host	smart-6f9e1fc8-388d-418e-94ff-2fbb9b73908e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3676355619 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.3676355619
Directory	/workspace/12.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/12.flash_ctrl_re_evict.4108090009
Short name	T566
Test name
Test status
Simulation time	131111200 ps
CPU time	34.92 seconds
Started	Aug 13 06:18:38 PM PDT 24
Finished	Aug 13 06:19:14 PM PDT 24
Peak memory	276432 kb
Host	smart-cc183f80-5801-46c2-9a08-91f3a7ebb49d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108090009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl ash_ctrl_re_evict.4108090009
Directory	/workspace/12.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/12.flash_ctrl_rw.2067642754
Short name	T687
Test name
Test status
Simulation time	8064117300 ps
CPU time	581.86 seconds
Started	Aug 13 06:18:38 PM PDT 24
Finished	Aug 13 06:28:20 PM PDT 24
Peak memory	314972 kb
Host	smart-b539acf1-f07a-4fb3-be9e-f9ff12afcd16
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067642754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 12.flash_ctrl_rw.2067642754
Directory	/workspace/12.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/12.flash_ctrl_rw_evict.3205427023
Short name	T415
Test name
Test status
Simulation time	44358000 ps
CPU time	31.13 seconds
Started	Aug 13 06:18:37 PM PDT 24
Finished	Aug 13 06:19:08 PM PDT 24
Peak memory	272996 kb
Host	smart-9434065c-ec1e-48f3-9524-98e51e21c1b4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205427023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.fl ash_ctrl_rw_evict.3205427023
Directory	/workspace/12.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/12.flash_ctrl_sec_info_access.4092675616
Short name	T200
Test name
Test status
Simulation time	709839900 ps
CPU time	55.46 seconds
Started	Aug 13 06:18:45 PM PDT 24
Finished	Aug 13 06:19:40 PM PDT 24
Peak memory	263672 kb
Host	smart-2c497a3c-a7cc-414c-97df-38297ace45e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4092675616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.4092675616
Directory	/workspace/12.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/12.flash_ctrl_smoke.66151691
Short name	T1015
Test name
Test status
Simulation time	18544000 ps
CPU time	123.34 seconds
Started	Aug 13 06:18:29 PM PDT 24
Finished	Aug 13 06:20:33 PM PDT 24
Peak memory	277908 kb
Host	smart-005d0de1-7778-4e04-b12d-96f462aa24eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=66151691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.66151691
Directory	/workspace/12.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/12.flash_ctrl_wo.451320302
Short name	T1115
Test name
Test status
Simulation time	11167069200 ps
CPU time	200.74 seconds
Started	Aug 13 06:18:40 PM PDT 24
Finished	Aug 13 06:22:01 PM PDT 24
Peak memory	260640 kb
Host	smart-42774dde-18ac-473a-b42f-743149ed4d4e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451320302 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 12.flash_ctrl_wo.451320302
Directory	/workspace/12.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/13.flash_ctrl_alert_test.2039547912
Short name	T777
Test name
Test status
Simulation time	57841700 ps
CPU time	13.51 seconds
Started	Aug 13 06:18:53 PM PDT 24
Finished	Aug 13 06:19:07 PM PDT 24
Peak memory	258748 kb
Host	smart-c3a00d48-2dc0-417e-aaa1-d7498ac54c20
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039547912 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test. 2039547912
Directory	/workspace/13.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/13.flash_ctrl_connect.365383864
Short name	T1039
Test name
Test status
Simulation time	16313200 ps
CPU time	15.93 seconds
Started	Aug 13 06:19:03 PM PDT 24
Finished	Aug 13 06:19:19 PM PDT 24
Peak memory	284860 kb
Host	smart-5d2a14b4-6fda-4e5d-9643-de604007bf5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=365383864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.365383864
Directory	/workspace/13.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/13.flash_ctrl_disable.713340270
Short name	T1017
Test name
Test status
Simulation time	34440200 ps
CPU time	21.96 seconds
Started	Aug 13 06:19:03 PM PDT 24
Finished	Aug 13 06:19:25 PM PDT 24
Peak memory	274188 kb
Host	smart-5d7712ca-1197-48e3-8687-42bfd07181eb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713340270 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_disable.713340270
Directory	/workspace/13.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.262123439
Short name	T745
Test name
Test status
Simulation time	10020860900 ps
CPU time	77.41 seconds
Started	Aug 13 06:19:02 PM PDT 24
Finished	Aug 13 06:20:20 PM PDT 24
Peak memory	293816 kb
Host	smart-b7f385c4-25d4-4827-ae2f-6bdf082d4a41
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262123439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.262123439
Directory	/workspace/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/13.flash_ctrl_hw_read_seed_err.1449253148
Short name	T218
Test name
Test status
Simulation time	45876400 ps
CPU time	13.61 seconds
Started	Aug 13 06:19:01 PM PDT 24
Finished	Aug 13 06:19:14 PM PDT 24
Peak memory	260628 kb
Host	smart-78e3cadc-2030-4e96-8d0b-79827808872c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449253148 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_read_seed_err.1449253148
Directory	/workspace/13.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/13.flash_ctrl_hw_rma_reset.2866452132
Short name	T1091
Test name
Test status
Simulation time	180176064300 ps
CPU time	978.26 seconds
Started	Aug 13 06:18:45 PM PDT 24
Finished	Aug 13 06:35:04 PM PDT 24
Peak memory	264520 kb
Host	smart-1572f2e3-a893-46ac-b62e-55d720af51b4
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866452132 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 13.flash_ctrl_hw_rma_reset.2866452132
Directory	/workspace/13.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/13.flash_ctrl_hw_sec_otp.1916888780
Short name	T933
Test name
Test status
Simulation time	2517414500 ps
CPU time	175.41 seconds
Started	Aug 13 06:18:43 PM PDT 24
Finished	Aug 13 06:21:39 PM PDT 24
Peak memory	261508 kb
Host	smart-149c5c16-3ee3-4538-a4f9-5a07c27da74a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916888780 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_ hw_sec_otp.1916888780
Directory	/workspace/13.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/13.flash_ctrl_intr_rd.4139684526
Short name	T136
Test name
Test status
Simulation time	1813448600 ps
CPU time	181.88 seconds
Started	Aug 13 06:18:55 PM PDT 24
Finished	Aug 13 06:21:57 PM PDT 24
Peak memory	285580 kb
Host	smart-44c7f2e3-b143-45c6-8812-3ce577135a18
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139684526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla sh_ctrl_intr_rd.4139684526
Directory	/workspace/13.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/13.flash_ctrl_intr_rd_slow_flash.568380731
Short name	T741
Test name
Test status
Simulation time	6088771000 ps
CPU time	136.36 seconds
Started	Aug 13 06:18:56 PM PDT 24
Finished	Aug 13 06:21:12 PM PDT 24
Peak memory	293456 kb
Host	smart-ad1d1c3a-d846-4c65-918b-1871ff726b6e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568380731 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd_slow_flash.568380731
Directory	/workspace/13.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/13.flash_ctrl_invalid_op.1166833962
Short name	T896
Test name
Test status
Simulation time	2431206300 ps
CPU time	93.18 seconds
Started	Aug 13 06:18:52 PM PDT 24
Finished	Aug 13 06:20:25 PM PDT 24
Peak memory	263920 kb
Host	smart-c27f0805-7247-42dc-bf84-6d42b7ed0019
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166833962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.1 166833962
Directory	/workspace/13.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/13.flash_ctrl_lcmgr_intg.2768830655
Short name	T970
Test name
Test status
Simulation time	15858400 ps
CPU time	13.81 seconds
Started	Aug 13 06:19:05 PM PDT 24
Finished	Aug 13 06:19:18 PM PDT 24
Peak memory	265392 kb
Host	smart-84322b61-278a-4c82-9145-73e9916f8128
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768830655 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 13.flash_ctrl_lcmgr_intg.2768830655
Directory	/workspace/13.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/13.flash_ctrl_mp_regions.246533246
Short name	T733
Test name
Test status
Simulation time	3909468900 ps
CPU time	140.2 seconds
Started	Aug 13 06:18:45 PM PDT 24
Finished	Aug 13 06:21:05 PM PDT 24
Peak memory	265772 kb
Host	smart-53c0cbb6-32e4-47f0-9df5-3a8e0a5e0c27
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246533246 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_mp_regions.246533246
Directory	/workspace/13.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/13.flash_ctrl_otp_reset.2011832301
Short name	T607
Test name
Test status
Simulation time	168674700 ps
CPU time	109.2 seconds
Started	Aug 13 06:18:45 PM PDT 24
Finished	Aug 13 06:20:35 PM PDT 24
Peak memory	260628 kb
Host	smart-0fe29e77-4a2b-43c9-895e-b52a23db6c19
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011832301 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_o tp_reset.2011832301
Directory	/workspace/13.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/13.flash_ctrl_phy_arb.3566372876
Short name	T232
Test name
Test status
Simulation time	2873492700 ps
CPU time	415.09 seconds
Started	Aug 13 06:18:46 PM PDT 24
Finished	Aug 13 06:25:41 PM PDT 24
Peak memory	263732 kb
Host	smart-76d13c58-ed03-4682-ab68-c82851606c10
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3566372876 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.3566372876
Directory	/workspace/13.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/13.flash_ctrl_prog_reset.1143957750
Short name	T454
Test name
Test status
Simulation time	59666700 ps
CPU time	13.84 seconds
Started	Aug 13 06:18:54 PM PDT 24
Finished	Aug 13 06:19:08 PM PDT 24
Peak memory	259524 kb
Host	smart-afb39a5c-f294-49e6-8adc-ebe77d0e6d33
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143957750 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 13.flash_ctrl_prog_reset.1143957750
Directory	/workspace/13.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/13.flash_ctrl_rand_ops.2089617064
Short name	T851
Test name
Test status
Simulation time	8818921100 ps
CPU time	1282.41 seconds
Started	Aug 13 06:18:47 PM PDT 24
Finished	Aug 13 06:40:09 PM PDT 24
Peak memory	287736 kb
Host	smart-d0b5e305-ddf9-41a5-98bf-eb922e1f379e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2089617064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.2089617064
Directory	/workspace/13.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/13.flash_ctrl_re_evict.4096989998
Short name	T650
Test name
Test status
Simulation time	256843200 ps
CPU time	35.47 seconds
Started	Aug 13 06:18:54 PM PDT 24
Finished	Aug 13 06:19:30 PM PDT 24
Peak memory	276488 kb
Host	smart-51c7fcef-1fb4-42f1-9de3-6463b5c65ae1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096989998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.fl ash_ctrl_re_evict.4096989998
Directory	/workspace/13.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/13.flash_ctrl_ro.2272983535
Short name	T784
Test name
Test status
Simulation time	2258147200 ps
CPU time	115.66 seconds
Started	Aug 13 06:19:03 PM PDT 24
Finished	Aug 13 06:20:58 PM PDT 24
Peak memory	289852 kb
Host	smart-6b0495b7-c3f1-4c4d-abfd-4e133fef44e2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272983535 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 13.flash_ctrl_ro.2272983535
Directory	/workspace/13.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/13.flash_ctrl_rw.2864937093
Short name	T220
Test name
Test status
Simulation time	7043599500 ps
CPU time	590.83 seconds
Started	Aug 13 06:18:55 PM PDT 24
Finished	Aug 13 06:28:46 PM PDT 24
Peak memory	315132 kb
Host	smart-e64fecd5-18ab-4522-826a-58d3ab72d536
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864937093 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 13.flash_ctrl_rw.2864937093
Directory	/workspace/13.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/13.flash_ctrl_rw_evict_all_en.203006126
Short name	T413
Test name
Test status
Simulation time	42698700 ps
CPU time	30.72 seconds
Started	Aug 13 06:18:53 PM PDT 24
Finished	Aug 13 06:19:24 PM PDT 24
Peak memory	268300 kb
Host	smart-84c1b1c5-a2d7-4354-bbf4-ecf39931dc8a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203006126 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict_all_en.203006126
Directory	/workspace/13.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/13.flash_ctrl_sec_info_access.255999240
Short name	T773
Test name
Test status
Simulation time	5476404200 ps
CPU time	63.55 seconds
Started	Aug 13 06:18:54 PM PDT 24
Finished	Aug 13 06:19:58 PM PDT 24
Peak memory	263584 kb
Host	smart-678edbd2-4afc-47c9-a6d3-347a2c2056bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=255999240 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.255999240
Directory	/workspace/13.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/13.flash_ctrl_smoke.4255233945
Short name	T990
Test name
Test status
Simulation time	18708700 ps
CPU time	51.65 seconds
Started	Aug 13 06:18:45 PM PDT 24
Finished	Aug 13 06:19:37 PM PDT 24
Peak memory	271652 kb
Host	smart-b3136ef4-91e5-4adf-888f-143a49213c06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4255233945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.4255233945
Directory	/workspace/13.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/13.flash_ctrl_wo.1386546026
Short name	T1111
Test name
Test status
Simulation time	9929258700 ps
CPU time	177.08 seconds
Started	Aug 13 06:18:54 PM PDT 24
Finished	Aug 13 06:21:51 PM PDT 24
Peak memory	260556 kb
Host	smart-47afee4c-4ab7-4070-9e35-21369c69e431
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386546026 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 13.flash_ctrl_wo.1386546026
Directory	/workspace/13.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/14.flash_ctrl_connect.2756024961
Short name	T1050
Test name
Test status
Simulation time	16315500 ps
CPU time	13.34 seconds
Started	Aug 13 06:19:11 PM PDT 24
Finished	Aug 13 06:19:25 PM PDT 24
Peak memory	284784 kb
Host	smart-558828b6-1f5a-459d-9b84-917fd6ed93d6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2756024961 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.2756024961
Directory	/workspace/14.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/14.flash_ctrl_disable.1309387686
Short name	T649
Test name
Test status
Simulation time	15332900 ps
CPU time	20.5 seconds
Started	Aug 13 06:19:10 PM PDT 24
Finished	Aug 13 06:19:30 PM PDT 24
Peak memory	274120 kb
Host	smart-8f4da3c9-55dd-45fa-9caf-515ad723ef95
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309387686 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_disable.1309387686
Directory	/workspace/14.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.1947615364
Short name	T285
Test name
Test status
Simulation time	10029824900 ps
CPU time	60.05 seconds
Started	Aug 13 06:19:11 PM PDT 24
Finished	Aug 13 06:20:11 PM PDT 24
Peak memory	293832 kb
Host	smart-9debcdd4-54ae-4a3c-a09c-9466816bfba0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947615364 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.1947615364
Directory	/workspace/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/14.flash_ctrl_hw_read_seed_err.4181903250
Short name	T915
Test name
Test status
Simulation time	22134600 ps
CPU time	13.52 seconds
Started	Aug 13 06:19:12 PM PDT 24
Finished	Aug 13 06:19:26 PM PDT 24
Peak memory	260684 kb
Host	smart-c1233290-ee1b-4bc1-929a-bf39ed59168f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181903250 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_read_seed_err.4181903250
Directory	/workspace/14.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/14.flash_ctrl_hw_rma_reset.2917017454
Short name	T107
Test name
Test status
Simulation time	160204720100 ps
CPU time	893.51 seconds
Started	Aug 13 06:19:02 PM PDT 24
Finished	Aug 13 06:33:55 PM PDT 24
Peak memory	261360 kb
Host	smart-cb5b9aa8-cf58-4f60-b788-725cd3590572
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917017454 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 14.flash_ctrl_hw_rma_reset.2917017454
Directory	/workspace/14.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/14.flash_ctrl_hw_sec_otp.2421841600
Short name	T878
Test name
Test status
Simulation time	5992256200 ps
CPU time	265.78 seconds
Started	Aug 13 06:19:04 PM PDT 24
Finished	Aug 13 06:23:29 PM PDT 24
Peak memory	263720 kb
Host	smart-a31e77b8-4478-4ec2-aa66-91d0ad3d5922
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421841600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_ hw_sec_otp.2421841600
Directory	/workspace/14.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/14.flash_ctrl_intr_rd.73851776
Short name	T540
Test name
Test status
Simulation time	14097313300 ps
CPU time	223.55 seconds
Started	Aug 13 06:19:03 PM PDT 24
Finished	Aug 13 06:22:47 PM PDT 24
Peak memory	285540 kb
Host	smart-123ae4f7-35b9-473a-8a7f-70a734eca713
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73851776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ =flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash _ctrl_intr_rd.73851776
Directory	/workspace/14.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.4158685528
Short name	T669
Test name
Test status
Simulation time	51541417800 ps
CPU time	287.66 seconds
Started	Aug 13 06:19:05 PM PDT 24
Finished	Aug 13 06:23:53 PM PDT 24
Peak memory	285804 kb
Host	smart-a2509415-9aed-401d-841e-585302ef0dcb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158685528 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd_slow_flash.4158685528
Directory	/workspace/14.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/14.flash_ctrl_invalid_op.3219165611
Short name	T865
Test name
Test status
Simulation time	3967694400 ps
CPU time	56.56 seconds
Started	Aug 13 06:19:04 PM PDT 24
Finished	Aug 13 06:20:01 PM PDT 24
Peak memory	263968 kb
Host	smart-f52039e0-3e83-400c-993f-ef53b10d9f6d
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219165611 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.3 219165611
Directory	/workspace/14.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/14.flash_ctrl_lcmgr_intg.2887054115
Short name	T289
Test name
Test status
Simulation time	15669800 ps
CPU time	13.33 seconds
Started	Aug 13 06:19:09 PM PDT 24
Finished	Aug 13 06:19:22 PM PDT 24
Peak memory	265332 kb
Host	smart-be6a1b56-20a5-4fa9-9a5c-c5803c6454a5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887054115 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 14.flash_ctrl_lcmgr_intg.2887054115
Directory	/workspace/14.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/14.flash_ctrl_mp_regions.2957786560
Short name	T974
Test name
Test status
Simulation time	14581697900 ps
CPU time	1087.68 seconds
Started	Aug 13 06:19:04 PM PDT 24
Finished	Aug 13 06:37:12 PM PDT 24
Peak memory	274972 kb
Host	smart-b0240284-2b62-419d-aca2-643f2a0084f1
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957786560 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_mp_regions.2957786560
Directory	/workspace/14.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/14.flash_ctrl_otp_reset.3904188363
Short name	T770
Test name
Test status
Simulation time	35987600 ps
CPU time	131.91 seconds
Started	Aug 13 06:19:03 PM PDT 24
Finished	Aug 13 06:21:15 PM PDT 24
Peak memory	260528 kb
Host	smart-580cd664-0795-4fe2-9300-e539ba1cd273
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904188363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_o tp_reset.3904188363
Directory	/workspace/14.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/14.flash_ctrl_phy_arb.1101211151
Short name	T721
Test name
Test status
Simulation time	1390889400 ps
CPU time	171.44 seconds
Started	Aug 13 06:19:03 PM PDT 24
Finished	Aug 13 06:21:54 PM PDT 24
Peak memory	263816 kb
Host	smart-aac3f9fc-0eb0-4adf-8858-c5f8e9dd441a
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1101211151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.1101211151
Directory	/workspace/14.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/14.flash_ctrl_prog_reset.2690452027
Short name	T641
Test name
Test status
Simulation time	71690000 ps
CPU time	13.74 seconds
Started	Aug 13 06:19:10 PM PDT 24
Finished	Aug 13 06:19:24 PM PDT 24
Peak memory	265620 kb
Host	smart-59a72c89-67f6-4c88-9bd2-6e5efbf2b743
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690452027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 14.flash_ctrl_prog_reset.2690452027
Directory	/workspace/14.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/14.flash_ctrl_rand_ops.3610232337
Short name	T535
Test name
Test status
Simulation time	4391531300 ps
CPU time	786.66 seconds
Started	Aug 13 06:19:00 PM PDT 24
Finished	Aug 13 06:32:06 PM PDT 24
Peak memory	285768 kb
Host	smart-2a44edb9-1563-41f9-801d-4856cd8d6592
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3610232337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.3610232337
Directory	/workspace/14.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/14.flash_ctrl_re_evict.1188090538
Short name	T786
Test name
Test status
Simulation time	190008800 ps
CPU time	34.35 seconds
Started	Aug 13 06:19:13 PM PDT 24
Finished	Aug 13 06:19:47 PM PDT 24
Peak memory	273856 kb
Host	smart-b93aa8f9-0085-4f16-9dc9-691e055343b8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188090538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl ash_ctrl_re_evict.1188090538
Directory	/workspace/14.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/14.flash_ctrl_rw.3280379305
Short name	T939
Test name
Test status
Simulation time	29824653900 ps
CPU time	619.16 seconds
Started	Aug 13 06:19:03 PM PDT 24
Finished	Aug 13 06:29:23 PM PDT 24
Peak memory	310328 kb
Host	smart-0c5f65ee-085f-4df7-8ff2-deb62c917d69
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280379305 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 14.flash_ctrl_rw.3280379305
Directory	/workspace/14.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/14.flash_ctrl_rw_evict.3541803003
Short name	T634
Test name
Test status
Simulation time	66999400 ps
CPU time	30.66 seconds
Started	Aug 13 06:19:11 PM PDT 24
Finished	Aug 13 06:19:42 PM PDT 24
Peak memory	276196 kb
Host	smart-d426bdfd-7244-4447-bf6f-5db56bf3c9d5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541803003 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.fl ash_ctrl_rw_evict.3541803003
Directory	/workspace/14.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/14.flash_ctrl_rw_evict_all_en.3474678847
Short name	T411
Test name
Test status
Simulation time	33278200 ps
CPU time	30.15 seconds
Started	Aug 13 06:19:11 PM PDT 24
Finished	Aug 13 06:19:41 PM PDT 24
Peak memory	275584 kb
Host	smart-6b4c789f-a213-4f2a-9424-6da390e61653
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474678847 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict_all_en.3474678847
Directory	/workspace/14.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/14.flash_ctrl_sec_info_access.3475497379
Short name	T239
Test name
Test status
Simulation time	1638640300 ps
CPU time	69.79 seconds
Started	Aug 13 06:19:12 PM PDT 24
Finished	Aug 13 06:20:22 PM PDT 24
Peak memory	264304 kb
Host	smart-9f4b72c0-9a77-4207-ad3b-f49ff37356b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3475497379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.3475497379
Directory	/workspace/14.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/14.flash_ctrl_smoke.1987155086
Short name	T847
Test name
Test status
Simulation time	132262000 ps
CPU time	171.19 seconds
Started	Aug 13 06:18:55 PM PDT 24
Finished	Aug 13 06:21:46 PM PDT 24
Peak memory	277504 kb
Host	smart-2f664aa2-faf2-4ae8-bbf1-63354fa92860
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1987155086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.1987155086
Directory	/workspace/14.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/14.flash_ctrl_wo.2687437321
Short name	T604
Test name
Test status
Simulation time	3941627200 ps
CPU time	172.9 seconds
Started	Aug 13 06:19:04 PM PDT 24
Finished	Aug 13 06:21:57 PM PDT 24
Peak memory	261568 kb
Host	smart-952015e1-1919-41d9-ba7b-67e747752f1c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687437321 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 14.flash_ctrl_wo.2687437321
Directory	/workspace/14.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/15.flash_ctrl_alert_test.4150048950
Short name	T855
Test name
Test status
Simulation time	21216300 ps
CPU time	13.58 seconds
Started	Aug 13 06:19:28 PM PDT 24
Finished	Aug 13 06:19:42 PM PDT 24
Peak memory	265700 kb
Host	smart-20643fae-b668-420e-b60f-f33cb06d93b9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150048950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test. 4150048950
Directory	/workspace/15.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/15.flash_ctrl_connect.1247914333
Short name	T146
Test name
Test status
Simulation time	44022300 ps
CPU time	15.91 seconds
Started	Aug 13 06:19:25 PM PDT 24
Finished	Aug 13 06:19:41 PM PDT 24
Peak memory	284864 kb
Host	smart-a1883660-b93e-4fe8-9f14-9c25e9d5fc81
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1247914333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.1247914333
Directory	/workspace/15.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.380404395
Short name	T291
Test name
Test status
Simulation time	10012302500 ps
CPU time	146.58 seconds
Started	Aug 13 06:19:26 PM PDT 24
Finished	Aug 13 06:21:53 PM PDT 24
Peak memory	384884 kb
Host	smart-778fdd77-8863-4911-83ec-7c63a8c31449
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380404395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.380404395
Directory	/workspace/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.2295650430
Short name	T165
Test name
Test status
Simulation time	26237000 ps
CPU time	13.66 seconds
Started	Aug 13 06:19:26 PM PDT 24
Finished	Aug 13 06:19:40 PM PDT 24
Peak memory	258928 kb
Host	smart-ce8df44d-3c8b-4694-8425-6c0da9cc4998
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295650430 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_read_seed_err.2295650430
Directory	/workspace/15.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/15.flash_ctrl_hw_rma_reset.2308459182
Short name	T191
Test name
Test status
Simulation time	60133814700 ps
CPU time	903.95 seconds
Started	Aug 13 06:19:18 PM PDT 24
Finished	Aug 13 06:34:23 PM PDT 24
Peak memory	264456 kb
Host	smart-1398c1e4-d968-4591-af46-89e86f37c81b
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308459182 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 15.flash_ctrl_hw_rma_reset.2308459182
Directory	/workspace/15.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/15.flash_ctrl_hw_sec_otp.443914489
Short name	T633
Test name
Test status
Simulation time	1829229900 ps
CPU time	53.48 seconds
Started	Aug 13 06:19:18 PM PDT 24
Finished	Aug 13 06:20:11 PM PDT 24
Peak memory	263736 kb
Host	smart-3e897fd8-0104-4ccf-9b32-49a633af6357
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443914489 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_h w_sec_otp.443914489
Directory	/workspace/15.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/15.flash_ctrl_intr_rd.1230953841
Short name	T866
Test name
Test status
Simulation time	4160933800 ps
CPU time	102.7 seconds
Started	Aug 13 06:19:21 PM PDT 24
Finished	Aug 13 06:21:04 PM PDT 24
Peak memory	295052 kb
Host	smart-1b961460-47ae-44eb-b488-a0fbd016e143
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230953841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla sh_ctrl_intr_rd.1230953841
Directory	/workspace/15.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/15.flash_ctrl_intr_rd_slow_flash.656654606
Short name	T964
Test name
Test status
Simulation time	15193635600 ps
CPU time	279.31 seconds
Started	Aug 13 06:19:17 PM PDT 24
Finished	Aug 13 06:23:56 PM PDT 24
Peak memory	285716 kb
Host	smart-4709fba1-9358-47e4-ad78-225a04156767
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656654606 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd_slow_flash.656654606
Directory	/workspace/15.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/15.flash_ctrl_lcmgr_intg.3119341338
Short name	T1008
Test name
Test status
Simulation time	19407700 ps
CPU time	13.24 seconds
Started	Aug 13 06:19:25 PM PDT 24
Finished	Aug 13 06:19:39 PM PDT 24
Peak memory	260692 kb
Host	smart-288a85ed-e8a3-42ad-a569-a0303c6e757a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119341338 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 15.flash_ctrl_lcmgr_intg.3119341338
Directory	/workspace/15.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/15.flash_ctrl_mp_regions.1057705309
Short name	T613
Test name
Test status
Simulation time	4186944100 ps
CPU time	177.04 seconds
Started	Aug 13 06:19:17 PM PDT 24
Finished	Aug 13 06:22:14 PM PDT 24
Peak memory	264148 kb
Host	smart-98b45c39-55e6-4486-b03a-c2a229966235
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057705309 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_mp_regions.1057705309
Directory	/workspace/15.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/15.flash_ctrl_otp_reset.338534753
Short name	T760
Test name
Test status
Simulation time	123825700 ps
CPU time	132.57 seconds
Started	Aug 13 06:19:17 PM PDT 24
Finished	Aug 13 06:21:29 PM PDT 24
Peak memory	260876 kb
Host	smart-01f70fbe-f325-475e-b93b-735a24389579
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338534753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_ot p_reset.338534753
Directory	/workspace/15.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/15.flash_ctrl_phy_arb.3799611956
Short name	T632
Test name
Test status
Simulation time	1421099900 ps
CPU time	569.38 seconds
Started	Aug 13 06:19:13 PM PDT 24
Finished	Aug 13 06:28:43 PM PDT 24
Peak memory	263668 kb
Host	smart-e02d5ef3-0758-4956-b106-378f94367267
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3799611956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.3799611956
Directory	/workspace/15.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/15.flash_ctrl_prog_reset.492581823
Short name	T582
Test name
Test status
Simulation time	23450300 ps
CPU time	13.57 seconds
Started	Aug 13 06:19:21 PM PDT 24
Finished	Aug 13 06:19:35 PM PDT 24
Peak memory	259708 kb
Host	smart-c6c0218a-0339-472b-a449-7fb10fb3b3a5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492581823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 15.flash_ctrl_prog_reset.492581823
Directory	/workspace/15.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/15.flash_ctrl_rand_ops.1995292271
Short name	T445
Test name
Test status
Simulation time	64425800 ps
CPU time	79.46 seconds
Started	Aug 13 06:19:13 PM PDT 24
Finished	Aug 13 06:20:33 PM PDT 24
Peak memory	277656 kb
Host	smart-55d36052-c563-4d17-a9d0-1e92f48546fe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1995292271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.1995292271
Directory	/workspace/15.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/15.flash_ctrl_re_evict.3652484932
Short name	T397
Test name
Test status
Simulation time	584032600 ps
CPU time	35.82 seconds
Started	Aug 13 06:19:21 PM PDT 24
Finished	Aug 13 06:19:57 PM PDT 24
Peak memory	276344 kb
Host	smart-364db1ab-efe2-4f5d-a706-9007c3c2c010
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652484932 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.fl ash_ctrl_re_evict.3652484932
Directory	/workspace/15.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/15.flash_ctrl_ro.2154238077
Short name	T310
Test name
Test status
Simulation time	547020100 ps
CPU time	124.72 seconds
Started	Aug 13 06:19:18 PM PDT 24
Finished	Aug 13 06:21:23 PM PDT 24
Peak memory	289876 kb
Host	smart-55f2d6dc-cddb-46b7-9348-b73bc7f88b85
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154238077 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 15.flash_ctrl_ro.2154238077
Directory	/workspace/15.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/15.flash_ctrl_rw.3557810285
Short name	T982
Test name
Test status
Simulation time	5088874400 ps
CPU time	588.31 seconds
Started	Aug 13 06:19:19 PM PDT 24
Finished	Aug 13 06:29:07 PM PDT 24
Peak memory	315120 kb
Host	smart-9e0cbe69-ca6e-4f94-8026-a37051e27c11
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557810285 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 15.flash_ctrl_rw.3557810285
Directory	/workspace/15.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/15.flash_ctrl_sec_info_access.3164680664
Short name	T765
Test name
Test status
Simulation time	637453600 ps
CPU time	68.63 seconds
Started	Aug 13 06:19:25 PM PDT 24
Finished	Aug 13 06:20:33 PM PDT 24
Peak memory	263748 kb
Host	smart-6ed72de9-28fb-44e7-8fb2-699f5aa18283
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3164680664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.3164680664
Directory	/workspace/15.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/15.flash_ctrl_smoke.3404535622
Short name	T465
Test name
Test status
Simulation time	95123800 ps
CPU time	99.67 seconds
Started	Aug 13 06:19:09 PM PDT 24
Finished	Aug 13 06:20:49 PM PDT 24
Peak memory	276348 kb
Host	smart-13fb662b-656a-4bac-af81-26d909e400bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3404535622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.3404535622
Directory	/workspace/15.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/15.flash_ctrl_wo.4249768426
Short name	T366
Test name
Test status
Simulation time	2786433700 ps
CPU time	176.13 seconds
Started	Aug 13 06:19:16 PM PDT 24
Finished	Aug 13 06:22:12 PM PDT 24
Peak memory	260504 kb
Host	smart-b44e28d2-2921-457f-a751-becd9cdaddc2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249768426 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 15.flash_ctrl_wo.4249768426
Directory	/workspace/15.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/16.flash_ctrl_alert_test.455295591
Short name	T1001
Test name
Test status
Simulation time	28473800 ps
CPU time	14 seconds
Started	Aug 13 06:19:32 PM PDT 24
Finished	Aug 13 06:19:46 PM PDT 24
Peak memory	265704 kb
Host	smart-3da2bffb-97ce-400a-ae14-422014236d76
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455295591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.455295591
Directory	/workspace/16.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/16.flash_ctrl_connect.338614535
Short name	T443
Test name
Test status
Simulation time	15728100 ps
CPU time	15.77 seconds
Started	Aug 13 06:19:31 PM PDT 24
Finished	Aug 13 06:19:47 PM PDT 24
Peak memory	284796 kb
Host	smart-5a92bad5-f888-4c21-88c7-ae7db80af550
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=338614535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.338614535
Directory	/workspace/16.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/16.flash_ctrl_disable.1136851958
Short name	T952
Test name
Test status
Simulation time	15681200 ps
CPU time	22.17 seconds
Started	Aug 13 06:19:33 PM PDT 24
Finished	Aug 13 06:19:55 PM PDT 24
Peak memory	273940 kb
Host	smart-b0dc1ac1-955d-4af5-8894-7f2aec86001d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136851958 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_disable.1136851958
Directory	/workspace/16.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.921449950
Short name	T286
Test name
Test status
Simulation time	10013270000 ps
CPU time	110.9 seconds
Started	Aug 13 06:19:34 PM PDT 24
Finished	Aug 13 06:21:25 PM PDT 24
Peak memory	313560 kb
Host	smart-c1514207-1862-44ab-850c-0183437c9537
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921449950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.921449950
Directory	/workspace/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.2883978822
Short name	T1109
Test name
Test status
Simulation time	26753100 ps
CPU time	13.41 seconds
Started	Aug 13 06:19:33 PM PDT 24
Finished	Aug 13 06:19:46 PM PDT 24
Peak memory	265300 kb
Host	smart-029aa8a4-112a-4dc7-998f-9ec52b71e86b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883978822 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_read_seed_err.2883978822
Directory	/workspace/16.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/16.flash_ctrl_hw_sec_otp.3392267020
Short name	T668
Test name
Test status
Simulation time	8139633100 ps
CPU time	125.96 seconds
Started	Aug 13 06:19:26 PM PDT 24
Finished	Aug 13 06:21:32 PM PDT 24
Peak memory	261112 kb
Host	smart-5d02a2bd-7d60-40ed-b64a-5c0dc5a248e5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392267020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_ hw_sec_otp.3392267020
Directory	/workspace/16.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/16.flash_ctrl_intr_rd.762158732
Short name	T331
Test name
Test status
Simulation time	8167371900 ps
CPU time	211.71 seconds
Started	Aug 13 06:19:22 PM PDT 24
Finished	Aug 13 06:22:53 PM PDT 24
Peak memory	291484 kb
Host	smart-d5ae72a7-8552-40ad-bdc3-b91345c378ad
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762158732 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flas h_ctrl_intr_rd.762158732
Directory	/workspace/16.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.2871912456
Short name	T627
Test name
Test status
Simulation time	72146822700 ps
CPU time	301.93 seconds
Started	Aug 13 06:19:34 PM PDT 24
Finished	Aug 13 06:24:36 PM PDT 24
Peak memory	285864 kb
Host	smart-7ce9f751-83de-4819-bdf8-eb81f355176c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871912456 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd_slow_flash.2871912456
Directory	/workspace/16.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/16.flash_ctrl_invalid_op.194829381
Short name	T805
Test name
Test status
Simulation time	2797789700 ps
CPU time	66.31 seconds
Started	Aug 13 06:19:26 PM PDT 24
Finished	Aug 13 06:20:32 PM PDT 24
Peak memory	264080 kb
Host	smart-86eeae4f-f873-4181-9307-a2b300f3a691
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194829381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.194829381
Directory	/workspace/16.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/16.flash_ctrl_lcmgr_intg.367813274
Short name	T449
Test name
Test status
Simulation time	15011200 ps
CPU time	13.6 seconds
Started	Aug 13 06:19:32 PM PDT 24
Finished	Aug 13 06:19:46 PM PDT 24
Peak memory	265380 kb
Host	smart-1f5d42ae-16af-4f09-9c44-98bb4478a7a9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367813274 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 16.flash_ctrl_lcmgr_intg.367813274
Directory	/workspace/16.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/16.flash_ctrl_mp_regions.12241604
Short name	T120
Test name
Test status
Simulation time	8265331900 ps
CPU time	576.11 seconds
Started	Aug 13 06:19:24 PM PDT 24
Finished	Aug 13 06:29:01 PM PDT 24
Peak memory	275860 kb
Host	smart-0447d608-0781-4436-8d7c-036ebe792916
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12241604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_mp_regions.12241604
Directory	/workspace/16.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/16.flash_ctrl_phy_arb.3845719634
Short name	T850
Test name
Test status
Simulation time	728958900 ps
CPU time	303.7 seconds
Started	Aug 13 06:19:28 PM PDT 24
Finished	Aug 13 06:24:32 PM PDT 24
Peak memory	263672 kb
Host	smart-0feb5223-9ec5-418c-98f7-3efe32a16c79
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3845719634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.3845719634
Directory	/workspace/16.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/16.flash_ctrl_prog_reset.857881851
Short name	T734
Test name
Test status
Simulation time	185272500 ps
CPU time	13.77 seconds
Started	Aug 13 06:19:34 PM PDT 24
Finished	Aug 13 06:19:48 PM PDT 24
Peak memory	265632 kb
Host	smart-945bdb1d-609a-496e-8174-09e79a972ff7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857881851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 16.flash_ctrl_prog_reset.857881851
Directory	/workspace/16.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/16.flash_ctrl_rand_ops.2881362533
Short name	T622
Test name
Test status
Simulation time	4591892900 ps
CPU time	644.29 seconds
Started	Aug 13 06:19:25 PM PDT 24
Finished	Aug 13 06:30:09 PM PDT 24
Peak memory	285904 kb
Host	smart-47ec8191-ae37-4daf-9dee-6de785c11c83
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2881362533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.2881362533
Directory	/workspace/16.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/16.flash_ctrl_re_evict.3256535882
Short name	T771
Test name
Test status
Simulation time	901054500 ps
CPU time	36.64 seconds
Started	Aug 13 06:19:34 PM PDT 24
Finished	Aug 13 06:20:11 PM PDT 24
Peak memory	274100 kb
Host	smart-32701563-d162-4e1c-9855-5f4aa91016f1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256535882 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.fl ash_ctrl_re_evict.3256535882
Directory	/workspace/16.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/16.flash_ctrl_ro.2163925164
Short name	T374
Test name
Test status
Simulation time	526672400 ps
CPU time	115.33 seconds
Started	Aug 13 06:19:26 PM PDT 24
Finished	Aug 13 06:21:21 PM PDT 24
Peak memory	292000 kb
Host	smart-26b79a3a-94a2-439d-8b5b-eb0503d15bdf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163925164 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 16.flash_ctrl_ro.2163925164
Directory	/workspace/16.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/16.flash_ctrl_rw.850087283
Short name	T522
Test name
Test status
Simulation time	2995328900 ps
CPU time	477.95 seconds
Started	Aug 13 06:19:26 PM PDT 24
Finished	Aug 13 06:27:24 PM PDT 24
Peak memory	314932 kb
Host	smart-8ed7e098-151f-4a63-a2ef-ab568fafc61d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850087283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rw.850087283
Directory	/workspace/16.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/16.flash_ctrl_rw_evict_all_en.2565313966
Short name	T579
Test name
Test status
Simulation time	29669800 ps
CPU time	31.15 seconds
Started	Aug 13 06:19:32 PM PDT 24
Finished	Aug 13 06:20:03 PM PDT 24
Peak memory	275524 kb
Host	smart-d601793f-b596-459b-824b-0e5f30b30b46
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565313966 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict_all_en.2565313966
Directory	/workspace/16.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/16.flash_ctrl_sec_info_access.647612360
Short name	T24
Test name
Test status
Simulation time	2005703400 ps
CPU time	71.95 seconds
Started	Aug 13 06:19:33 PM PDT 24
Finished	Aug 13 06:20:45 PM PDT 24
Peak memory	263916 kb
Host	smart-969c507f-cb59-4a66-901c-ff6b49dec943
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=647612360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.647612360
Directory	/workspace/16.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/16.flash_ctrl_smoke.2750709799
Short name	T695
Test name
Test status
Simulation time	134825100 ps
CPU time	167.71 seconds
Started	Aug 13 06:19:26 PM PDT 24
Finished	Aug 13 06:22:14 PM PDT 24
Peak memory	277740 kb
Host	smart-e9b265c8-9114-4709-adf9-714a699d8e0f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2750709799 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.2750709799
Directory	/workspace/16.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/16.flash_ctrl_wo.2162367014
Short name	T828
Test name
Test status
Simulation time	2206141500 ps
CPU time	164.33 seconds
Started	Aug 13 06:19:25 PM PDT 24
Finished	Aug 13 06:22:10 PM PDT 24
Peak memory	260572 kb
Host	smart-e4b161cd-0de4-4f96-afcb-0a5a7315edf0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162367014 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 16.flash_ctrl_wo.2162367014
Directory	/workspace/16.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/17.flash_ctrl_alert_test.1851462409
Short name	T372
Test name
Test status
Simulation time	61126100 ps
CPU time	13.39 seconds
Started	Aug 13 06:19:46 PM PDT 24
Finished	Aug 13 06:20:00 PM PDT 24
Peak memory	258808 kb
Host	smart-daa5956d-eeb5-42f2-a776-d89e0ebc268e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851462409 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test. 1851462409
Directory	/workspace/17.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/17.flash_ctrl_connect.2211879179
Short name	T1078
Test name
Test status
Simulation time	52347400 ps
CPU time	15.94 seconds
Started	Aug 13 06:19:41 PM PDT 24
Finished	Aug 13 06:19:57 PM PDT 24
Peak memory	284812 kb
Host	smart-248b1d98-2ec1-43ac-9c50-1e38c4d30f95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2211879179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.2211879179
Directory	/workspace/17.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/17.flash_ctrl_disable.70023114
Short name	T1047
Test name
Test status
Simulation time	84372100 ps
CPU time	20.88 seconds
Started	Aug 13 06:19:41 PM PDT 24
Finished	Aug 13 06:20:02 PM PDT 24
Peak memory	274060 kb
Host	smart-c1476c0c-ac93-45b2-818c-b5b4162744ed
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70023114 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 17.flash_ctrl_disable.70023114
Directory	/workspace/17.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.767117510
Short name	T514
Test name
Test status
Simulation time	10112312000 ps
CPU time	41.39 seconds
Started	Aug 13 06:19:53 PM PDT 24
Finished	Aug 13 06:20:34 PM PDT 24
Peak memory	265028 kb
Host	smart-3fa5056d-86f0-4f59-935b-c803bb50e27b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767117510 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.767117510
Directory	/workspace/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.728102640
Short name	T1058
Test name
Test status
Simulation time	56665600 ps
CPU time	13.63 seconds
Started	Aug 13 06:19:43 PM PDT 24
Finished	Aug 13 06:19:56 PM PDT 24
Peak memory	258996 kb
Host	smart-df3dd228-e8b1-494b-9009-98acbccf866e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728102640 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_read_seed_err.728102640
Directory	/workspace/17.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/17.flash_ctrl_hw_rma_reset.987668180
Short name	T163
Test name
Test status
Simulation time	40125039200 ps
CPU time	872.29 seconds
Started	Aug 13 06:19:41 PM PDT 24
Finished	Aug 13 06:34:14 PM PDT 24
Peak memory	265548 kb
Host	smart-1a3d18f4-c0d7-4cbb-84ef-2d4722aa1a5f
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987668180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 17.flash_ctrl_hw_rma_reset.987668180
Directory	/workspace/17.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/17.flash_ctrl_hw_sec_otp.3589465279
Short name	T256
Test name
Test status
Simulation time	36234508500 ps
CPU time	280.9 seconds
Started	Aug 13 06:19:41 PM PDT 24
Finished	Aug 13 06:24:22 PM PDT 24
Peak memory	261480 kb
Host	smart-d9214fdd-0785-4a7e-a187-2241e2b7e316
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589465279 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_ hw_sec_otp.3589465279
Directory	/workspace/17.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/17.flash_ctrl_intr_rd.2781762292
Short name	T51
Test name
Test status
Simulation time	1665226600 ps
CPU time	221.48 seconds
Started	Aug 13 06:19:40 PM PDT 24
Finished	Aug 13 06:23:22 PM PDT 24
Peak memory	285820 kb
Host	smart-cf4086ea-323b-4142-b500-0b0ce8d910e3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781762292 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla sh_ctrl_intr_rd.2781762292
Directory	/workspace/17.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/17.flash_ctrl_intr_rd_slow_flash.3393657258
Short name	T949
Test name
Test status
Simulation time	12287522200 ps
CPU time	210.84 seconds
Started	Aug 13 06:19:41 PM PDT 24
Finished	Aug 13 06:23:12 PM PDT 24
Peak memory	291656 kb
Host	smart-c3feef0a-c966-4fc3-9365-ca9a5e322f30
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393657258 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd_slow_flash.3393657258
Directory	/workspace/17.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/17.flash_ctrl_invalid_op.3243450934
Short name	T391
Test name
Test status
Simulation time	2127411500 ps
CPU time	68.59 seconds
Started	Aug 13 06:19:40 PM PDT 24
Finished	Aug 13 06:20:49 PM PDT 24
Peak memory	264056 kb
Host	smart-255914bd-51e4-4ed1-9921-c557b73b3cfa
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243450934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.3 243450934
Directory	/workspace/17.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/17.flash_ctrl_lcmgr_intg.4224438421
Short name	T446
Test name
Test status
Simulation time	31570000 ps
CPU time	13.66 seconds
Started	Aug 13 06:19:41 PM PDT 24
Finished	Aug 13 06:19:54 PM PDT 24
Peak memory	260740 kb
Host	smart-7ab8d185-eb45-4f80-bca8-471a5c7de229
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224438421 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 17.flash_ctrl_lcmgr_intg.4224438421
Directory	/workspace/17.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/17.flash_ctrl_mp_regions.1356664691
Short name	T114
Test name
Test status
Simulation time	14817706000 ps
CPU time	565.48 seconds
Started	Aug 13 06:19:42 PM PDT 24
Finished	Aug 13 06:29:08 PM PDT 24
Peak memory	275016 kb
Host	smart-2aeae378-4b52-4302-a7c1-f4fa4b467cb1
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356664691 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_mp_regions.1356664691
Directory	/workspace/17.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/17.flash_ctrl_otp_reset.1670696438
Short name	T178
Test name
Test status
Simulation time	39720900 ps
CPU time	133.66 seconds
Started	Aug 13 06:19:38 PM PDT 24
Finished	Aug 13 06:21:52 PM PDT 24
Peak memory	260652 kb
Host	smart-b36f202f-6b58-4172-b750-51d794bea493
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670696438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_o tp_reset.1670696438
Directory	/workspace/17.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/17.flash_ctrl_phy_arb.3645795981
Short name	T996
Test name
Test status
Simulation time	1400067300 ps
CPU time	323.55 seconds
Started	Aug 13 06:19:40 PM PDT 24
Finished	Aug 13 06:25:03 PM PDT 24
Peak memory	263812 kb
Host	smart-2527b9e0-184f-47e4-bbb0-304ee20075a5
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3645795981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.3645795981
Directory	/workspace/17.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/17.flash_ctrl_prog_reset.3337347462
Short name	T452
Test name
Test status
Simulation time	1003153000 ps
CPU time	44.93 seconds
Started	Aug 13 06:19:40 PM PDT 24
Finished	Aug 13 06:20:25 PM PDT 24
Peak memory	260800 kb
Host	smart-b3ccfcaa-f0ec-427b-a4f2-00c6cd164ab2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337347462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 17.flash_ctrl_prog_reset.3337347462
Directory	/workspace/17.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/17.flash_ctrl_rand_ops.2339426327
Short name	T780
Test name
Test status
Simulation time	870549600 ps
CPU time	958.38 seconds
Started	Aug 13 06:19:40 PM PDT 24
Finished	Aug 13 06:35:39 PM PDT 24
Peak memory	284552 kb
Host	smart-de8d3585-7c88-4b8d-aa1c-2814a91b0f75
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2339426327 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.2339426327
Directory	/workspace/17.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/17.flash_ctrl_re_evict.1593296008
Short name	T880
Test name
Test status
Simulation time	210008100 ps
CPU time	34.24 seconds
Started	Aug 13 06:19:42 PM PDT 24
Finished	Aug 13 06:20:16 PM PDT 24
Peak memory	276444 kb
Host	smart-bd2d99ce-ae50-4b33-a6e4-6f22b8b35024
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593296008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.fl ash_ctrl_re_evict.1593296008
Directory	/workspace/17.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/17.flash_ctrl_ro.1088041613
Short name	T821
Test name
Test status
Simulation time	459404600 ps
CPU time	115.87 seconds
Started	Aug 13 06:19:40 PM PDT 24
Finished	Aug 13 06:21:36 PM PDT 24
Peak memory	290596 kb
Host	smart-28e2a4d4-17c4-40a1-88c0-eab973d6c8ee
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088041613 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 17.flash_ctrl_ro.1088041613
Directory	/workspace/17.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/17.flash_ctrl_rw.1821163724
Short name	T130
Test name
Test status
Simulation time	14414405200 ps
CPU time	497.98 seconds
Started	Aug 13 06:19:41 PM PDT 24
Finished	Aug 13 06:27:59 PM PDT 24
Peak memory	310152 kb
Host	smart-146961ca-ed2c-44d8-83fe-898701c5b7df
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821163724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 17.flash_ctrl_rw.1821163724
Directory	/workspace/17.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/17.flash_ctrl_sec_info_access.3689289610
Short name	T694
Test name
Test status
Simulation time	6612925100 ps
CPU time	75.92 seconds
Started	Aug 13 06:19:40 PM PDT 24
Finished	Aug 13 06:20:56 PM PDT 24
Peak memory	263620 kb
Host	smart-68a62e07-d0db-47dc-8eb5-dd0d73c1b61b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3689289610 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.3689289610
Directory	/workspace/17.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/17.flash_ctrl_smoke.3121387977
Short name	T373
Test name
Test status
Simulation time	117790900 ps
CPU time	121.72 seconds
Started	Aug 13 06:19:40 PM PDT 24
Finished	Aug 13 06:21:41 PM PDT 24
Peak memory	276928 kb
Host	smart-1eb4e305-c41f-49ff-8c72-cbe38da34dc8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3121387977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.3121387977
Directory	/workspace/17.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/17.flash_ctrl_wo.1419758522
Short name	T884
Test name
Test status
Simulation time	5262641200 ps
CPU time	191.76 seconds
Started	Aug 13 06:19:38 PM PDT 24
Finished	Aug 13 06:22:50 PM PDT 24
Peak memory	265680 kb
Host	smart-20bf0277-bb14-45f7-a5c1-e4235478223f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419758522 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 17.flash_ctrl_wo.1419758522
Directory	/workspace/17.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/18.flash_ctrl_alert_test.4245364782
Short name	T841
Test name
Test status
Simulation time	31133000 ps
CPU time	13.73 seconds
Started	Aug 13 06:19:57 PM PDT 24
Finished	Aug 13 06:20:11 PM PDT 24
Peak memory	258636 kb
Host	smart-1d25a316-532e-4c40-95c4-ea1916158449
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245364782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test. 4245364782
Directory	/workspace/18.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/18.flash_ctrl_connect.3712033401
Short name	T551
Test name
Test status
Simulation time	16567100 ps
CPU time	16.11 seconds
Started	Aug 13 06:19:57 PM PDT 24
Finished	Aug 13 06:20:14 PM PDT 24
Peak memory	284860 kb
Host	smart-02a5c6de-6557-49b5-965a-e9c119dfd277
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3712033401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.3712033401
Directory	/workspace/18.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/18.flash_ctrl_disable.1796662609
Short name	T121
Test name
Test status
Simulation time	35341500 ps
CPU time	21.93 seconds
Started	Aug 13 06:19:55 PM PDT 24
Finished	Aug 13 06:20:17 PM PDT 24
Peak memory	274104 kb
Host	smart-5c3b505c-2205-4206-9dc5-eab793a4eeae
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796662609 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_disable.1796662609
Directory	/workspace/18.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.1197427995
Short name	T177
Test name
Test status
Simulation time	10019980500 ps
CPU time	83.07 seconds
Started	Aug 13 06:19:55 PM PDT 24
Finished	Aug 13 06:21:18 PM PDT 24
Peak memory	292364 kb
Host	smart-a6dc2dc0-30da-4c1d-8de0-003fbe8c049b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197427995 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.1197427995
Directory	/workspace/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/18.flash_ctrl_hw_read_seed_err.809544133
Short name	T537
Test name
Test status
Simulation time	15564100 ps
CPU time	13.32 seconds
Started	Aug 13 06:19:54 PM PDT 24
Finished	Aug 13 06:20:08 PM PDT 24
Peak memory	259024 kb
Host	smart-fc093af1-46e7-41d9-8e91-79638edcbe39
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809544133 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_read_seed_err.809544133
Directory	/workspace/18.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/18.flash_ctrl_hw_sec_otp.1678420453
Short name	T36
Test name
Test status
Simulation time	3728013700 ps
CPU time	92.57 seconds
Started	Aug 13 06:19:50 PM PDT 24
Finished	Aug 13 06:21:22 PM PDT 24
Peak memory	263716 kb
Host	smart-4267cde7-eb9b-411c-9659-32016010d8df
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678420453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_ hw_sec_otp.1678420453
Directory	/workspace/18.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/18.flash_ctrl_intr_rd.2755700822
Short name	T497
Test name
Test status
Simulation time	6611269600 ps
CPU time	199.61 seconds
Started	Aug 13 06:19:52 PM PDT 24
Finished	Aug 13 06:23:12 PM PDT 24
Peak memory	291460 kb
Host	smart-7c088470-a325-48fe-9c18-60246d8051d3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755700822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla sh_ctrl_intr_rd.2755700822
Directory	/workspace/18.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/18.flash_ctrl_intr_rd_slow_flash.1288075261
Short name	T595
Test name
Test status
Simulation time	23169011900 ps
CPU time	265.94 seconds
Started	Aug 13 06:19:48 PM PDT 24
Finished	Aug 13 06:24:14 PM PDT 24
Peak memory	290320 kb
Host	smart-c7d984c6-3628-49cd-897e-9c6bf7bcb687
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288075261 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd_slow_flash.1288075261
Directory	/workspace/18.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/18.flash_ctrl_invalid_op.2709055584
Short name	T129
Test name
Test status
Simulation time	8704684500 ps
CPU time	69.89 seconds
Started	Aug 13 06:19:48 PM PDT 24
Finished	Aug 13 06:20:58 PM PDT 24
Peak memory	261140 kb
Host	smart-4ad28386-8ff8-4725-96d3-bafe6a7684ee
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709055584 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.2 709055584
Directory	/workspace/18.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/18.flash_ctrl_mp_regions.2704453490
Short name	T854
Test name
Test status
Simulation time	34800242100 ps
CPU time	398.78 seconds
Started	Aug 13 06:19:49 PM PDT 24
Finished	Aug 13 06:26:28 PM PDT 24
Peak memory	276036 kb
Host	smart-a67d7f1c-83ec-45ec-8cff-728656eac36c
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704453490 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_mp_regions.2704453490
Directory	/workspace/18.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/18.flash_ctrl_otp_reset.2853751938
Short name	T182
Test name
Test status
Simulation time	64948600 ps
CPU time	131.37 seconds
Started	Aug 13 06:19:47 PM PDT 24
Finished	Aug 13 06:21:59 PM PDT 24
Peak memory	260508 kb
Host	smart-50ce89f1-37c7-439b-977b-9c0199535124
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853751938 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_o tp_reset.2853751938
Directory	/workspace/18.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/18.flash_ctrl_phy_arb.2379297556
Short name	T559
Test name
Test status
Simulation time	1448000000 ps
CPU time	506.58 seconds
Started	Aug 13 06:19:53 PM PDT 24
Finished	Aug 13 06:28:20 PM PDT 24
Peak memory	263648 kb
Host	smart-a9a628d8-7c09-40ee-8191-00e060d3124d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2379297556 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.2379297556
Directory	/workspace/18.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/18.flash_ctrl_prog_reset.2987578285
Short name	T511
Test name
Test status
Simulation time	142406500 ps
CPU time	21.46 seconds
Started	Aug 13 06:19:50 PM PDT 24
Finished	Aug 13 06:20:11 PM PDT 24
Peak memory	260672 kb
Host	smart-ffd5117f-94e1-4f11-8343-41e16b706be8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987578285 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 18.flash_ctrl_prog_reset.2987578285
Directory	/workspace/18.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/18.flash_ctrl_rand_ops.335674667
Short name	T520
Test name
Test status
Simulation time	57283800 ps
CPU time	102.09 seconds
Started	Aug 13 06:19:48 PM PDT 24
Finished	Aug 13 06:21:30 PM PDT 24
Peak memory	277128 kb
Host	smart-d7b2e29b-7b08-4bf6-bbab-469eba19d243
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=335674667 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.335674667
Directory	/workspace/18.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/18.flash_ctrl_re_evict.4081545036
Short name	T396
Test name
Test status
Simulation time	71038900 ps
CPU time	33.72 seconds
Started	Aug 13 06:19:57 PM PDT 24
Finished	Aug 13 06:20:31 PM PDT 24
Peak memory	276468 kb
Host	smart-66f33eac-d4b1-4ba6-b977-1e41861cccc0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081545036 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.fl ash_ctrl_re_evict.4081545036
Directory	/workspace/18.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/18.flash_ctrl_ro.2471630377
Short name	T638
Test name
Test status
Simulation time	582505700 ps
CPU time	112.88 seconds
Started	Aug 13 06:19:54 PM PDT 24
Finished	Aug 13 06:21:47 PM PDT 24
Peak memory	290568 kb
Host	smart-e32537e2-a781-41f3-8b12-4255cb8f35b4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471630377 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 18.flash_ctrl_ro.2471630377
Directory	/workspace/18.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/18.flash_ctrl_rw.2770367721
Short name	T895
Test name
Test status
Simulation time	8021421000 ps
CPU time	557.71 seconds
Started	Aug 13 06:19:50 PM PDT 24
Finished	Aug 13 06:29:08 PM PDT 24
Peak memory	315192 kb
Host	smart-a10780a5-e17f-4947-9879-5de86f4257ee
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770367721 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 18.flash_ctrl_rw.2770367721
Directory	/workspace/18.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/18.flash_ctrl_rw_evict_all_en.2360955916
Short name	T525
Test name
Test status
Simulation time	42660000 ps
CPU time	30.75 seconds
Started	Aug 13 06:19:57 PM PDT 24
Finished	Aug 13 06:20:28 PM PDT 24
Peak memory	275480 kb
Host	smart-e3b4aaf4-03e0-4281-a4c4-097465aefee2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360955916 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict_all_en.2360955916
Directory	/workspace/18.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/18.flash_ctrl_sec_info_access.3365926652
Short name	T383
Test name
Test status
Simulation time	3424479200 ps
CPU time	68.43 seconds
Started	Aug 13 06:19:55 PM PDT 24
Finished	Aug 13 06:21:04 PM PDT 24
Peak memory	264228 kb
Host	smart-313f009b-0aa5-4055-a4a3-e5df18ed2ea5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3365926652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.3365926652
Directory	/workspace/18.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/18.flash_ctrl_smoke.2310489397
Short name	T704
Test name
Test status
Simulation time	149093500 ps
CPU time	170.48 seconds
Started	Aug 13 06:19:50 PM PDT 24
Finished	Aug 13 06:22:40 PM PDT 24
Peak memory	277804 kb
Host	smart-76c20c32-3668-4863-bb8b-d3c5f6cde9a2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2310489397 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.2310489397
Directory	/workspace/18.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/18.flash_ctrl_wo.2740487561
Short name	T363
Test name
Test status
Simulation time	20822420200 ps
CPU time	180.18 seconds
Started	Aug 13 06:19:48 PM PDT 24
Finished	Aug 13 06:22:49 PM PDT 24
Peak memory	265828 kb
Host	smart-8fe0bc8d-be94-4328-aaf9-2b3414dd8b75
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740487561 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 18.flash_ctrl_wo.2740487561
Directory	/workspace/18.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/19.flash_ctrl_alert_test.3007404735
Short name	T674
Test name
Test status
Simulation time	45572700 ps
CPU time	13.28 seconds
Started	Aug 13 06:20:12 PM PDT 24
Finished	Aug 13 06:20:26 PM PDT 24
Peak memory	258952 kb
Host	smart-89a66e6f-a5bb-4fef-8ae3-5bb0f694dffd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007404735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test. 3007404735
Directory	/workspace/19.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/19.flash_ctrl_connect.2555422870
Short name	T793
Test name
Test status
Simulation time	14550900 ps
CPU time	13.61 seconds
Started	Aug 13 06:20:03 PM PDT 24
Finished	Aug 13 06:20:17 PM PDT 24
Peak memory	283592 kb
Host	smart-246c84e0-ea70-442a-b558-86f6e48bab84
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2555422870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.2555422870
Directory	/workspace/19.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/19.flash_ctrl_disable.907178539
Short name	T591
Test name
Test status
Simulation time	23008900 ps
CPU time	20.64 seconds
Started	Aug 13 06:20:04 PM PDT 24
Finished	Aug 13 06:20:25 PM PDT 24
Peak memory	273980 kb
Host	smart-3b46e1cf-0910-476f-a0eb-25a4ee587c42
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907178539 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_disable.907178539
Directory	/workspace/19.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.2283235231
Short name	T1073
Test name
Test status
Simulation time	10102116100 ps
CPU time	43.55 seconds
Started	Aug 13 06:20:12 PM PDT 24
Finished	Aug 13 06:20:56 PM PDT 24
Peak memory	265804 kb
Host	smart-dbc3dbe0-2c2e-4413-be16-56e0d29ba791
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283235231 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.2283235231
Directory	/workspace/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/19.flash_ctrl_hw_read_seed_err.2068948181
Short name	T882
Test name
Test status
Simulation time	15883200 ps
CPU time	13.44 seconds
Started	Aug 13 06:20:03 PM PDT 24
Finished	Aug 13 06:20:16 PM PDT 24
Peak memory	260640 kb
Host	smart-04bcffb3-1372-450b-a6de-eb40aa7fc3f4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068948181 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_read_seed_err.2068948181
Directory	/workspace/19.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/19.flash_ctrl_hw_rma_reset.3335457809
Short name	T829
Test name
Test status
Simulation time	160186008700 ps
CPU time	866.26 seconds
Started	Aug 13 06:19:54 PM PDT 24
Finished	Aug 13 06:34:21 PM PDT 24
Peak memory	264564 kb
Host	smart-50db5466-d7e7-40e2-8eec-3c3b9921b17c
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335457809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 19.flash_ctrl_hw_rma_reset.3335457809
Directory	/workspace/19.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/19.flash_ctrl_hw_sec_otp.1787997479
Short name	T100
Test name
Test status
Simulation time	3364708000 ps
CPU time	257.96 seconds
Started	Aug 13 06:19:56 PM PDT 24
Finished	Aug 13 06:24:14 PM PDT 24
Peak memory	263676 kb
Host	smart-382f8886-6391-43bf-9aae-33c673cfeb10
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787997479 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_ hw_sec_otp.1787997479
Directory	/workspace/19.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/19.flash_ctrl_intr_rd.2264769451
Short name	T322
Test name
Test status
Simulation time	721169900 ps
CPU time	179.99 seconds
Started	Aug 13 06:20:04 PM PDT 24
Finished	Aug 13 06:23:04 PM PDT 24
Peak memory	296104 kb
Host	smart-87a9cc71-5fd6-4961-b7ab-c2e24d649b94
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264769451 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla sh_ctrl_intr_rd.2264769451
Directory	/workspace/19.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/19.flash_ctrl_intr_rd_slow_flash.3344471958
Short name	T570
Test name
Test status
Simulation time	6095315200 ps
CPU time	153.23 seconds
Started	Aug 13 06:20:03 PM PDT 24
Finished	Aug 13 06:22:37 PM PDT 24
Peak memory	294688 kb
Host	smart-7eb77f82-0312-401e-ae34-79e4d4ee26a6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344471958 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd_slow_flash.3344471958
Directory	/workspace/19.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/19.flash_ctrl_invalid_op.3538524934
Short name	T457
Test name
Test status
Simulation time	4345711400 ps
CPU time	68.25 seconds
Started	Aug 13 06:19:55 PM PDT 24
Finished	Aug 13 06:21:04 PM PDT 24
Peak memory	264240 kb
Host	smart-cca449c8-e617-4087-b1e0-7ca336ea703b
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538524934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.3 538524934
Directory	/workspace/19.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/19.flash_ctrl_lcmgr_intg.1527908514
Short name	T905
Test name
Test status
Simulation time	34235100 ps
CPU time	13.68 seconds
Started	Aug 13 06:20:07 PM PDT 24
Finished	Aug 13 06:20:20 PM PDT 24
Peak memory	265380 kb
Host	smart-eff8920b-f369-4a56-bc99-f09ca91ff857
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527908514 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 19.flash_ctrl_lcmgr_intg.1527908514
Directory	/workspace/19.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/19.flash_ctrl_mp_regions.3900107711
Short name	T390
Test name
Test status
Simulation time	5934634800 ps
CPU time	166.67 seconds
Started	Aug 13 06:19:56 PM PDT 24
Finished	Aug 13 06:22:43 PM PDT 24
Peak memory	264332 kb
Host	smart-d86e1aea-ebda-489a-8898-9f045a33f982
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900107711 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_mp_regions.3900107711
Directory	/workspace/19.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/19.flash_ctrl_otp_reset.3208536093
Short name	T801
Test name
Test status
Simulation time	38874300 ps
CPU time	108.47 seconds
Started	Aug 13 06:19:54 PM PDT 24
Finished	Aug 13 06:21:43 PM PDT 24
Peak memory	259360 kb
Host	smart-6a160eb0-42c7-47a5-b5f3-7819ae011399
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208536093 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_o tp_reset.3208536093
Directory	/workspace/19.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/19.flash_ctrl_phy_arb.3988373597
Short name	T764
Test name
Test status
Simulation time	292475200 ps
CPU time	409.43 seconds
Started	Aug 13 06:19:56 PM PDT 24
Finished	Aug 13 06:26:46 PM PDT 24
Peak memory	263644 kb
Host	smart-e9c650c7-27b6-4f75-92d4-e28f73577daa
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3988373597 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.3988373597
Directory	/workspace/19.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/19.flash_ctrl_prog_reset.1692378340
Short name	T799
Test name
Test status
Simulation time	46325700 ps
CPU time	13.84 seconds
Started	Aug 13 06:20:04 PM PDT 24
Finished	Aug 13 06:20:18 PM PDT 24
Peak memory	260000 kb
Host	smart-7ff82b71-590b-4232-9f4b-ba6ab657d5e1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692378340 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 19.flash_ctrl_prog_reset.1692378340
Directory	/workspace/19.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/19.flash_ctrl_rand_ops.1800947262
Short name	T835
Test name
Test status
Simulation time	179122300 ps
CPU time	323.09 seconds
Started	Aug 13 06:19:53 PM PDT 24
Finished	Aug 13 06:25:16 PM PDT 24
Peak memory	282020 kb
Host	smart-2006bdb1-2831-4056-b3ba-1db6f889955f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1800947262 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.1800947262
Directory	/workspace/19.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/19.flash_ctrl_re_evict.2056098374
Short name	T134
Test name
Test status
Simulation time	120360600 ps
CPU time	34.31 seconds
Started	Aug 13 06:20:04 PM PDT 24
Finished	Aug 13 06:20:38 PM PDT 24
Peak memory	268100 kb
Host	smart-a4519585-a5cc-4274-9d52-38162d7ce294
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056098374 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl ash_ctrl_re_evict.2056098374
Directory	/workspace/19.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/19.flash_ctrl_ro.4074779865
Short name	T226
Test name
Test status
Simulation time	586862700 ps
CPU time	142.86 seconds
Started	Aug 13 06:20:05 PM PDT 24
Finished	Aug 13 06:22:28 PM PDT 24
Peak memory	290596 kb
Host	smart-d2f39e57-b9c8-40e1-9326-6701820cf60d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074779865 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 19.flash_ctrl_ro.4074779865
Directory	/workspace/19.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/19.flash_ctrl_rw.2568715209
Short name	T644
Test name
Test status
Simulation time	18230674600 ps
CPU time	561.04 seconds
Started	Aug 13 06:20:03 PM PDT 24
Finished	Aug 13 06:29:24 PM PDT 24
Peak memory	315060 kb
Host	smart-7415117b-6f1d-4f2c-bad7-b18b71e21b01
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568715209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 19.flash_ctrl_rw.2568715209
Directory	/workspace/19.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/19.flash_ctrl_rw_evict.1713491716
Short name	T747
Test name
Test status
Simulation time	67951600 ps
CPU time	29.25 seconds
Started	Aug 13 06:20:04 PM PDT 24
Finished	Aug 13 06:20:33 PM PDT 24
Peak memory	276192 kb
Host	smart-34e4266f-5b9d-4c14-b738-9fb375a60783
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713491716 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.fl ash_ctrl_rw_evict.1713491716
Directory	/workspace/19.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/19.flash_ctrl_rw_evict_all_en.3201024317
Short name	T900
Test name
Test status
Simulation time	43606700 ps
CPU time	30.71 seconds
Started	Aug 13 06:20:04 PM PDT 24
Finished	Aug 13 06:20:35 PM PDT 24
Peak memory	274192 kb
Host	smart-130f3b89-385e-4547-9eaa-5843fe61309b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201024317 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict_all_en.3201024317
Directory	/workspace/19.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/19.flash_ctrl_sec_info_access.2584162912
Short name	T753
Test name
Test status
Simulation time	21455462700 ps
CPU time	87.5 seconds
Started	Aug 13 06:20:04 PM PDT 24
Finished	Aug 13 06:21:32 PM PDT 24
Peak memory	264316 kb
Host	smart-663ee22e-8684-4409-ba42-f72ac4dbce1f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2584162912 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.2584162912
Directory	/workspace/19.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/19.flash_ctrl_smoke.2486902475
Short name	T576
Test name
Test status
Simulation time	34181800 ps
CPU time	124.71 seconds
Started	Aug 13 06:19:56 PM PDT 24
Finished	Aug 13 06:22:01 PM PDT 24
Peak memory	278084 kb
Host	smart-39a42d65-6f6e-418b-bd3d-9d27bd775e2f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2486902475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.2486902475
Directory	/workspace/19.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/19.flash_ctrl_wo.3928198635
Short name	T1107
Test name
Test status
Simulation time	12694666800 ps
CPU time	203.16 seconds
Started	Aug 13 06:19:56 PM PDT 24
Finished	Aug 13 06:23:19 PM PDT 24
Peak memory	259988 kb
Host	smart-6c7aade1-88d5-4e08-987f-04a205fd9185
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928198635 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 19.flash_ctrl_wo.3928198635
Directory	/workspace/19.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/2.flash_ctrl_alert_test.1385820534
Short name	T965
Test name
Test status
Simulation time	146538500 ps
CPU time	13.53 seconds
Started	Aug 13 06:15:32 PM PDT 24
Finished	Aug 13 06:15:45 PM PDT 24
Peak memory	258692 kb
Host	smart-99b4613b-efcb-4e4d-ad95-2db12287f368
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385820534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.1 385820534
Directory	/workspace/2.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/2.flash_ctrl_config_regwen.1640610799
Short name	T259
Test name
Test status
Simulation time	23316700 ps
CPU time	13.78 seconds
Started	Aug 13 06:15:35 PM PDT 24
Finished	Aug 13 06:15:49 PM PDT 24
Peak memory	265412 kb
Host	smart-edc185b5-4869-4d3f-b938-819b35897af0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640610799 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .flash_ctrl_config_regwen.1640610799
Directory	/workspace/2.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/2.flash_ctrl_connect.1733745535
Short name	T739
Test name
Test status
Simulation time	16367600 ps
CPU time	13.26 seconds
Started	Aug 13 06:15:24 PM PDT 24
Finished	Aug 13 06:15:37 PM PDT 24
Peak memory	284752 kb
Host	smart-e09784ee-cc85-4120-ad2d-0e26f42c1a2a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1733745535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.1733745535
Directory	/workspace/2.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/2.flash_ctrl_derr_detect.2152512259
Short name	T620
Test name
Test status
Simulation time	903266700 ps
CPU time	202.45 seconds
Started	Aug 13 06:15:16 PM PDT 24
Finished	Aug 13 06:18:38 PM PDT 24
Peak memory	278432 kb
Host	smart-28b1ff81-3168-4b82-8030-ebca02927d22
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152512259 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_derr_detect.2152512259
Directory	/workspace/2.flash_ctrl_derr_detect/latest

Test location	/workspace/coverage/default/2.flash_ctrl_disable.2574314623
Short name	T830
Test name
Test status
Simulation time	10246100 ps
CPU time	21.82 seconds
Started	Aug 13 06:15:27 PM PDT 24
Finished	Aug 13 06:15:48 PM PDT 24
Peak memory	274100 kb
Host	smart-83d6602d-77b1-42cd-afc3-8e6780411823
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574314623 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_disable.2574314623
Directory	/workspace/2.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/2.flash_ctrl_erase_suspend.1635342979
Short name	T833
Test name
Test status
Simulation time	7643076700 ps
CPU time	559.29 seconds
Started	Aug 13 06:15:07 PM PDT 24
Finished	Aug 13 06:24:26 PM PDT 24
Peak memory	263828 kb
Host	smart-5c870f69-0a40-4e76-bb6b-7f8042835479
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1635342979 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.1635342979
Directory	/workspace/2.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/2.flash_ctrl_error_mp.2465182357
Short name	T818
Test name
Test status
Simulation time	112345589700 ps
CPU time	2604.95 seconds
Started	Aug 13 06:15:04 PM PDT 24
Finished	Aug 13 06:58:30 PM PDT 24
Peak memory	265316 kb
Host	smart-9c47a760-d19b-4d4c-8492-2a2140cc7d02
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2465182357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_mp.2465182357
Directory	/workspace/2.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/2.flash_ctrl_error_prog_type.1883473092
Short name	T83
Test name
Test status
Simulation time	2973329300 ps
CPU time	2103.1 seconds
Started	Aug 13 06:15:09 PM PDT 24
Finished	Aug 13 06:50:12 PM PDT 24
Peak memory	265808 kb
Host	smart-f3678507-26f6-4054-9039-f438bad51613
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883473092 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.flash_ctrl_error_prog_type.1883473092
Directory	/workspace/2.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/2.flash_ctrl_error_prog_win.499943758
Short name	T1029
Test name
Test status
Simulation time	1747057100 ps
CPU time	952.45 seconds
Started	Aug 13 06:15:08 PM PDT 24
Finished	Aug 13 06:31:01 PM PDT 24
Peak memory	273876 kb
Host	smart-87efcea7-950d-42fc-a965-0e811b9e0777
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=499943758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.499943758
Directory	/workspace/2.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/2.flash_ctrl_fetch_code.3463588006
Short name	T968
Test name
Test status
Simulation time	394134300 ps
CPU time	21.25 seconds
Started	Aug 13 06:15:06 PM PDT 24
Finished	Aug 13 06:15:27 PM PDT 24
Peak memory	263036 kb
Host	smart-fb5cbe09-f480-4620-bd6c-82b7564c0365
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463588006 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetch_code.3463588006
Directory	/workspace/2.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/2.flash_ctrl_fs_sup.667721613
Short name	T280
Test name
Test status
Simulation time	636113000 ps
CPU time	38.83 seconds
Started	Aug 13 06:15:35 PM PDT 24
Finished	Aug 13 06:16:14 PM PDT 24
Peak memory	263000 kb
Host	smart-0988c1f0-ba8e-4041-a669-c0b25ba6c535
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667721613 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base _test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.flash_ctrl_fs_sup.667721613
Directory	/workspace/2.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/default/2.flash_ctrl_full_mem_access.739576583
Short name	T139
Test name
Test status
Simulation time	78248281500 ps
CPU time	2440.75 seconds
Started	Aug 13 06:15:04 PM PDT 24
Finished	Aug 13 06:55:45 PM PDT 24
Peak memory	263716 kb
Host	smart-ceee8407-e8ad-4337-a4e4-6f16aefd8296
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739576583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ct rl_full_mem_access.739576583
Directory	/workspace/2.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/2.flash_ctrl_host_addr_infection.241085947
Short name	T1026
Test name
Test status
Simulation time	40347100 ps
CPU time	30.23 seconds
Started	Aug 13 06:15:34 PM PDT 24
Finished	Aug 13 06:16:05 PM PDT 24
Peak memory	276132 kb
Host	smart-b4f8a442-313e-47c1-be78-0367e9297d2b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241085947 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_t est +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.flash_ctrl_host_addr_infection.241085947
Directory	/workspace/2.flash_ctrl_host_addr_infection/latest

Test location	/workspace/coverage/default/2.flash_ctrl_host_dir_rd.1307548907
Short name	T281
Test name
Test status
Simulation time	300527400 ps
CPU time	102.4 seconds
Started	Aug 13 06:15:08 PM PDT 24
Finished	Aug 13 06:16:51 PM PDT 24
Peak memory	263284 kb
Host	smart-36ccc208-375a-44f1-85ad-959f2e035296
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1307548907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.1307548907
Directory	/workspace/2.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.3969416566
Short name	T195
Test name
Test status
Simulation time	10021414200 ps
CPU time	77.25 seconds
Started	Aug 13 06:15:36 PM PDT 24
Finished	Aug 13 06:16:53 PM PDT 24
Peak memory	307176 kb
Host	smart-dda889cf-85cf-4c8b-8828-56e9bb9efbfe
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969416566 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.3969416566
Directory	/workspace/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_read_seed_err.4145934410
Short name	T1037
Test name
Test status
Simulation time	15093600 ps
CPU time	13.51 seconds
Started	Aug 13 06:15:35 PM PDT 24
Finished	Aug 13 06:15:48 PM PDT 24
Peak memory	258960 kb
Host	smart-155fe483-43bd-419c-9dcd-d0c3d01aa74f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145934410 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_read_seed_err.4145934410
Directory	/workspace/2.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_rma.4035997486
Short name	T716
Test name
Test status
Simulation time	167433671400 ps
CPU time	1915.8 seconds
Started	Aug 13 06:15:06 PM PDT 24
Finished	Aug 13 06:47:02 PM PDT 24
Peak memory	261320 kb
Host	smart-e76ea9fe-2208-4209-a6d7-6241549e59af
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035997486 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.flash_ctrl_hw_rma.4035997486
Directory	/workspace/2.flash_ctrl_hw_rma/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_rma_reset.3079693109
Short name	T489
Test name
Test status
Simulation time	80149473100 ps
CPU time	853.74 seconds
Started	Aug 13 06:15:07 PM PDT 24
Finished	Aug 13 06:29:21 PM PDT 24
Peak memory	261288 kb
Host	smart-af672166-b6bd-4ee9-bd83-50ec00a403c6
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079693109 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.flash_ctrl_hw_rma_reset.3079693109
Directory	/workspace/2.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/2.flash_ctrl_hw_sec_otp.703495679
Short name	T547
Test name
Test status
Simulation time	3288259800 ps
CPU time	65.58 seconds
Started	Aug 13 06:15:06 PM PDT 24
Finished	Aug 13 06:16:11 PM PDT 24
Peak memory	263808 kb
Host	smart-e748cadc-1baa-461a-bea5-c733f33aac52
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703495679 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw _sec_otp.703495679
Directory	/workspace/2.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/2.flash_ctrl_integrity.2216277596
Short name	T948
Test name
Test status
Simulation time	4264417900 ps
CPU time	494.77 seconds
Started	Aug 13 06:15:14 PM PDT 24
Finished	Aug 13 06:23:29 PM PDT 24
Peak memory	318420 kb
Host	smart-13e4887a-7772-4840-8089-02e625d949a4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216277596 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.flash_ctrl_integrity.2216277596
Directory	/workspace/2.flash_ctrl_integrity/latest

Test location	/workspace/coverage/default/2.flash_ctrl_intr_rd.470346902
Short name	T861
Test name
Test status
Simulation time	3146528200 ps
CPU time	136.21 seconds
Started	Aug 13 06:15:15 PM PDT 24
Finished	Aug 13 06:17:31 PM PDT 24
Peak memory	294956 kb
Host	smart-48a4348f-241c-4f0f-9b09-74f3c458db1a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470346902 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash _ctrl_intr_rd.470346902
Directory	/workspace/2.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/2.flash_ctrl_intr_rd_slow_flash.943948043
Short name	T981
Test name
Test status
Simulation time	5827293200 ps
CPU time	163.63 seconds
Started	Aug 13 06:15:16 PM PDT 24
Finished	Aug 13 06:17:59 PM PDT 24
Peak memory	290540 kb
Host	smart-7d8611ee-2fb0-4c80-b636-65242ed28846
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943948043 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd_slow_flash.943948043
Directory	/workspace/2.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/2.flash_ctrl_intr_wr.3653126552
Short name	T615
Test name
Test status
Simulation time	7318201000 ps
CPU time	68.08 seconds
Started	Aug 13 06:15:16 PM PDT 24
Finished	Aug 13 06:16:24 PM PDT 24
Peak memory	260592 kb
Host	smart-190d02ce-fea1-43c1-a4b7-b362b9345185
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653126552 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.flash_ctrl_intr_wr.3653126552
Directory	/workspace/2.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_intr_wr_slow_flash.3186680926
Short name	T18
Test name
Test status
Simulation time	22565994700 ps
CPU time	181.52 seconds
Started	Aug 13 06:15:22 PM PDT 24
Finished	Aug 13 06:18:24 PM PDT 24
Peak memory	260280 kb
Host	smart-afa65291-70c5-4b6f-a8e2-5a6ec1173ba9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318 6680926 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.3186680926
Directory	/workspace/2.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/2.flash_ctrl_invalid_op.2403175425
Short name	T150
Test name
Test status
Simulation time	8329451700 ps
CPU time	66.83 seconds
Started	Aug 13 06:15:09 PM PDT 24
Finished	Aug 13 06:16:16 PM PDT 24
Peak memory	261200 kb
Host	smart-9796bc0a-027f-4641-adbd-1e07f256bb73
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403175425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.2403175425
Directory	/workspace/2.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/2.flash_ctrl_lcmgr_intg.3440291334
Short name	T10
Test name
Test status
Simulation time	46200100 ps
CPU time	13.47 seconds
Started	Aug 13 06:15:36 PM PDT 24
Finished	Aug 13 06:15:50 PM PDT 24
Peak memory	265248 kb
Host	smart-89509c52-3987-42d9-b428-e3923811cc3a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440291334 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 2.flash_ctrl_lcmgr_intg.3440291334
Directory	/workspace/2.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/2.flash_ctrl_mid_op_rst.3205888239
Short name	T166
Test name
Test status
Simulation time	1058783900 ps
CPU time	69.5 seconds
Started	Aug 13 06:15:07 PM PDT 24
Finished	Aug 13 06:16:16 PM PDT 24
Peak memory	261156 kb
Host	smart-7d0a38f0-e1b9-4bba-bdd5-65b5bc1fd413
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3205888239 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.3205888239
Directory	/workspace/2.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/2.flash_ctrl_mp_regions.2628474468
Short name	T118
Test name
Test status
Simulation time	21141774000 ps
CPU time	820.02 seconds
Started	Aug 13 06:15:06 PM PDT 24
Finished	Aug 13 06:28:46 PM PDT 24
Peak memory	275104 kb
Host	smart-a9918758-e6f0-440d-a9f1-d8b5635d0e4f
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628474468 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mp_regions.2628474468
Directory	/workspace/2.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/2.flash_ctrl_otp_reset.4046155654
Short name	T709
Test name
Test status
Simulation time	118183500 ps
CPU time	111.07 seconds
Started	Aug 13 06:15:07 PM PDT 24
Finished	Aug 13 06:16:58 PM PDT 24
Peak memory	265548 kb
Host	smart-29a4bf90-8709-40a9-aa19-48f3774135b9
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046155654 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ot p_reset.4046155654
Directory	/workspace/2.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/2.flash_ctrl_oversize_error.4243974293
Short name	T1066
Test name
Test status
Simulation time	7344382200 ps
CPU time	178.95 seconds
Started	Aug 13 06:15:14 PM PDT 24
Finished	Aug 13 06:18:13 PM PDT 24
Peak memory	282396 kb
Host	smart-e025d0bd-8cb3-43d9-a43f-bbbbff62e3b2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243974293 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_oversize_error.4243974293
Directory	/workspace/2.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/2.flash_ctrl_phy_arb.3004227617
Short name	T584
Test name
Test status
Simulation time	774994700 ps
CPU time	503.1 seconds
Started	Aug 13 06:15:09 PM PDT 24
Finished	Aug 13 06:23:32 PM PDT 24
Peak memory	263652 kb
Host	smart-97d99389-1f8d-46e9-975f-2e7a4b59414f
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3004227617 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.3004227617
Directory	/workspace/2.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/2.flash_ctrl_prog_reset.1654535468
Short name	T603
Test name
Test status
Simulation time	20207400 ps
CPU time	13.59 seconds
Started	Aug 13 06:15:24 PM PDT 24
Finished	Aug 13 06:15:38 PM PDT 24
Peak memory	259528 kb
Host	smart-480f7343-b7ba-4cb7-ab95-fe42c38b94d4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654535468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 2.flash_ctrl_prog_reset.1654535468
Directory	/workspace/2.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rand_ops.1452084332
Short name	T152
Test name
Test status
Simulation time	346178000 ps
CPU time	868.34 seconds
Started	Aug 13 06:15:05 PM PDT 24
Finished	Aug 13 06:29:34 PM PDT 24
Peak memory	283304 kb
Host	smart-ce8b1ee0-c9cb-4c8c-8997-43eef5311d30
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1452084332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.1452084332
Directory	/workspace/2.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rd_buff_evict.1023853053
Short name	T16
Test name
Test status
Simulation time	273588900 ps
CPU time	101.03 seconds
Started	Aug 13 06:15:06 PM PDT 24
Finished	Aug 13 06:16:47 PM PDT 24
Peak memory	263172 kb
Host	smart-1e53765c-21c3-4c4a-864b-3eb70e410ff5
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1023853053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.1023853053
Directory	/workspace/2.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rd_intg.4050125308
Short name	T1108
Test name
Test status
Simulation time	66010200 ps
CPU time	31.17 seconds
Started	Aug 13 06:15:23 PM PDT 24
Finished	Aug 13 06:15:55 PM PDT 24
Peak memory	276148 kb
Host	smart-d7614a8a-3dff-4965-a65c-1b03a03f896b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050125308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_ test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.flash_ctrl_rd_intg.4050125308
Directory	/workspace/2.flash_ctrl_rd_intg/latest

Test location	/workspace/coverage/default/2.flash_ctrl_re_evict.620824042
Short name	T395
Test name
Test status
Simulation time	353612800 ps
CPU time	34.39 seconds
Started	Aug 13 06:15:25 PM PDT 24
Finished	Aug 13 06:15:59 PM PDT 24
Peak memory	276544 kb
Host	smart-fe1f5e92-6d1f-4859-bcba-2e57f631d54b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620824042 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas h_ctrl_re_evict.620824042
Directory	/workspace/2.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/2.flash_ctrl_read_word_sweep_derr.804605208
Short name	T795
Test name
Test status
Simulation time	57886000 ps
CPU time	22.95 seconds
Started	Aug 13 06:15:14 PM PDT 24
Finished	Aug 13 06:15:37 PM PDT 24
Peak memory	265584 kb
Host	smart-783615b0-db25-4e93-9f4d-ae21852e37bd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804605208 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_derr.804605208
Directory	/workspace/2.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_read_word_sweep_serr.2304106157
Short name	T611
Test name
Test status
Simulation time	40245900 ps
CPU time	22.66 seconds
Started	Aug 13 06:15:17 PM PDT 24
Finished	Aug 13 06:15:40 PM PDT 24
Peak memory	265896 kb
Host	smart-d85726e3-ca32-44a2-856b-9c8179b9361a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304106157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.fl ash_ctrl_read_word_sweep_serr.2304106157
Directory	/workspace/2.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rma_err.2256672182
Short name	T187
Test name
Test status
Simulation time	174696137500 ps
CPU time	958.59 seconds
Started	Aug 13 06:15:36 PM PDT 24
Finished	Aug 13 06:31:35 PM PDT 24
Peak memory	261976 kb
Host	smart-fa6e7cb9-fb08-4da2-a77f-99fa4a328735
User	root
Command	/workspace/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256672182 -assert nopostproc +UVM_TES TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rma_err.2256672182
Directory	/workspace/2.flash_ctrl_rma_err/latest

Test location	/workspace/coverage/default/2.flash_ctrl_ro.2300479408
Short name	T678
Test name
Test status
Simulation time	2005660600 ps
CPU time	105.6 seconds
Started	Aug 13 06:15:08 PM PDT 24
Finished	Aug 13 06:16:53 PM PDT 24
Peak memory	282332 kb
Host	smart-b79c762c-9024-47e0-aca6-89947ede2434
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300479408 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.flash_ctrl_ro.2300479408
Directory	/workspace/2.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/2.flash_ctrl_ro_derr.4242825479
Short name	T227
Test name
Test status
Simulation time	606801600 ps
CPU time	132.47 seconds
Started	Aug 13 06:15:13 PM PDT 24
Finished	Aug 13 06:17:25 PM PDT 24
Peak memory	282372 kb
Host	smart-5e9e265d-fdbd-4f4c-952d-7ec2ac938f64
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4242825479 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.4242825479
Directory	/workspace/2.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_ro_serr.523059953
Short name	T29
Test name
Test status
Simulation time	2799538500 ps
CPU time	146.75 seconds
Started	Aug 13 06:15:15 PM PDT 24
Finished	Aug 13 06:17:42 PM PDT 24
Peak memory	293684 kb
Host	smart-27b07e15-3103-4dab-ac51-50c3343aeebb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523059953 -assert nopostproc +UVM_T ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.flash_ctrl_ro_serr.523059953
Directory	/workspace/2.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rw.371049789
Short name	T703
Test name
Test status
Simulation time	46641725700 ps
CPU time	496.07 seconds
Started	Aug 13 06:15:16 PM PDT 24
Finished	Aug 13 06:23:32 PM PDT 24
Peak memory	310560 kb
Host	smart-2df73e62-7e63-4691-bf35-cc9fe48a01b2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371049789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw.371049789
Directory	/workspace/2.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/2.flash_ctrl_rw_derr.4136093539
Short name	T937
Test name
Test status
Simulation time	5975872400 ps
CPU time	205.2 seconds
Started	Aug 13 06:15:17 PM PDT 24
Finished	Aug 13 06:18:42 PM PDT 24
Peak memory	291092 kb
Host	smart-48bb01ed-9b6f-466b-864c-54dcfedc2188
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136093539 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_derr.4136093539
Directory	/workspace/2.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/2.flash_ctrl_sec_cm.1346182284
Short name	T33
Test name
Test status
Simulation time	2188473200 ps
CPU time	4988.59 seconds
Started	Aug 13 06:15:25 PM PDT 24
Finished	Aug 13 07:38:34 PM PDT 24
Peak memory	284776 kb
Host	smart-454485b2-0512-4243-a7a1-736250a201da
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346182284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.1346182284
Directory	/workspace/2.flash_ctrl_sec_cm/latest

Test location	/workspace/coverage/default/2.flash_ctrl_sec_info_access.682780201
Short name	T646
Test name
Test status
Simulation time	5175207100 ps
CPU time	71.48 seconds
Started	Aug 13 06:15:27 PM PDT 24
Finished	Aug 13 06:16:38 PM PDT 24
Peak memory	264264 kb
Host	smart-b1f7a48d-4abe-4d21-9a1d-c8e8500ab238
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=682780201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.682780201
Directory	/workspace/2.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/2.flash_ctrl_serr_address.3246644508
Short name	T823
Test name
Test status
Simulation time	3507806400 ps
CPU time	81.05 seconds
Started	Aug 13 06:15:12 PM PDT 24
Finished	Aug 13 06:16:34 PM PDT 24
Peak memory	274188 kb
Host	smart-0c08c70f-1178-4358-bc85-638f893e5d57
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246644508 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.flash_ctrl_serr_address.3246644508
Directory	/workspace/2.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/2.flash_ctrl_serr_counter.918666146
Short name	T800
Test name
Test status
Simulation time	799903200 ps
CPU time	88.53 seconds
Started	Aug 13 06:15:15 PM PDT 24
Finished	Aug 13 06:16:43 PM PDT 24
Peak memory	274192 kb
Host	smart-81c6c046-914a-4dfe-bbbe-d20fd41d337d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918666146 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.flash_ctrl_serr_counter.918666146
Directory	/workspace/2.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/2.flash_ctrl_smoke.3854134201
Short name	T991
Test name
Test status
Simulation time	31871700 ps
CPU time	123.58 seconds
Started	Aug 13 06:14:58 PM PDT 24
Finished	Aug 13 06:17:02 PM PDT 24
Peak memory	277888 kb
Host	smart-30483116-8580-473e-b083-f7874ee8c0e9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3854134201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.3854134201
Directory	/workspace/2.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/2.flash_ctrl_smoke_hw.1329280984
Short name	T451
Test name
Test status
Simulation time	46301300 ps
CPU time	25.86 seconds
Started	Aug 13 06:14:58 PM PDT 24
Finished	Aug 13 06:15:24 PM PDT 24
Peak memory	260156 kb
Host	smart-2cc32e4e-dae0-4603-aefd-61006cbfb5e8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1329280984 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.1329280984
Directory	/workspace/2.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/2.flash_ctrl_stress_all.436052676
Short name	T464
Test name
Test status
Simulation time	82862600 ps
CPU time	355.9 seconds
Started	Aug 13 06:15:24 PM PDT 24
Finished	Aug 13 06:21:20 PM PDT 24
Peak memory	281180 kb
Host	smart-ea83c48f-2409-4d57-a3b3-8a9963c131ce
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436052676 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_st ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stress _all.436052676
Directory	/workspace/2.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/2.flash_ctrl_sw_op.3970190818
Short name	T580
Test name
Test status
Simulation time	312011100 ps
CPU time	26.5 seconds
Started	Aug 13 06:15:07 PM PDT 24
Finished	Aug 13 06:15:33 PM PDT 24
Peak memory	260260 kb
Host	smart-ef28016e-39c8-402e-b613-ee9b435a948b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3970190818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.3970190818
Directory	/workspace/2.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/2.flash_ctrl_wo.1749493564
Short name	T1090
Test name
Test status
Simulation time	2643691000 ps
CPU time	215.65 seconds
Started	Aug 13 06:15:08 PM PDT 24
Finished	Aug 13 06:18:44 PM PDT 24
Peak memory	261684 kb
Host	smart-bc6efb6a-0ae2-4d8c-9fab-0b770f68941d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749493564 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.flash_ctrl_wo.1749493564
Directory	/workspace/2.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/2.flash_ctrl_wr_intg.3209396381
Short name	T261
Test name
Test status
Simulation time	45924100 ps
CPU time	14.96 seconds
Started	Aug 13 06:15:26 PM PDT 24
Finished	Aug 13 06:15:41 PM PDT 24
Peak memory	261416 kb
Host	smart-4c8dc11a-4998-4f7d-b10e-179a221bf040
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_prog=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209396381 -assert nopostproc +UV M_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wr_intg.3209396381
Directory	/workspace/2.flash_ctrl_wr_intg/latest

Test location	/workspace/coverage/default/20.flash_ctrl_alert_test.3361419430
Short name	T690
Test name
Test status
Simulation time	55316800 ps
CPU time	13.61 seconds
Started	Aug 13 06:20:12 PM PDT 24
Finished	Aug 13 06:20:25 PM PDT 24
Peak memory	265732 kb
Host	smart-5b679e42-047b-46ad-922b-44465bf73dea
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361419430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test. 3361419430
Directory	/workspace/20.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/20.flash_ctrl_connect.3748537660
Short name	T444
Test name
Test status
Simulation time	46895800 ps
CPU time	15.95 seconds
Started	Aug 13 06:20:13 PM PDT 24
Finished	Aug 13 06:20:29 PM PDT 24
Peak memory	284836 kb
Host	smart-a6e4cb02-bcf9-46c5-91a5-c740024c389f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3748537660 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.3748537660
Directory	/workspace/20.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/20.flash_ctrl_disable.3404743638
Short name	T831
Test name
Test status
Simulation time	14614400 ps
CPU time	21.83 seconds
Started	Aug 13 06:20:12 PM PDT 24
Finished	Aug 13 06:20:34 PM PDT 24
Peak memory	274172 kb
Host	smart-43bad364-7472-4e2f-be24-d9d27ed348aa
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404743638 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_disable.3404743638
Directory	/workspace/20.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/20.flash_ctrl_hw_sec_otp.2041567626
Short name	T712
Test name
Test status
Simulation time	37636286500 ps
CPU time	126.75 seconds
Started	Aug 13 06:20:13 PM PDT 24
Finished	Aug 13 06:22:20 PM PDT 24
Peak memory	263848 kb
Host	smart-5ac007a8-734f-4365-90d0-5bc6e50903c4
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041567626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_ hw_sec_otp.2041567626
Directory	/workspace/20.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/20.flash_ctrl_intr_rd_slow_flash.729200884
Short name	T476
Test name
Test status
Simulation time	24774993500 ps
CPU time	323.78 seconds
Started	Aug 13 06:20:12 PM PDT 24
Finished	Aug 13 06:25:36 PM PDT 24
Peak memory	285764 kb
Host	smart-9e224548-6aaa-4701-bee3-8c67df90c539
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729200884 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd_slow_flash.729200884
Directory	/workspace/20.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/20.flash_ctrl_otp_reset.717691420
Short name	T848
Test name
Test status
Simulation time	38877900 ps
CPU time	135.56 seconds
Started	Aug 13 06:20:10 PM PDT 24
Finished	Aug 13 06:22:26 PM PDT 24
Peak memory	265700 kb
Host	smart-912f038b-6b2b-4473-ad3f-4a3eede67fa5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717691420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_ot p_reset.717691420
Directory	/workspace/20.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/20.flash_ctrl_prog_reset.3907470720
Short name	T814
Test name
Test status
Simulation time	75906000 ps
CPU time	13.53 seconds
Started	Aug 13 06:20:12 PM PDT 24
Finished	Aug 13 06:20:25 PM PDT 24
Peak memory	259420 kb
Host	smart-0004d1f5-13fb-4c86-a9dd-c5f7baac3a8d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907470720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 20.flash_ctrl_prog_reset.3907470720
Directory	/workspace/20.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/20.flash_ctrl_rw_evict_all_en.1983912209
Short name	T125
Test name
Test status
Simulation time	43890600 ps
CPU time	31.35 seconds
Started	Aug 13 06:20:12 PM PDT 24
Finished	Aug 13 06:20:44 PM PDT 24
Peak memory	276260 kb
Host	smart-e692a8f5-8171-44d3-809c-9d05c511fec9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983912209 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict_all_en.1983912209
Directory	/workspace/20.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/20.flash_ctrl_sec_info_access.2219462586
Short name	T792
Test name
Test status
Simulation time	6010332000 ps
CPU time	69.45 seconds
Started	Aug 13 06:20:14 PM PDT 24
Finished	Aug 13 06:21:23 PM PDT 24
Peak memory	263664 kb
Host	smart-fa788565-bbfc-484f-8a45-1068030fbbe1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2219462586 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.2219462586
Directory	/workspace/20.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/20.flash_ctrl_smoke.943592336
Short name	T662
Test name
Test status
Simulation time	22311200 ps
CPU time	51.15 seconds
Started	Aug 13 06:20:13 PM PDT 24
Finished	Aug 13 06:21:05 PM PDT 24
Peak memory	271756 kb
Host	smart-c759c9cf-6d51-425f-b77a-746dc5c9667f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=943592336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.943592336
Directory	/workspace/20.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/21.flash_ctrl_alert_test.2657352163
Short name	T461
Test name
Test status
Simulation time	55990300 ps
CPU time	13.81 seconds
Started	Aug 13 06:20:20 PM PDT 24
Finished	Aug 13 06:20:34 PM PDT 24
Peak memory	265728 kb
Host	smart-376de98e-43c7-461f-8e45-fb7b071e98a7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657352163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test. 2657352163
Directory	/workspace/21.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/21.flash_ctrl_connect.1689905031
Short name	T1028
Test name
Test status
Simulation time	37609400 ps
CPU time	15.73 seconds
Started	Aug 13 06:20:21 PM PDT 24
Finished	Aug 13 06:20:36 PM PDT 24
Peak memory	283624 kb
Host	smart-2a829528-5cbc-44f9-ad05-be210be32218
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1689905031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.1689905031
Directory	/workspace/21.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/21.flash_ctrl_disable.404873099
Short name	T623
Test name
Test status
Simulation time	38597200 ps
CPU time	21.22 seconds
Started	Aug 13 06:20:22 PM PDT 24
Finished	Aug 13 06:20:43 PM PDT 24
Peak memory	274076 kb
Host	smart-6e0926b2-25df-44a1-842a-834cf56520bb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404873099 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_disable.404873099
Directory	/workspace/21.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/21.flash_ctrl_hw_sec_otp.2068431623
Short name	T1021
Test name
Test status
Simulation time	2142687800 ps
CPU time	47.33 seconds
Started	Aug 13 06:20:18 PM PDT 24
Finished	Aug 13 06:21:05 PM PDT 24
Peak memory	263816 kb
Host	smart-b065c7d5-9647-4eba-b1ad-e2471d4d0387
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068431623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_ hw_sec_otp.2068431623
Directory	/workspace/21.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/21.flash_ctrl_intr_rd.2271412601
Short name	T590
Test name
Test status
Simulation time	574650000 ps
CPU time	130.08 seconds
Started	Aug 13 06:20:20 PM PDT 24
Finished	Aug 13 06:22:30 PM PDT 24
Peak memory	297276 kb
Host	smart-9da0c9b7-05ae-49c1-b769-fa97032d83b1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271412601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fla sh_ctrl_intr_rd.2271412601
Directory	/workspace/21.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/21.flash_ctrl_intr_rd_slow_flash.3092627231
Short name	T822
Test name
Test status
Simulation time	26082614700 ps
CPU time	283.86 seconds
Started	Aug 13 06:20:21 PM PDT 24
Finished	Aug 13 06:25:05 PM PDT 24
Peak memory	290496 kb
Host	smart-b1b78a26-3275-42dd-8ed4-f96e7b50b422
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092627231 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd_slow_flash.3092627231
Directory	/workspace/21.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/21.flash_ctrl_otp_reset.2542636146
Short name	T653
Test name
Test status
Simulation time	173396900 ps
CPU time	133.47 seconds
Started	Aug 13 06:20:21 PM PDT 24
Finished	Aug 13 06:22:35 PM PDT 24
Peak memory	260596 kb
Host	smart-f122346d-d57b-4432-8cc0-1607a427c1eb
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542636146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_o tp_reset.2542636146
Directory	/workspace/21.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/21.flash_ctrl_prog_reset.1057523371
Short name	T169
Test name
Test status
Simulation time	184023000 ps
CPU time	14.5 seconds
Started	Aug 13 06:20:19 PM PDT 24
Finished	Aug 13 06:20:33 PM PDT 24
Peak memory	265884 kb
Host	smart-4c3d00be-e82a-4cce-82b5-dd91b126bfc8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057523371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 21.flash_ctrl_prog_reset.1057523371
Directory	/workspace/21.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/21.flash_ctrl_rw_evict.3686442312
Short name	T133
Test name
Test status
Simulation time	34567100 ps
CPU time	29.33 seconds
Started	Aug 13 06:20:19 PM PDT 24
Finished	Aug 13 06:20:49 PM PDT 24
Peak memory	276308 kb
Host	smart-3a1ab895-9c98-4617-b604-8f6c5979cfab
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686442312 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.fl ash_ctrl_rw_evict.3686442312
Directory	/workspace/21.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/21.flash_ctrl_sec_info_access.571298702
Short name	T761
Test name
Test status
Simulation time	5378278800 ps
CPU time	67.08 seconds
Started	Aug 13 06:20:21 PM PDT 24
Finished	Aug 13 06:21:28 PM PDT 24
Peak memory	264260 kb
Host	smart-4b3e8e06-65ad-401b-b254-06cba16a1b74
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=571298702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.571298702
Directory	/workspace/21.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/21.flash_ctrl_smoke.3606367296
Short name	T659
Test name
Test status
Simulation time	49608700 ps
CPU time	144.92 seconds
Started	Aug 13 06:20:20 PM PDT 24
Finished	Aug 13 06:22:45 PM PDT 24
Peak memory	279184 kb
Host	smart-b8ab4f3a-d9be-4453-b879-99ec247bf90d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3606367296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.3606367296
Directory	/workspace/21.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/22.flash_ctrl_alert_test.3614835144
Short name	T699
Test name
Test status
Simulation time	206223900 ps
CPU time	13.59 seconds
Started	Aug 13 06:20:27 PM PDT 24
Finished	Aug 13 06:20:40 PM PDT 24
Peak memory	258800 kb
Host	smart-b6b87969-e4bf-4367-8e35-402f8daac44a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614835144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test. 3614835144
Directory	/workspace/22.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/22.flash_ctrl_connect.1111724204
Short name	T533
Test name
Test status
Simulation time	15350400 ps
CPU time	13.41 seconds
Started	Aug 13 06:20:27 PM PDT 24
Finished	Aug 13 06:20:41 PM PDT 24
Peak memory	284684 kb
Host	smart-742fc7ea-dad0-457d-beb9-706e946c7ab2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1111724204 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.1111724204
Directory	/workspace/22.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/22.flash_ctrl_disable.3151976794
Short name	T378
Test name
Test status
Simulation time	10625800 ps
CPU time	22.37 seconds
Started	Aug 13 06:20:27 PM PDT 24
Finished	Aug 13 06:20:49 PM PDT 24
Peak memory	274124 kb
Host	smart-ae89847c-9754-4cf9-8904-fd71e2c6a025
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151976794 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_disable.3151976794
Directory	/workspace/22.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/22.flash_ctrl_hw_sec_otp.1673314477
Short name	T593
Test name
Test status
Simulation time	11950222100 ps
CPU time	252.47 seconds
Started	Aug 13 06:20:20 PM PDT 24
Finished	Aug 13 06:24:33 PM PDT 24
Peak memory	261404 kb
Host	smart-b738ddc4-f7a5-47e4-b662-d424ab30536f
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673314477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_ hw_sec_otp.1673314477
Directory	/workspace/22.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/22.flash_ctrl_intr_rd.1190003490
Short name	T999
Test name
Test status
Simulation time	730530700 ps
CPU time	155.29 seconds
Started	Aug 13 06:20:19 PM PDT 24
Finished	Aug 13 06:22:54 PM PDT 24
Peak memory	294320 kb
Host	smart-0bfeefe0-5efd-487d-8f60-877fd0554d34
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190003490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fla sh_ctrl_intr_rd.1190003490
Directory	/workspace/22.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/22.flash_ctrl_intr_rd_slow_flash.1507634943
Short name	T1007
Test name
Test status
Simulation time	12129010900 ps
CPU time	283.48 seconds
Started	Aug 13 06:20:18 PM PDT 24
Finished	Aug 13 06:25:01 PM PDT 24
Peak memory	291352 kb
Host	smart-07d0e51a-cebf-424c-8beb-901613a1da1a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507634943 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd_slow_flash.1507634943
Directory	/workspace/22.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/22.flash_ctrl_otp_reset.3490954068
Short name	T1099
Test name
Test status
Simulation time	147804800 ps
CPU time	110.29 seconds
Started	Aug 13 06:20:22 PM PDT 24
Finished	Aug 13 06:22:12 PM PDT 24
Peak memory	260616 kb
Host	smart-43968ae4-ed5b-4188-b1d4-25576e080d5d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490954068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_o tp_reset.3490954068
Directory	/workspace/22.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/22.flash_ctrl_prog_reset.3476457528
Short name	T470
Test name
Test status
Simulation time	219140600 ps
CPU time	21.07 seconds
Started	Aug 13 06:20:30 PM PDT 24
Finished	Aug 13 06:20:51 PM PDT 24
Peak memory	265560 kb
Host	smart-e1ef9429-e3c7-4a35-9909-0e842655e70e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476457528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 22.flash_ctrl_prog_reset.3476457528
Directory	/workspace/22.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/22.flash_ctrl_rw_evict.3184916624
Short name	T985
Test name
Test status
Simulation time	66108200 ps
CPU time	31.39 seconds
Started	Aug 13 06:20:27 PM PDT 24
Finished	Aug 13 06:20:58 PM PDT 24
Peak memory	274188 kb
Host	smart-5f7f2d91-32f2-4cf1-8431-84dce820855b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184916624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.fl ash_ctrl_rw_evict.3184916624
Directory	/workspace/22.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/22.flash_ctrl_sec_info_access.949385095
Short name	T726
Test name
Test status
Simulation time	394550700 ps
CPU time	56.23 seconds
Started	Aug 13 06:20:29 PM PDT 24
Finished	Aug 13 06:21:25 PM PDT 24
Peak memory	263728 kb
Host	smart-1737044f-2e14-49fc-93aa-e7eac70785e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=949385095 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.949385095
Directory	/workspace/22.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/22.flash_ctrl_smoke.4070207600
Short name	T959
Test name
Test status
Simulation time	201590000 ps
CPU time	146.89 seconds
Started	Aug 13 06:20:20 PM PDT 24
Finished	Aug 13 06:22:47 PM PDT 24
Peak memory	278880 kb
Host	smart-bac3360c-aa36-40c0-8e84-f659643a2221
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4070207600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.4070207600
Directory	/workspace/22.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/23.flash_ctrl_alert_test.3952761171
Short name	T440
Test name
Test status
Simulation time	54307700 ps
CPU time	14.4 seconds
Started	Aug 13 06:20:27 PM PDT 24
Finished	Aug 13 06:20:41 PM PDT 24
Peak memory	258692 kb
Host	smart-f5cf0afb-00e3-457e-bae4-f0a032128b43
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952761171 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test. 3952761171
Directory	/workspace/23.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/23.flash_ctrl_connect.4180607804
Short name	T41
Test name
Test status
Simulation time	17852600 ps
CPU time	15.77 seconds
Started	Aug 13 06:20:28 PM PDT 24
Finished	Aug 13 06:20:44 PM PDT 24
Peak memory	283552 kb
Host	smart-eeb2ec89-6369-41bc-8b50-62ff4f337059
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4180607804 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.4180607804
Directory	/workspace/23.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/23.flash_ctrl_disable.2255683470
Short name	T1083
Test name
Test status
Simulation time	16778100 ps
CPU time	21.79 seconds
Started	Aug 13 06:20:26 PM PDT 24
Finished	Aug 13 06:20:48 PM PDT 24
Peak memory	274184 kb
Host	smart-137ec170-fa37-45e0-9be6-02bfd891e315
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255683470 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_disable.2255683470
Directory	/workspace/23.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/23.flash_ctrl_hw_sec_otp.62285379
Short name	T252
Test name
Test status
Simulation time	3318736400 ps
CPU time	246.26 seconds
Started	Aug 13 06:20:27 PM PDT 24
Finished	Aug 13 06:24:33 PM PDT 24
Peak memory	261376 kb
Host	smart-94021c6f-7715-4838-b5ca-fdbf5caa8d5f
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62285379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl _hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_hw _sec_otp.62285379
Directory	/workspace/23.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/23.flash_ctrl_intr_rd.2469293535
Short name	T555
Test name
Test status
Simulation time	3498981600 ps
CPU time	214.11 seconds
Started	Aug 13 06:20:27 PM PDT 24
Finished	Aug 13 06:24:02 PM PDT 24
Peak memory	291516 kb
Host	smart-94f763a6-670d-464d-897f-da873d575510
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469293535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fla sh_ctrl_intr_rd.2469293535
Directory	/workspace/23.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.2355348714
Short name	T319
Test name
Test status
Simulation time	119059833500 ps
CPU time	479.23 seconds
Started	Aug 13 06:20:30 PM PDT 24
Finished	Aug 13 06:28:29 PM PDT 24
Peak memory	285496 kb
Host	smart-0a98d27e-f08a-4771-ba6d-a0870c8c2270
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355348714 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd_slow_flash.2355348714
Directory	/workspace/23.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/23.flash_ctrl_otp_reset.951161783
Short name	T599
Test name
Test status
Simulation time	101052000 ps
CPU time	132.96 seconds
Started	Aug 13 06:20:27 PM PDT 24
Finished	Aug 13 06:22:40 PM PDT 24
Peak memory	260736 kb
Host	smart-9c33608a-bc90-4a88-a437-7fe16456ec7a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951161783 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_ot p_reset.951161783
Directory	/workspace/23.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/23.flash_ctrl_prog_reset.1591796303
Short name	T370
Test name
Test status
Simulation time	67341400 ps
CPU time	13.55 seconds
Started	Aug 13 06:20:28 PM PDT 24
Finished	Aug 13 06:20:41 PM PDT 24
Peak memory	259576 kb
Host	smart-322b8ec5-1af4-4a07-9cb4-39d450c9c57b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591796303 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 23.flash_ctrl_prog_reset.1591796303
Directory	/workspace/23.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/23.flash_ctrl_rw_evict.3697558854
Short name	T498
Test name
Test status
Simulation time	29839300 ps
CPU time	31.59 seconds
Started	Aug 13 06:20:28 PM PDT 24
Finished	Aug 13 06:20:59 PM PDT 24
Peak memory	276244 kb
Host	smart-be340fd6-9c8d-4e60-85fb-28dbf45dedce
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697558854 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.fl ash_ctrl_rw_evict.3697558854
Directory	/workspace/23.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/23.flash_ctrl_rw_evict_all_en.2007620164
Short name	T881
Test name
Test status
Simulation time	54652200 ps
CPU time	28.62 seconds
Started	Aug 13 06:20:28 PM PDT 24
Finished	Aug 13 06:20:57 PM PDT 24
Peak memory	276252 kb
Host	smart-f1b7a463-8987-44ad-ad8c-c66d0ad473ef
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007620164 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict_all_en.2007620164
Directory	/workspace/23.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/23.flash_ctrl_smoke.2915380302
Short name	T592
Test name
Test status
Simulation time	68412500 ps
CPU time	76.5 seconds
Started	Aug 13 06:20:30 PM PDT 24
Finished	Aug 13 06:21:47 PM PDT 24
Peak memory	277040 kb
Host	smart-7ddc3e74-6acf-4d9d-9b23-06f9a0c7a107
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2915380302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.2915380302
Directory	/workspace/23.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/24.flash_ctrl_alert_test.792718746
Short name	T429
Test name
Test status
Simulation time	74471600 ps
CPU time	13.64 seconds
Started	Aug 13 06:20:37 PM PDT 24
Finished	Aug 13 06:20:51 PM PDT 24
Peak memory	265728 kb
Host	smart-09a59bd5-d36d-4b84-a040-c43ebbfa9d4a
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792718746 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.792718746
Directory	/workspace/24.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/24.flash_ctrl_connect.4123304972
Short name	T984
Test name
Test status
Simulation time	39825500 ps
CPU time	15.84 seconds
Started	Aug 13 06:20:38 PM PDT 24
Finished	Aug 13 06:20:54 PM PDT 24
Peak memory	284828 kb
Host	smart-ec548df5-b6b3-40a7-b2eb-614ddec95196
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4123304972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.4123304972
Directory	/workspace/24.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/24.flash_ctrl_disable.1314090096
Short name	T381
Test name
Test status
Simulation time	125817800 ps
CPU time	21.83 seconds
Started	Aug 13 06:20:36 PM PDT 24
Finished	Aug 13 06:20:58 PM PDT 24
Peak memory	275460 kb
Host	smart-c9be023a-6517-4093-8487-3f9c88df85b6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314090096 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_disable.1314090096
Directory	/workspace/24.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/24.flash_ctrl_hw_sec_otp.3798767258
Short name	T530
Test name
Test status
Simulation time	17003740800 ps
CPU time	101.91 seconds
Started	Aug 13 06:20:28 PM PDT 24
Finished	Aug 13 06:22:10 PM PDT 24
Peak memory	261124 kb
Host	smart-6742cd87-3c2b-4429-9505-e57650724004
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798767258 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_ hw_sec_otp.3798767258
Directory	/workspace/24.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/24.flash_ctrl_intr_rd.3903661754
Short name	T798
Test name
Test status
Simulation time	6685007200 ps
CPU time	202.04 seconds
Started	Aug 13 06:20:34 PM PDT 24
Finished	Aug 13 06:23:57 PM PDT 24
Peak memory	291540 kb
Host	smart-e15443d4-3fd3-41b1-8ecf-7e6104554bc2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903661754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.fla sh_ctrl_intr_rd.3903661754
Directory	/workspace/24.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/24.flash_ctrl_intr_rd_slow_flash.3511323642
Short name	T840
Test name
Test status
Simulation time	24425019300 ps
CPU time	292.54 seconds
Started	Aug 13 06:20:37 PM PDT 24
Finished	Aug 13 06:25:29 PM PDT 24
Peak memory	285736 kb
Host	smart-b4013d70-d96a-4a49-939f-718c24f93c8a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511323642 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd_slow_flash.3511323642
Directory	/workspace/24.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/24.flash_ctrl_otp_reset.4277288374
Short name	T992
Test name
Test status
Simulation time	69686400 ps
CPU time	110.61 seconds
Started	Aug 13 06:20:38 PM PDT 24
Finished	Aug 13 06:22:29 PM PDT 24
Peak memory	261504 kb
Host	smart-23d7181f-f5d8-4375-a704-3caac4194931
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277288374 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_o tp_reset.4277288374
Directory	/workspace/24.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/24.flash_ctrl_prog_reset.1290482854
Short name	T1084
Test name
Test status
Simulation time	67195400 ps
CPU time	13.28 seconds
Started	Aug 13 06:20:34 PM PDT 24
Finished	Aug 13 06:20:47 PM PDT 24
Peak memory	259624 kb
Host	smart-f59f68c3-17b9-45c9-814b-8872372141a9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290482854 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 24.flash_ctrl_prog_reset.1290482854
Directory	/workspace/24.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/24.flash_ctrl_rw_evict_all_en.4192560428
Short name	T675
Test name
Test status
Simulation time	165663900 ps
CPU time	31.52 seconds
Started	Aug 13 06:20:37 PM PDT 24
Finished	Aug 13 06:21:09 PM PDT 24
Peak memory	276192 kb
Host	smart-f1b827e0-1c7d-4e96-acd0-7bb61066d408
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192560428 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict_all_en.4192560428
Directory	/workspace/24.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/24.flash_ctrl_sec_info_access.242955529
Short name	T951
Test name
Test status
Simulation time	8706299300 ps
CPU time	68.02 seconds
Started	Aug 13 06:20:37 PM PDT 24
Finished	Aug 13 06:21:45 PM PDT 24
Peak memory	264316 kb
Host	smart-e6037d8b-810c-4a95-a156-f14adc924270
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=242955529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.242955529
Directory	/workspace/24.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/24.flash_ctrl_smoke.3443242425
Short name	T906
Test name
Test status
Simulation time	144857300 ps
CPU time	146.96 seconds
Started	Aug 13 06:20:27 PM PDT 24
Finished	Aug 13 06:22:54 PM PDT 24
Peak memory	277508 kb
Host	smart-5546f982-0a60-4f9f-8833-a710f3edf21b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3443242425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.3443242425
Directory	/workspace/24.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/25.flash_ctrl_alert_test.2904579909
Short name	T428
Test name
Test status
Simulation time	83299400 ps
CPU time	13.68 seconds
Started	Aug 13 06:20:43 PM PDT 24
Finished	Aug 13 06:20:57 PM PDT 24
Peak memory	258796 kb
Host	smart-8fdccc63-9979-4d3e-a857-5389add2ed37
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904579909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test. 2904579909
Directory	/workspace/25.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/25.flash_ctrl_connect.2863073860
Short name	T1112
Test name
Test status
Simulation time	54428700 ps
CPU time	16.22 seconds
Started	Aug 13 06:20:43 PM PDT 24
Finished	Aug 13 06:20:59 PM PDT 24
Peak memory	284784 kb
Host	smart-a9c4d274-4ee2-4570-af4e-63d31be7b714
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2863073860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.2863073860
Directory	/workspace/25.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/25.flash_ctrl_disable.3573685807
Short name	T74
Test name
Test status
Simulation time	25767100 ps
CPU time	20.38 seconds
Started	Aug 13 06:20:42 PM PDT 24
Finished	Aug 13 06:21:02 PM PDT 24
Peak memory	274148 kb
Host	smart-1abb18cb-3471-4ea7-8e03-399ba6deace7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573685807 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_disable.3573685807
Directory	/workspace/25.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/25.flash_ctrl_hw_sec_otp.2620354131
Short name	T1027
Test name
Test status
Simulation time	2680490600 ps
CPU time	214.81 seconds
Started	Aug 13 06:20:36 PM PDT 24
Finished	Aug 13 06:24:11 PM PDT 24
Peak memory	263784 kb
Host	smart-4e226d8e-5d84-412a-900a-d5d695018e9b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620354131 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_ hw_sec_otp.2620354131
Directory	/workspace/25.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/25.flash_ctrl_intr_rd.701521082
Short name	T3
Test name
Test status
Simulation time	5814120500 ps
CPU time	193.81 seconds
Started	Aug 13 06:20:43 PM PDT 24
Finished	Aug 13 06:23:57 PM PDT 24
Peak memory	291532 kb
Host	smart-462928a8-32d4-4bfc-bef5-543c249e9a98
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701521082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flas h_ctrl_intr_rd.701521082
Directory	/workspace/25.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/25.flash_ctrl_intr_rd_slow_flash.3984934729
Short name	T977
Test name
Test status
Simulation time	47922077800 ps
CPU time	311.3 seconds
Started	Aug 13 06:20:43 PM PDT 24
Finished	Aug 13 06:25:54 PM PDT 24
Peak memory	285764 kb
Host	smart-978def96-4106-44a7-9b66-1e9cb4c1b869
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984934729 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd_slow_flash.3984934729
Directory	/workspace/25.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/25.flash_ctrl_otp_reset.3607869337
Short name	T914
Test name
Test status
Simulation time	217678800 ps
CPU time	110.88 seconds
Started	Aug 13 06:20:37 PM PDT 24
Finished	Aug 13 06:22:28 PM PDT 24
Peak memory	264592 kb
Host	smart-0ee08ec1-3de9-4b16-99b2-873e4b9169a9
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607869337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_o tp_reset.3607869337
Directory	/workspace/25.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/25.flash_ctrl_prog_reset.1432054118
Short name	T371
Test name
Test status
Simulation time	27666400 ps
CPU time	13.54 seconds
Started	Aug 13 06:20:42 PM PDT 24
Finished	Aug 13 06:20:56 PM PDT 24
Peak memory	259940 kb
Host	smart-63574370-cdf4-407d-807f-1c7f57fcad7c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432054118 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 25.flash_ctrl_prog_reset.1432054118
Directory	/workspace/25.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/25.flash_ctrl_rw_evict.726603659
Short name	T20
Test name
Test status
Simulation time	30283900 ps
CPU time	31.73 seconds
Started	Aug 13 06:20:42 PM PDT 24
Finished	Aug 13 06:21:13 PM PDT 24
Peak memory	273816 kb
Host	smart-2a1d9cd6-bc37-491d-a1df-bb1d3c03ede6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726603659 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.fla sh_ctrl_rw_evict.726603659
Directory	/workspace/25.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/25.flash_ctrl_rw_evict_all_en.2945709579
Short name	T408
Test name
Test status
Simulation time	27321700 ps
CPU time	28.34 seconds
Started	Aug 13 06:20:41 PM PDT 24
Finished	Aug 13 06:21:09 PM PDT 24
Peak memory	274228 kb
Host	smart-abd3c151-6813-4bd4-bfa2-29e99a2087c0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945709579 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict_all_en.2945709579
Directory	/workspace/25.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/25.flash_ctrl_smoke.2854499366
Short name	T466
Test name
Test status
Simulation time	38317800 ps
CPU time	49.66 seconds
Started	Aug 13 06:20:35 PM PDT 24
Finished	Aug 13 06:21:24 PM PDT 24
Peak memory	271752 kb
Host	smart-865fdc79-197a-449d-a2d5-a2b23976ac57
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2854499366 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.2854499366
Directory	/workspace/25.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/26.flash_ctrl_alert_test.4182810180
Short name	T467
Test name
Test status
Simulation time	100523600 ps
CPU time	13.65 seconds
Started	Aug 13 06:20:49 PM PDT 24
Finished	Aug 13 06:21:03 PM PDT 24
Peak memory	265720 kb
Host	smart-6807b229-a580-4bdb-8f94-6a548d6293f7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182810180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test. 4182810180
Directory	/workspace/26.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/26.flash_ctrl_connect.2429681106
Short name	T913
Test name
Test status
Simulation time	17318600 ps
CPU time	16.07 seconds
Started	Aug 13 06:20:49 PM PDT 24
Finished	Aug 13 06:21:06 PM PDT 24
Peak memory	283508 kb
Host	smart-92bc6f6a-8539-4b17-a0d4-0ac945bac4dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2429681106 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.2429681106
Directory	/workspace/26.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/26.flash_ctrl_disable.1333149268
Short name	T190
Test name
Test status
Simulation time	23691300 ps
CPU time	22.19 seconds
Started	Aug 13 06:20:50 PM PDT 24
Finished	Aug 13 06:21:13 PM PDT 24
Peak memory	274016 kb
Host	smart-9aa22d79-5658-4be3-9c8f-badf27e287be
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333149268 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_disable.1333149268
Directory	/workspace/26.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/26.flash_ctrl_hw_sec_otp.3473604009
Short name	T932
Test name
Test status
Simulation time	7809978600 ps
CPU time	251.61 seconds
Started	Aug 13 06:20:49 PM PDT 24
Finished	Aug 13 06:25:01 PM PDT 24
Peak memory	261424 kb
Host	smart-30fb4970-e4ee-4901-9b77-ba969c02df55
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473604009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_ hw_sec_otp.3473604009
Directory	/workspace/26.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/26.flash_ctrl_intr_rd.2531759395
Short name	T561
Test name
Test status
Simulation time	4833504700 ps
CPU time	164.27 seconds
Started	Aug 13 06:20:50 PM PDT 24
Finished	Aug 13 06:23:35 PM PDT 24
Peak memory	294772 kb
Host	smart-873a1608-1c30-4cce-a55a-333795524e83
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531759395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fla sh_ctrl_intr_rd.2531759395
Directory	/workspace/26.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/26.flash_ctrl_intr_rd_slow_flash.1700924931
Short name	T564
Test name
Test status
Simulation time	27231742400 ps
CPU time	140.24 seconds
Started	Aug 13 06:20:51 PM PDT 24
Finished	Aug 13 06:23:12 PM PDT 24
Peak memory	293472 kb
Host	smart-8ef58ab3-1f69-4b7c-a384-08365ff13a22
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700924931 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd_slow_flash.1700924931
Directory	/workspace/26.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/26.flash_ctrl_otp_reset.3058190050
Short name	T643
Test name
Test status
Simulation time	221620100 ps
CPU time	133.65 seconds
Started	Aug 13 06:20:49 PM PDT 24
Finished	Aug 13 06:23:03 PM PDT 24
Peak memory	260372 kb
Host	smart-c00674af-c3c6-4ae8-9590-70ea4a182444
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058190050 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_o tp_reset.3058190050
Directory	/workspace/26.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/26.flash_ctrl_prog_reset.414428593
Short name	T369
Test name
Test status
Simulation time	7365186500 ps
CPU time	191.18 seconds
Started	Aug 13 06:20:50 PM PDT 24
Finished	Aug 13 06:24:01 PM PDT 24
Peak memory	261108 kb
Host	smart-d0a58d54-b843-4671-b9cc-6a5b117587ed
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414428593 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 26.flash_ctrl_prog_reset.414428593
Directory	/workspace/26.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/26.flash_ctrl_rw_evict.1120638190
Short name	T401
Test name
Test status
Simulation time	31348100 ps
CPU time	31.47 seconds
Started	Aug 13 06:20:50 PM PDT 24
Finished	Aug 13 06:21:22 PM PDT 24
Peak memory	276216 kb
Host	smart-02c45824-5d24-442e-aa14-3b4fc6409bac
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120638190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.fl ash_ctrl_rw_evict.1120638190
Directory	/workspace/26.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/26.flash_ctrl_rw_evict_all_en.277876800
Short name	T149
Test name
Test status
Simulation time	78080500 ps
CPU time	29.28 seconds
Started	Aug 13 06:20:48 PM PDT 24
Finished	Aug 13 06:21:17 PM PDT 24
Peak memory	268476 kb
Host	smart-fa1cbf27-851d-4d72-a8e7-2b41ca0faaaa
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277876800 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict_all_en.277876800
Directory	/workspace/26.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/26.flash_ctrl_smoke.4144805508
Short name	T523
Test name
Test status
Simulation time	22428200 ps
CPU time	146.49 seconds
Started	Aug 13 06:20:42 PM PDT 24
Finished	Aug 13 06:23:09 PM PDT 24
Peak memory	278660 kb
Host	smart-ce1a2422-2d93-4025-8b5f-ca25d5782550
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4144805508 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.4144805508
Directory	/workspace/26.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/27.flash_ctrl_alert_test.1372727042
Short name	T88
Test name
Test status
Simulation time	87412100 ps
CPU time	13.49 seconds
Started	Aug 13 06:20:57 PM PDT 24
Finished	Aug 13 06:21:11 PM PDT 24
Peak memory	258756 kb
Host	smart-086a487f-b1ec-4222-bd1f-055564999a83
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372727042 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test. 1372727042
Directory	/workspace/27.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/27.flash_ctrl_connect.3128793273
Short name	T740
Test name
Test status
Simulation time	40732600 ps
CPU time	15.71 seconds
Started	Aug 13 06:20:56 PM PDT 24
Finished	Aug 13 06:21:12 PM PDT 24
Peak memory	284752 kb
Host	smart-4114836a-0313-42b8-a73e-5475b9eac0ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3128793273 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.3128793273
Directory	/workspace/27.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/27.flash_ctrl_hw_sec_otp.761817815
Short name	T846
Test name
Test status
Simulation time	10038964800 ps
CPU time	63.56 seconds
Started	Aug 13 06:20:52 PM PDT 24
Finished	Aug 13 06:21:56 PM PDT 24
Peak memory	262692 kb
Host	smart-bba87614-e795-45f4-8762-ebcf94bd39a2
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761817815 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_h w_sec_otp.761817815
Directory	/workspace/27.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/27.flash_ctrl_intr_rd.2574554912
Short name	T808
Test name
Test status
Simulation time	574095700 ps
CPU time	138.74 seconds
Started	Aug 13 06:20:50 PM PDT 24
Finished	Aug 13 06:23:09 PM PDT 24
Peak memory	294924 kb
Host	smart-c2bd3efa-55d1-4567-ae91-5bab76ceb185
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574554912 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fla sh_ctrl_intr_rd.2574554912
Directory	/workspace/27.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.1430929638
Short name	T737
Test name
Test status
Simulation time	9049280600 ps
CPU time	203.82 seconds
Started	Aug 13 06:20:50 PM PDT 24
Finished	Aug 13 06:24:13 PM PDT 24
Peak memory	292624 kb
Host	smart-88a828ee-05f8-43d2-9e9d-85a7a039e319
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430929638 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd_slow_flash.1430929638
Directory	/workspace/27.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/27.flash_ctrl_otp_reset.2350004666
Short name	T779
Test name
Test status
Simulation time	133459200 ps
CPU time	131.51 seconds
Started	Aug 13 06:20:56 PM PDT 24
Finished	Aug 13 06:23:08 PM PDT 24
Peak memory	260440 kb
Host	smart-1ff53d94-3ba1-412b-b8be-cd856aeb0e52
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350004666 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_o tp_reset.2350004666
Directory	/workspace/27.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/27.flash_ctrl_prog_reset.2824379837
Short name	T762
Test name
Test status
Simulation time	34508900 ps
CPU time	13.57 seconds
Started	Aug 13 06:20:50 PM PDT 24
Finished	Aug 13 06:21:04 PM PDT 24
Peak memory	259640 kb
Host	smart-4897566e-aa15-43b6-97c9-e13b0cfbb323
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824379837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 27.flash_ctrl_prog_reset.2824379837
Directory	/workspace/27.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/27.flash_ctrl_rw_evict.3089559343
Short name	T400
Test name
Test status
Simulation time	76563700 ps
CPU time	28.97 seconds
Started	Aug 13 06:20:50 PM PDT 24
Finished	Aug 13 06:21:19 PM PDT 24
Peak memory	274204 kb
Host	smart-4e0bdaf0-7f3e-4b3e-b5d0-a3de4f775d8f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089559343 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.fl ash_ctrl_rw_evict.3089559343
Directory	/workspace/27.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/27.flash_ctrl_rw_evict_all_en.1177250556
Short name	T636
Test name
Test status
Simulation time	68532400 ps
CPU time	28.98 seconds
Started	Aug 13 06:20:51 PM PDT 24
Finished	Aug 13 06:21:20 PM PDT 24
Peak memory	276272 kb
Host	smart-e7c37b8c-c3dd-4242-96e8-907ede9e32a5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177250556 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict_all_en.1177250556
Directory	/workspace/27.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/27.flash_ctrl_smoke.1952777624
Short name	T676
Test name
Test status
Simulation time	21292200 ps
CPU time	124.71 seconds
Started	Aug 13 06:20:50 PM PDT 24
Finished	Aug 13 06:22:55 PM PDT 24
Peak memory	278392 kb
Host	smart-3c735b98-7cc6-4666-8277-68cec8591efa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1952777624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.1952777624
Directory	/workspace/27.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/28.flash_ctrl_alert_test.917444544
Short name	T956
Test name
Test status
Simulation time	126208100 ps
CPU time	13.67 seconds
Started	Aug 13 06:20:57 PM PDT 24
Finished	Aug 13 06:21:11 PM PDT 24
Peak memory	258924 kb
Host	smart-08cfcc48-86d5-42da-ab9f-7f9c1d616b22
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917444544 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.917444544
Directory	/workspace/28.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/28.flash_ctrl_connect.412323691
Short name	T311
Test name
Test status
Simulation time	50378100 ps
CPU time	15.89 seconds
Started	Aug 13 06:20:57 PM PDT 24
Finished	Aug 13 06:21:13 PM PDT 24
Peak memory	283552 kb
Host	smart-fcd10bae-7e39-46c7-9521-bbd6d85aeade
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=412323691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.412323691
Directory	/workspace/28.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/28.flash_ctrl_disable.1489868576
Short name	T94
Test name
Test status
Simulation time	20033600 ps
CPU time	22.64 seconds
Started	Aug 13 06:20:57 PM PDT 24
Finished	Aug 13 06:21:20 PM PDT 24
Peak memory	274048 kb
Host	smart-803a5aef-48e4-4184-9c72-090ec4545cf7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489868576 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_disable.1489868576
Directory	/workspace/28.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/28.flash_ctrl_hw_sec_otp.3613206486
Short name	T1009
Test name
Test status
Simulation time	5231072100 ps
CPU time	97.13 seconds
Started	Aug 13 06:20:56 PM PDT 24
Finished	Aug 13 06:22:33 PM PDT 24
Peak memory	262776 kb
Host	smart-95569808-d9a2-470e-a475-702fde495172
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613206486 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_ hw_sec_otp.3613206486
Directory	/workspace/28.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/28.flash_ctrl_intr_rd.3726452403
Short name	T609
Test name
Test status
Simulation time	4650462300 ps
CPU time	236.75 seconds
Started	Aug 13 06:21:01 PM PDT 24
Finished	Aug 13 06:24:58 PM PDT 24
Peak memory	285592 kb
Host	smart-7b125f98-89a9-4139-a612-7f5e37430394
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726452403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fla sh_ctrl_intr_rd.3726452403
Directory	/workspace/28.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/28.flash_ctrl_intr_rd_slow_flash.2516271224
Short name	T1025
Test name
Test status
Simulation time	23661082800 ps
CPU time	140.64 seconds
Started	Aug 13 06:20:56 PM PDT 24
Finished	Aug 13 06:23:16 PM PDT 24
Peak memory	293644 kb
Host	smart-6bf35140-79f4-439c-a823-33733b99a3db
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516271224 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd_slow_flash.2516271224
Directory	/workspace/28.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/28.flash_ctrl_otp_reset.1344258918
Short name	T868
Test name
Test status
Simulation time	159443400 ps
CPU time	108.6 seconds
Started	Aug 13 06:20:58 PM PDT 24
Finished	Aug 13 06:22:46 PM PDT 24
Peak memory	260444 kb
Host	smart-b3fe5916-564d-42a5-813c-ea200182b09b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344258918 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_o tp_reset.1344258918
Directory	/workspace/28.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/28.flash_ctrl_prog_reset.2864176682
Short name	T527
Test name
Test status
Simulation time	234600900 ps
CPU time	21.45 seconds
Started	Aug 13 06:20:57 PM PDT 24
Finished	Aug 13 06:21:19 PM PDT 24
Peak memory	260504 kb
Host	smart-fc699c3a-d5bb-414e-87a9-c16d3084cb4a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864176682 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 28.flash_ctrl_prog_reset.2864176682
Directory	/workspace/28.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/28.flash_ctrl_rw_evict.3044777482
Short name	T1057
Test name
Test status
Simulation time	142827700 ps
CPU time	30.68 seconds
Started	Aug 13 06:20:57 PM PDT 24
Finished	Aug 13 06:21:28 PM PDT 24
Peak memory	274104 kb
Host	smart-71b941df-adda-4ce6-b98f-f968d3db254d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044777482 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.fl ash_ctrl_rw_evict.3044777482
Directory	/workspace/28.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.1532431470
Short name	T614
Test name
Test status
Simulation time	82330500 ps
CPU time	31.73 seconds
Started	Aug 13 06:20:56 PM PDT 24
Finished	Aug 13 06:21:28 PM PDT 24
Peak memory	275412 kb
Host	smart-cbd5813b-1f14-4394-b7b4-3d653ba5e6a3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532431470 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict_all_en.1532431470
Directory	/workspace/28.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/28.flash_ctrl_sec_info_access.1101717470
Short name	T1011
Test name
Test status
Simulation time	1978740300 ps
CPU time	70.11 seconds
Started	Aug 13 06:20:58 PM PDT 24
Finished	Aug 13 06:22:08 PM PDT 24
Peak memory	263608 kb
Host	smart-4668a0c7-bfa7-4825-94d0-3cd5873d5424
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1101717470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.1101717470
Directory	/workspace/28.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/28.flash_ctrl_smoke.3797366776
Short name	T924
Test name
Test status
Simulation time	31610800 ps
CPU time	50.48 seconds
Started	Aug 13 06:20:58 PM PDT 24
Finished	Aug 13 06:21:49 PM PDT 24
Peak memory	271428 kb
Host	smart-88d5b5d0-9280-4ef0-8916-358b99883b7a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3797366776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.3797366776
Directory	/workspace/28.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/29.flash_ctrl_alert_test.2363653136
Short name	T425
Test name
Test status
Simulation time	48024900 ps
CPU time	13.72 seconds
Started	Aug 13 06:21:04 PM PDT 24
Finished	Aug 13 06:21:18 PM PDT 24
Peak memory	258876 kb
Host	smart-1071e7a9-66c2-42ce-80de-b21bc173b259
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363653136 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test. 2363653136
Directory	/workspace/29.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/29.flash_ctrl_connect.389850783
Short name	T110
Test name
Test status
Simulation time	39848100 ps
CPU time	13.28 seconds
Started	Aug 13 06:21:02 PM PDT 24
Finished	Aug 13 06:21:16 PM PDT 24
Peak memory	283464 kb
Host	smart-e1c4be7d-538e-4b03-8428-ae9f5742dfa0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=389850783 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.389850783
Directory	/workspace/29.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/29.flash_ctrl_disable.101905869
Short name	T680
Test name
Test status
Simulation time	15361100 ps
CPU time	22.4 seconds
Started	Aug 13 06:21:03 PM PDT 24
Finished	Aug 13 06:21:26 PM PDT 24
Peak memory	274188 kb
Host	smart-664a7380-c134-4dec-a715-45d309d21064
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101905869 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_disable.101905869
Directory	/workspace/29.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/29.flash_ctrl_hw_sec_otp.2420234981
Short name	T624
Test name
Test status
Simulation time	5684345900 ps
CPU time	113.61 seconds
Started	Aug 13 06:20:58 PM PDT 24
Finished	Aug 13 06:22:51 PM PDT 24
Peak memory	263500 kb
Host	smart-b06300bb-3190-4490-9372-4a8573573ce6
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420234981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_ hw_sec_otp.2420234981
Directory	/workspace/29.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.1985298424
Short name	T456
Test name
Test status
Simulation time	40896112700 ps
CPU time	172.74 seconds
Started	Aug 13 06:20:58 PM PDT 24
Finished	Aug 13 06:23:51 PM PDT 24
Peak memory	293488 kb
Host	smart-9c539131-500f-49da-94e4-4aa44705d34d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985298424 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd_slow_flash.1985298424
Directory	/workspace/29.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/29.flash_ctrl_otp_reset.2673311625
Short name	T917
Test name
Test status
Simulation time	171421500 ps
CPU time	132.33 seconds
Started	Aug 13 06:20:57 PM PDT 24
Finished	Aug 13 06:23:10 PM PDT 24
Peak memory	262720 kb
Host	smart-74c7a0cb-345b-4b78-99da-322b6545c594
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673311625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_o tp_reset.2673311625
Directory	/workspace/29.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/29.flash_ctrl_prog_reset.3154655131
Short name	T546
Test name
Test status
Simulation time	33656200 ps
CPU time	13.59 seconds
Started	Aug 13 06:20:57 PM PDT 24
Finished	Aug 13 06:21:11 PM PDT 24
Peak memory	259532 kb
Host	smart-b77f50b0-4eb1-47bb-9d38-c3474230ef2b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154655131 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 29.flash_ctrl_prog_reset.3154655131
Directory	/workspace/29.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/29.flash_ctrl_rw_evict_all_en.975657062
Short name	T1053
Test name
Test status
Simulation time	29643000 ps
CPU time	30.74 seconds
Started	Aug 13 06:20:58 PM PDT 24
Finished	Aug 13 06:21:29 PM PDT 24
Peak memory	276252 kb
Host	smart-b2e5a312-d88d-4a97-82e5-778c7337963d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975657062 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict_all_en.975657062
Directory	/workspace/29.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/29.flash_ctrl_sec_info_access.1081192059
Short name	T794
Test name
Test status
Simulation time	1953840400 ps
CPU time	55.14 seconds
Started	Aug 13 06:21:04 PM PDT 24
Finished	Aug 13 06:21:59 PM PDT 24
Peak memory	264448 kb
Host	smart-598c11fe-9417-49d6-be4b-1215004edb72
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1081192059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.1081192059
Directory	/workspace/29.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/29.flash_ctrl_smoke.2612636909
Short name	T529
Test name
Test status
Simulation time	259563800 ps
CPU time	98.87 seconds
Started	Aug 13 06:21:01 PM PDT 24
Finished	Aug 13 06:22:40 PM PDT 24
Peak memory	276432 kb
Host	smart-e6e60d29-989c-4481-84a2-9eaa17c76314
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2612636909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.2612636909
Directory	/workspace/29.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/3.flash_ctrl_alert_test.418921749
Short name	T483
Test name
Test status
Simulation time	42905600 ps
CPU time	14.11 seconds
Started	Aug 13 06:16:04 PM PDT 24
Finished	Aug 13 06:16:18 PM PDT 24
Peak memory	265740 kb
Host	smart-986cf818-7f14-4ba4-98f3-d226ee16c4c2
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418921749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.418921749
Directory	/workspace/3.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/3.flash_ctrl_config_regwen.3051763149
Short name	T1032
Test name
Test status
Simulation time	39037200 ps
CPU time	13.8 seconds
Started	Aug 13 06:16:03 PM PDT 24
Finished	Aug 13 06:16:17 PM PDT 24
Peak memory	262020 kb
Host	smart-b1d5765a-bf00-4daa-ac17-cf8f16da2b48
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051763149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3 .flash_ctrl_config_regwen.3051763149
Directory	/workspace/3.flash_ctrl_config_regwen/latest

Test location	/workspace/coverage/default/3.flash_ctrl_connect.2043450147
Short name	T804
Test name
Test status
Simulation time	15062700 ps
CPU time	15.83 seconds
Started	Aug 13 06:16:03 PM PDT 24
Finished	Aug 13 06:16:19 PM PDT 24
Peak memory	284832 kb
Host	smart-c8992b91-9705-44b9-9918-ce5ed5269a1c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2043450147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.2043450147
Directory	/workspace/3.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/3.flash_ctrl_derr_detect.2737305990
Short name	T724
Test name
Test status
Simulation time	3028621700 ps
CPU time	190.32 seconds
Started	Aug 13 06:15:59 PM PDT 24
Finished	Aug 13 06:19:09 PM PDT 24
Peak memory	282372 kb
Host	smart-bf87f7dc-ee49-4611-8a00-32777477a73d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737305990 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_derr_detect.2737305990
Directory	/workspace/3.flash_ctrl_derr_detect/latest

Test location	/workspace/coverage/default/3.flash_ctrl_erase_suspend.1503718222
Short name	T162
Test name
Test status
Simulation time	2699819200 ps
CPU time	453.7 seconds
Started	Aug 13 06:15:45 PM PDT 24
Finished	Aug 13 06:23:19 PM PDT 24
Peak memory	263964 kb
Host	smart-6c4af140-66e0-4cd0-ab7c-f21ccb218311
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1503718222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.1503718222
Directory	/workspace/3.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/3.flash_ctrl_error_mp.609562837
Short name	T686
Test name
Test status
Simulation time	8044118800 ps
CPU time	2187.82 seconds
Started	Aug 13 06:15:56 PM PDT 24
Finished	Aug 13 06:52:25 PM PDT 24
Peak memory	265500 kb
Host	smart-d65ffc64-a4bc-4968-a591-dae29936748f
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=609562837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_mp.609562837
Directory	/workspace/3.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/3.flash_ctrl_error_prog_type.677253078
Short name	T82
Test name
Test status
Simulation time	3645712300 ps
CPU time	2281.86 seconds
Started	Aug 13 06:15:55 PM PDT 24
Finished	Aug 13 06:53:57 PM PDT 24
Peak memory	262564 kb
Host	smart-99e50bd4-270c-4d83-9ab3-834fef965bf6
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677253078 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 3.flash_ctrl_error_prog_type.677253078
Directory	/workspace/3.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/3.flash_ctrl_error_prog_win.4116594378
Short name	T447
Test name
Test status
Simulation time	328573800 ps
CPU time	783.71 seconds
Started	Aug 13 06:15:56 PM PDT 24
Finished	Aug 13 06:29:00 PM PDT 24
Peak memory	274060 kb
Host	smart-ed849d59-93bb-4352-9a10-39090af2969d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4116594378 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.4116594378
Directory	/workspace/3.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/3.flash_ctrl_fetch_code.766000823
Short name	T1093
Test name
Test status
Simulation time	271329400 ps
CPU time	20.34 seconds
Started	Aug 13 06:15:42 PM PDT 24
Finished	Aug 13 06:16:03 PM PDT 24
Peak memory	264244 kb
Host	smart-7118cc2d-b031-4bcd-a083-76e5cbef678a
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766000823 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetch_code.766000823
Directory	/workspace/3.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/3.flash_ctrl_full_mem_access.2690703686
Short name	T908
Test name
Test status
Simulation time	497564644200 ps
CPU time	3012 seconds
Started	Aug 13 06:15:42 PM PDT 24
Finished	Aug 13 07:05:54 PM PDT 24
Peak memory	265772 kb
Host	smart-27bfe71b-3d0a-45e4-a36d-23f54fd28d9c
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690703686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_c trl_full_mem_access.2690703686
Directory	/workspace/3.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/3.flash_ctrl_host_dir_rd.2641695345
Short name	T640
Test name
Test status
Simulation time	122166200 ps
CPU time	112.98 seconds
Started	Aug 13 06:15:35 PM PDT 24
Finished	Aug 13 06:17:28 PM PDT 24
Peak memory	265840 kb
Host	smart-8cbe1f62-ee5a-47c4-a2ee-b4fe75ead12d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2641695345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.2641695345
Directory	/workspace/3.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.3470307979
Short name	T1114
Test name
Test status
Simulation time	10019569700 ps
CPU time	66.45 seconds
Started	Aug 13 06:16:04 PM PDT 24
Finished	Aug 13 06:17:11 PM PDT 24
Peak memory	270356 kb
Host	smart-e39aa4ce-6cbd-43af-afd7-f9c60bccf486
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470307979 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.3470307979
Directory	/workspace/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/3.flash_ctrl_hw_read_seed_err.2304171580
Short name	T1051
Test name
Test status
Simulation time	27160400 ps
CPU time	13.61 seconds
Started	Aug 13 06:16:05 PM PDT 24
Finished	Aug 13 06:16:18 PM PDT 24
Peak memory	258732 kb
Host	smart-bedbc770-df0a-492d-9b30-ba9925143883
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304171580 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_read_seed_err.2304171580
Directory	/workspace/3.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/3.flash_ctrl_hw_rma_reset.4131284155
Short name	T635
Test name
Test status
Simulation time	480285816100 ps
CPU time	1066.46 seconds
Started	Aug 13 06:15:43 PM PDT 24
Finished	Aug 13 06:33:30 PM PDT 24
Peak memory	261660 kb
Host	smart-3b031cd5-d282-417b-ad8b-37dcb3ef270f
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131284155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 3.flash_ctrl_hw_rma_reset.4131284155
Directory	/workspace/3.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/3.flash_ctrl_hw_sec_otp.2198970184
Short name	T606
Test name
Test status
Simulation time	5261343200 ps
CPU time	109.36 seconds
Started	Aug 13 06:15:46 PM PDT 24
Finished	Aug 13 06:17:36 PM PDT 24
Peak memory	263388 kb
Host	smart-9ee281ea-c8b3-4c99-9294-b744e64f7769
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198970184 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_h w_sec_otp.2198970184
Directory	/workspace/3.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/3.flash_ctrl_integrity.4115022325
Short name	T817
Test name
Test status
Simulation time	6798805200 ps
CPU time	554.34 seconds
Started	Aug 13 06:15:57 PM PDT 24
Finished	Aug 13 06:25:12 PM PDT 24
Peak memory	331252 kb
Host	smart-0808f45c-034f-4102-9b2c-9150086855c8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115022325 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 3.flash_ctrl_integrity.4115022325
Directory	/workspace/3.flash_ctrl_integrity/latest

Test location	/workspace/coverage/default/3.flash_ctrl_intr_rd.1284354802
Short name	T903
Test name
Test status
Simulation time	4660829200 ps
CPU time	212.14 seconds
Started	Aug 13 06:15:55 PM PDT 24
Finished	Aug 13 06:19:27 PM PDT 24
Peak memory	285636 kb
Host	smart-bc15d1c9-a70c-40e0-9804-7943ecca244e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284354802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas h_ctrl_intr_rd.1284354802
Directory	/workspace/3.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.1709142724
Short name	T916
Test name
Test status
Simulation time	26783285800 ps
CPU time	268.96 seconds
Started	Aug 13 06:15:56 PM PDT 24
Finished	Aug 13 06:20:25 PM PDT 24
Peak memory	285768 kb
Host	smart-01f6c36b-78fe-4f03-ae22-76c498cc8d20
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709142724 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd_slow_flash.1709142724
Directory	/workspace/3.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/3.flash_ctrl_intr_wr.3514344397
Short name	T1036
Test name
Test status
Simulation time	5028197000 ps
CPU time	76.7 seconds
Started	Aug 13 06:15:57 PM PDT 24
Finished	Aug 13 06:17:13 PM PDT 24
Peak memory	261212 kb
Host	smart-92df1de9-7704-4367-ae15-eb699ba8eb72
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514344397 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 3.flash_ctrl_intr_wr.3514344397
Directory	/workspace/3.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_intr_wr_slow_flash.2584497936
Short name	T500
Test name
Test status
Simulation time	18987032400 ps
CPU time	156.77 seconds
Started	Aug 13 06:16:04 PM PDT 24
Finished	Aug 13 06:18:41 PM PDT 24
Peak memory	260524 kb
Host	smart-e68c0947-d43e-4c39-ae77-91e5b5b82cc7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258 4497936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.2584497936
Directory	/workspace/3.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/3.flash_ctrl_invalid_op.597480805
Short name	T989
Test name
Test status
Simulation time	996250100 ps
CPU time	80.3 seconds
Started	Aug 13 06:15:55 PM PDT 24
Finished	Aug 13 06:17:16 PM PDT 24
Peak memory	263976 kb
Host	smart-0cba1b16-90bb-453f-bac2-486e5fd4a59c
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597480805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.597480805
Directory	/workspace/3.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/3.flash_ctrl_lcmgr_intg.1272196514
Short name	T552
Test name
Test status
Simulation time	37855000 ps
CPU time	13.79 seconds
Started	Aug 13 06:16:05 PM PDT 24
Finished	Aug 13 06:16:19 PM PDT 24
Peak memory	260732 kb
Host	smart-4ddd48f1-fb38-4f50-b45e-225443bee96d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272196514 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 3.flash_ctrl_lcmgr_intg.1272196514
Directory	/workspace/3.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/3.flash_ctrl_mp_regions.656384138
Short name	T141
Test name
Test status
Simulation time	40835350600 ps
CPU time	276.21 seconds
Started	Aug 13 06:15:44 PM PDT 24
Finished	Aug 13 06:20:20 PM PDT 24
Peak memory	276012 kb
Host	smart-2a507740-dd2c-48d9-b698-854019880ee3
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656384138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mp_regions.656384138
Directory	/workspace/3.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/3.flash_ctrl_otp_reset.2903563895
Short name	T667
Test name
Test status
Simulation time	147233100 ps
CPU time	132.05 seconds
Started	Aug 13 06:15:41 PM PDT 24
Finished	Aug 13 06:17:54 PM PDT 24
Peak memory	264800 kb
Host	smart-35b02934-c1d2-4b28-9053-a19ed7167775
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903563895 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ot p_reset.2903563895
Directory	/workspace/3.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/3.flash_ctrl_oversize_error.2523236738
Short name	T677
Test name
Test status
Simulation time	2663566700 ps
CPU time	192.81 seconds
Started	Aug 13 06:15:58 PM PDT 24
Finished	Aug 13 06:19:11 PM PDT 24
Peak memory	282340 kb
Host	smart-a19befc5-9886-4513-9486-e71f9e647f8e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523236738 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_oversize_error.2523236738
Directory	/workspace/3.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.563837627
Short name	T54
Test name
Test status
Simulation time	16737000 ps
CPU time	13.98 seconds
Started	Aug 13 06:16:05 PM PDT 24
Finished	Aug 13 06:16:19 PM PDT 24
Peak memory	277712 kb
Host	smart-f8005640-a3fe-49ad-aba1-25704703ffd3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_ check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=563837627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.563837627
Directory	/workspace/3.flash_ctrl_phy_ack_consistency/latest

Test location	/workspace/coverage/default/3.flash_ctrl_phy_arb_redun.3929855249
Short name	T68
Test name
Test status
Simulation time	719051500 ps
CPU time	20.09 seconds
Started	Aug 13 06:16:05 PM PDT 24
Finished	Aug 13 06:16:25 PM PDT 24
Peak memory	266068 kb
Host	smart-a9e0852f-bbeb-460e-bf89-ed92e80a494d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929855249 -a ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.3929855249
Directory	/workspace/3.flash_ctrl_phy_arb_redun/latest

Test location	/workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.339785178
Short name	T202
Test name
Test status
Simulation time	16498000 ps
CPU time	14.36 seconds
Started	Aug 13 06:16:06 PM PDT 24
Finished	Aug 13 06:16:21 PM PDT 24
Peak memory	263196 kb
Host	smart-53694d9e-6409-4e07-ad20-c13aac0f1488
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339785178 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.339785178
Directory	/workspace/3.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/3.flash_ctrl_prog_reset.397329877
Short name	T1040
Test name
Test status
Simulation time	66817400 ps
CPU time	13.69 seconds
Started	Aug 13 06:16:05 PM PDT 24
Finished	Aug 13 06:16:18 PM PDT 24
Peak memory	259612 kb
Host	smart-e0cf9c73-0674-4e65-9bea-7531aed07616
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397329877 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 3.flash_ctrl_prog_reset.397329877
Directory	/workspace/3.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rand_ops.3846361583
Short name	T31
Test name
Test status
Simulation time	307622500 ps
CPU time	889.48 seconds
Started	Aug 13 06:15:37 PM PDT 24
Finished	Aug 13 06:30:27 PM PDT 24
Peak memory	287056 kb
Host	smart-a3244240-abeb-4a5e-a99e-092847e579b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3846361583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.3846361583
Directory	/workspace/3.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rd_buff_evict.3909476102
Short name	T58
Test name
Test status
Simulation time	3667024400 ps
CPU time	118.58 seconds
Started	Aug 13 06:15:44 PM PDT 24
Finished	Aug 13 06:17:42 PM PDT 24
Peak memory	263320 kb
Host	smart-9010f8d5-44cc-4424-9808-dbc2f81a5e54
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3909476102 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.3909476102
Directory	/workspace/3.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/3.flash_ctrl_re_evict.1250434450
Short name	T402
Test name
Test status
Simulation time	112965900 ps
CPU time	31.28 seconds
Started	Aug 13 06:16:04 PM PDT 24
Finished	Aug 13 06:16:35 PM PDT 24
Peak memory	274220 kb
Host	smart-0da310c3-e298-410f-945f-6167c3850ddd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250434450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla sh_ctrl_re_evict.1250434450
Directory	/workspace/3.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/3.flash_ctrl_read_word_sweep_derr.3537649464
Short name	T361
Test name
Test status
Simulation time	60392100 ps
CPU time	22.64 seconds
Started	Aug 13 06:15:59 PM PDT 24
Finished	Aug 13 06:16:22 PM PDT 24
Peak memory	265892 kb
Host	smart-ce98e950-c850-4efd-9d34-9b4157d3d654
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537649464 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_derr.3537649464
Directory	/workspace/3.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_read_word_sweep_serr.1787727457
Short name	T357
Test name
Test status
Simulation time	78882000 ps
CPU time	22.53 seconds
Started	Aug 13 06:15:58 PM PDT 24
Finished	Aug 13 06:16:20 PM PDT 24
Peak memory	265900 kb
Host	smart-ad113c9b-465d-4e33-a3d7-41f4d4d73c00
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787727457 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fl ash_ctrl_read_word_sweep_serr.1787727457
Directory	/workspace/3.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_ro.594763449
Short name	T918
Test name
Test status
Simulation time	2501921500 ps
CPU time	117.88 seconds
Started	Aug 13 06:16:03 PM PDT 24
Finished	Aug 13 06:18:01 PM PDT 24
Peak memory	290080 kb
Host	smart-c098c8f1-3103-4ec5-9b9e-78c373483869
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594763449 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 3.flash_ctrl_ro.594763449
Directory	/workspace/3.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/3.flash_ctrl_ro_derr.406649240
Short name	T157
Test name
Test status
Simulation time	2451007200 ps
CPU time	139.87 seconds
Started	Aug 13 06:15:56 PM PDT 24
Finished	Aug 13 06:18:16 PM PDT 24
Peak memory	282432 kb
Host	smart-44c43b62-5302-4735-8b81-ff3310f24dd8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 406649240 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.406649240
Directory	/workspace/3.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_ro_serr.2024444906
Short name	T553
Test name
Test status
Simulation time	589800700 ps
CPU time	123.46 seconds
Started	Aug 13 06:15:58 PM PDT 24
Finished	Aug 13 06:18:02 PM PDT 24
Peak memory	282396 kb
Host	smart-e0f320f2-0eff-4874-b39b-d3bb5b6583d3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024444906 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 3.flash_ctrl_ro_serr.2024444906
Directory	/workspace/3.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rw.3492725377
Short name	T720
Test name
Test status
Simulation time	3817685600 ps
CPU time	543.18 seconds
Started	Aug 13 06:15:58 PM PDT 24
Finished	Aug 13 06:25:01 PM PDT 24
Peak memory	310192 kb
Host	smart-56fa01f9-3634-4130-bf81-7a37a1721e99
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492725377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 3.flash_ctrl_rw.3492725377
Directory	/workspace/3.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rw_derr.69382754
Short name	T159
Test name
Test status
Simulation time	20011181800 ps
CPU time	241.15 seconds
Started	Aug 13 06:15:56 PM PDT 24
Finished	Aug 13 06:19:57 PM PDT 24
Peak memory	294384 kb
Host	smart-9008cd2d-9ae9-486a-8eca-31b3271f2297
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69382754 -asse rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_derr.69382754
Directory	/workspace/3.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rw_evict.3765765368
Short name	T22
Test name
Test status
Simulation time	101678100 ps
CPU time	28.84 seconds
Started	Aug 13 06:16:02 PM PDT 24
Finished	Aug 13 06:16:31 PM PDT 24
Peak memory	273744 kb
Host	smart-6fafd904-bb9d-4969-a84e-dbc1a18bc89b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765765368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.fla sh_ctrl_rw_evict.3765765368
Directory	/workspace/3.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rw_evict_all_en.2540819553
Short name	T416
Test name
Test status
Simulation time	29806700 ps
CPU time	31.75 seconds
Started	Aug 13 06:16:05 PM PDT 24
Finished	Aug 13 06:16:37 PM PDT 24
Peak memory	276212 kb
Host	smart-0c469fd3-b049-4041-8d73-4b9f3599a14b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540819553 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict_all_en.2540819553
Directory	/workspace/3.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/3.flash_ctrl_rw_serr.2949526058
Short name	T510
Test name
Test status
Simulation time	7717783400 ps
CPU time	208.89 seconds
Started	Aug 13 06:15:54 PM PDT 24
Finished	Aug 13 06:19:23 PM PDT 24
Peak memory	295656 kb
Host	smart-419b3c0f-f667-4aac-bfea-66e8c4ff77f9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949526058 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 3.flash_ctrl_rw_serr.2949526058
Directory	/workspace/3.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/3.flash_ctrl_sec_info_access.2862375466
Short name	T911
Test name
Test status
Simulation time	1249805800 ps
CPU time	56.1 seconds
Started	Aug 13 06:16:00 PM PDT 24
Finished	Aug 13 06:16:56 PM PDT 24
Peak memory	264976 kb
Host	smart-0de67ac7-fce6-44b7-a1c2-a64b09308a6d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2862375466 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.2862375466
Directory	/workspace/3.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/3.flash_ctrl_serr_address.1775999117
Short name	T710
Test name
Test status
Simulation time	821178200 ps
CPU time	77.69 seconds
Started	Aug 13 06:15:55 PM PDT 24
Finished	Aug 13 06:17:13 PM PDT 24
Peak memory	274172 kb
Host	smart-5c0e157b-dbfc-4f3b-947b-d74cbce0e17b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775999117 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 3.flash_ctrl_serr_address.1775999117
Directory	/workspace/3.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/3.flash_ctrl_serr_counter.764615439
Short name	T860
Test name
Test status
Simulation time	2072996700 ps
CPU time	58.83 seconds
Started	Aug 13 06:15:52 PM PDT 24
Finished	Aug 13 06:16:51 PM PDT 24
Peak memory	276060 kb
Host	smart-3a31e817-fa96-4590-b2bb-4634610ecb7e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764615439 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 3.flash_ctrl_serr_counter.764615439
Directory	/workspace/3.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/3.flash_ctrl_smoke.1249340128
Short name	T478
Test name
Test status
Simulation time	38660200 ps
CPU time	100.08 seconds
Started	Aug 13 06:15:35 PM PDT 24
Finished	Aug 13 06:17:15 PM PDT 24
Peak memory	276496 kb
Host	smart-59204e97-c719-4c02-a31a-edb0f8d5554c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1249340128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.1249340128
Directory	/workspace/3.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/3.flash_ctrl_smoke_hw.2407856538
Short name	T574
Test name
Test status
Simulation time	29474100 ps
CPU time	26.45 seconds
Started	Aug 13 06:15:35 PM PDT 24
Finished	Aug 13 06:16:02 PM PDT 24
Peak memory	260124 kb
Host	smart-31c30ca0-dbc8-401d-a66b-f33cd0b247bf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2407856538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.2407856538
Directory	/workspace/3.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/3.flash_ctrl_stress_all.1842980240
Short name	T889
Test name
Test status
Simulation time	4517782200 ps
CPU time	1260.8 seconds
Started	Aug 13 06:16:04 PM PDT 24
Finished	Aug 13 06:37:06 PM PDT 24
Peak memory	285888 kb
Host	smart-72f9763e-7d85-440b-831d-b8b50471b3d6
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842980240 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stres s_all.1842980240
Directory	/workspace/3.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/3.flash_ctrl_sw_op.1215394968
Short name	T681
Test name
Test status
Simulation time	310818400 ps
CPU time	24.72 seconds
Started	Aug 13 06:15:33 PM PDT 24
Finished	Aug 13 06:15:58 PM PDT 24
Peak memory	262668 kb
Host	smart-ccd5edb1-2a2a-4c39-a728-abdd12e3fa18
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1215394968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.1215394968
Directory	/workspace/3.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/3.flash_ctrl_wo.2989577931
Short name	T55
Test name
Test status
Simulation time	4778107500 ps
CPU time	175.22 seconds
Started	Aug 13 06:15:56 PM PDT 24
Finished	Aug 13 06:18:51 PM PDT 24
Peak memory	260436 kb
Host	smart-dc18483c-6152-47f7-834c-46374653576f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989577931 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 3.flash_ctrl_wo.2989577931
Directory	/workspace/3.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/30.flash_ctrl_alert_test.3221929765
Short name	T1012
Test name
Test status
Simulation time	80885200 ps
CPU time	13.83 seconds
Started	Aug 13 06:21:05 PM PDT 24
Finished	Aug 13 06:21:19 PM PDT 24
Peak memory	265604 kb
Host	smart-0cfbb15e-1a02-4e31-a4f0-7e7d2c049254
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221929765 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test. 3221929765
Directory	/workspace/30.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/30.flash_ctrl_connect.3449017992
Short name	T787
Test name
Test status
Simulation time	15050100 ps
CPU time	15.7 seconds
Started	Aug 13 06:21:05 PM PDT 24
Finished	Aug 13 06:21:20 PM PDT 24
Peak memory	283596 kb
Host	smart-290a090b-e70f-420b-8cc3-95611aa0aa41
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3449017992 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.3449017992
Directory	/workspace/30.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/30.flash_ctrl_disable.165827358
Short name	T637
Test name
Test status
Simulation time	10694000 ps
CPU time	21.66 seconds
Started	Aug 13 06:21:04 PM PDT 24
Finished	Aug 13 06:21:26 PM PDT 24
Peak memory	274148 kb
Host	smart-e03a9bb0-de9a-464b-aa45-c47b0eb465a6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165827358 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_disable.165827358
Directory	/workspace/30.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/30.flash_ctrl_hw_sec_otp.294580658
Short name	T912
Test name
Test status
Simulation time	11517049200 ps
CPU time	248.33 seconds
Started	Aug 13 06:21:04 PM PDT 24
Finished	Aug 13 06:25:13 PM PDT 24
Peak memory	261516 kb
Host	smart-a68f6c6c-092b-4d2f-bca1-ff5b096a5e08
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294580658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_h w_sec_otp.294580658
Directory	/workspace/30.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/30.flash_ctrl_intr_rd.2222002048
Short name	T887
Test name
Test status
Simulation time	817545800 ps
CPU time	131.79 seconds
Started	Aug 13 06:21:04 PM PDT 24
Finished	Aug 13 06:23:16 PM PDT 24
Peak memory	294968 kb
Host	smart-d0d989e5-8546-436c-a242-d4596c68c055
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222002048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.fla sh_ctrl_intr_rd.2222002048
Directory	/workspace/30.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/30.flash_ctrl_intr_rd_slow_flash.3153200860
Short name	T791
Test name
Test status
Simulation time	6185520800 ps
CPU time	119.09 seconds
Started	Aug 13 06:21:04 PM PDT 24
Finished	Aug 13 06:23:03 PM PDT 24
Peak memory	293528 kb
Host	smart-2595634f-f986-4749-99d9-ee2ac1ed5482
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153200860 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd_slow_flash.3153200860
Directory	/workspace/30.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/30.flash_ctrl_rw_evict.85826690
Short name	T405
Test name
Test status
Simulation time	30044500 ps
CPU time	31.06 seconds
Started	Aug 13 06:21:01 PM PDT 24
Finished	Aug 13 06:21:32 PM PDT 24
Peak memory	275032 kb
Host	smart-9a03d497-8efa-4076-8530-ed4b54d2b6d7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85826690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ =flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flas h_ctrl_rw_evict.85826690
Directory	/workspace/30.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/30.flash_ctrl_sec_info_access.2375370974
Short name	T387
Test name
Test status
Simulation time	3045545400 ps
CPU time	72.32 seconds
Started	Aug 13 06:21:04 PM PDT 24
Finished	Aug 13 06:22:17 PM PDT 24
Peak memory	263120 kb
Host	smart-ad0e4f66-c8a6-4ee1-bf4d-8134283f1231
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2375370974 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.2375370974
Directory	/workspace/30.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/30.flash_ctrl_smoke.3446671855
Short name	T569
Test name
Test status
Simulation time	73812300 ps
CPU time	146.78 seconds
Started	Aug 13 06:21:04 PM PDT 24
Finished	Aug 13 06:23:31 PM PDT 24
Peak memory	270400 kb
Host	smart-355c5fc3-3e3a-4682-a5d2-60a775759301
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3446671855 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.3446671855
Directory	/workspace/30.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/31.flash_ctrl_alert_test.2741273563
Short name	T1106
Test name
Test status
Simulation time	36235400 ps
CPU time	13.82 seconds
Started	Aug 13 06:21:12 PM PDT 24
Finished	Aug 13 06:21:26 PM PDT 24
Peak memory	258792 kb
Host	smart-d6b45dca-0f1c-4691-8006-cabd3451b582
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741273563 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test. 2741273563
Directory	/workspace/31.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/31.flash_ctrl_connect.1362833635
Short name	T420
Test name
Test status
Simulation time	46812600 ps
CPU time	13.28 seconds
Started	Aug 13 06:21:11 PM PDT 24
Finished	Aug 13 06:21:24 PM PDT 24
Peak memory	283496 kb
Host	smart-e22c6455-4035-48bd-8c3d-d2de4a2fb68d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1362833635 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.1362833635
Directory	/workspace/31.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/31.flash_ctrl_disable.1863773971
Short name	T97
Test name
Test status
Simulation time	12962400 ps
CPU time	22.01 seconds
Started	Aug 13 06:21:13 PM PDT 24
Finished	Aug 13 06:21:35 PM PDT 24
Peak memory	274052 kb
Host	smart-6ef341f1-88d9-43be-9ff5-8bc32fe7cff1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863773971 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_disable.1863773971
Directory	/workspace/31.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/31.flash_ctrl_hw_sec_otp.1676985864
Short name	T306
Test name
Test status
Simulation time	8686729600 ps
CPU time	142.91 seconds
Started	Aug 13 06:21:04 PM PDT 24
Finished	Aug 13 06:23:27 PM PDT 24
Peak memory	261176 kb
Host	smart-30cb9537-2fe8-4d9f-bd1a-794a9a10552d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676985864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_ hw_sec_otp.1676985864
Directory	/workspace/31.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/31.flash_ctrl_intr_rd.1612352617
Short name	T323
Test name
Test status
Simulation time	726175400 ps
CPU time	111.04 seconds
Started	Aug 13 06:21:04 PM PDT 24
Finished	Aug 13 06:22:55 PM PDT 24
Peak memory	292172 kb
Host	smart-603eb8c0-07d5-4ebe-8e4b-b21ff480b1e0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612352617 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fla sh_ctrl_intr_rd.1612352617
Directory	/workspace/31.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/31.flash_ctrl_intr_rd_slow_flash.1497065796
Short name	T983
Test name
Test status
Simulation time	28729998300 ps
CPU time	163.69 seconds
Started	Aug 13 06:21:14 PM PDT 24
Finished	Aug 13 06:23:58 PM PDT 24
Peak memory	293416 kb
Host	smart-c8552817-89e6-4396-8f76-3e80f408655f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497065796 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd_slow_flash.1497065796
Directory	/workspace/31.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/31.flash_ctrl_otp_reset.2033824588
Short name	T852
Test name
Test status
Simulation time	131825000 ps
CPU time	130.66 seconds
Started	Aug 13 06:21:04 PM PDT 24
Finished	Aug 13 06:23:15 PM PDT 24
Peak memory	260708 kb
Host	smart-0c62bcfb-72e2-4e67-8c3a-3e1a489393a6
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033824588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_o tp_reset.2033824588
Directory	/workspace/31.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/31.flash_ctrl_rw_evict.654962793
Short name	T930
Test name
Test status
Simulation time	28045300 ps
CPU time	30.77 seconds
Started	Aug 13 06:21:13 PM PDT 24
Finished	Aug 13 06:21:44 PM PDT 24
Peak memory	276208 kb
Host	smart-c4e73650-e515-4d89-b6a4-b4076d6035ce
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654962793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.fla sh_ctrl_rw_evict.654962793
Directory	/workspace/31.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/31.flash_ctrl_rw_evict_all_en.1647807641
Short name	T392
Test name
Test status
Simulation time	84748700 ps
CPU time	29.54 seconds
Started	Aug 13 06:21:14 PM PDT 24
Finished	Aug 13 06:21:43 PM PDT 24
Peak memory	276268 kb
Host	smart-34cb49ca-b0b7-404b-a2d3-41ec95307764
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647807641 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict_all_en.1647807641
Directory	/workspace/31.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/31.flash_ctrl_sec_info_access.899743363
Short name	T495
Test name
Test status
Simulation time	3470406200 ps
CPU time	69.49 seconds
Started	Aug 13 06:21:12 PM PDT 24
Finished	Aug 13 06:22:22 PM PDT 24
Peak memory	264400 kb
Host	smart-54b26d88-bc9d-476e-853c-ff097fba996f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=899743363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.899743363
Directory	/workspace/31.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/31.flash_ctrl_smoke.2652015616
Short name	T790
Test name
Test status
Simulation time	45104900 ps
CPU time	146.98 seconds
Started	Aug 13 06:21:04 PM PDT 24
Finished	Aug 13 06:23:31 PM PDT 24
Peak memory	277436 kb
Host	smart-b513a8e8-5f3b-49a1-8cdf-27f066ac995c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2652015616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.2652015616
Directory	/workspace/31.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/32.flash_ctrl_alert_test.2833285257
Short name	T1068
Test name
Test status
Simulation time	41635400 ps
CPU time	13.58 seconds
Started	Aug 13 06:21:12 PM PDT 24
Finished	Aug 13 06:21:26 PM PDT 24
Peak memory	265804 kb
Host	smart-1e855e08-443f-443c-82e8-2668010ca233
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833285257 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test. 2833285257
Directory	/workspace/32.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/32.flash_ctrl_connect.1883411052
Short name	T1046
Test name
Test status
Simulation time	17523900 ps
CPU time	16.11 seconds
Started	Aug 13 06:21:12 PM PDT 24
Finished	Aug 13 06:21:29 PM PDT 24
Peak memory	283532 kb
Host	smart-9b785bd1-b4ab-4228-b68e-0a39943e5b66
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1883411052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.1883411052
Directory	/workspace/32.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/32.flash_ctrl_disable.3837990516
Short name	T376
Test name
Test status
Simulation time	60723300 ps
CPU time	21.61 seconds
Started	Aug 13 06:21:12 PM PDT 24
Finished	Aug 13 06:21:34 PM PDT 24
Peak memory	274088 kb
Host	smart-640bac4f-1470-4a57-bde4-4e3dbe1e3fc6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837990516 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_disable.3837990516
Directory	/workspace/32.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/32.flash_ctrl_hw_sec_otp.3780977097
Short name	T618
Test name
Test status
Simulation time	3972264400 ps
CPU time	126.84 seconds
Started	Aug 13 06:21:13 PM PDT 24
Finished	Aug 13 06:23:20 PM PDT 24
Peak memory	263364 kb
Host	smart-c7b358fa-90c2-465e-9e77-fa181e5831e5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780977097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_ hw_sec_otp.3780977097
Directory	/workspace/32.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/32.flash_ctrl_intr_rd.2764589319
Short name	T751
Test name
Test status
Simulation time	2766251500 ps
CPU time	168.45 seconds
Started	Aug 13 06:21:12 PM PDT 24
Finished	Aug 13 06:24:01 PM PDT 24
Peak memory	295068 kb
Host	smart-147a2f27-7e4a-4036-9486-94751f89f451
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764589319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.fla sh_ctrl_intr_rd.2764589319
Directory	/workspace/32.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/32.flash_ctrl_intr_rd_slow_flash.1201608508
Short name	T27
Test name
Test status
Simulation time	22389787100 ps
CPU time	148.86 seconds
Started	Aug 13 06:21:12 PM PDT 24
Finished	Aug 13 06:23:41 PM PDT 24
Peak memory	294256 kb
Host	smart-35d1b555-fe78-4324-9f96-79e2ca366ffd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201608508 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd_slow_flash.1201608508
Directory	/workspace/32.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/32.flash_ctrl_otp_reset.832786394
Short name	T1072
Test name
Test status
Simulation time	147214200 ps
CPU time	136.09 seconds
Started	Aug 13 06:21:13 PM PDT 24
Finished	Aug 13 06:23:29 PM PDT 24
Peak memory	261656 kb
Host	smart-70300820-e8c5-46a4-81d1-be1211207244
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832786394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_ot p_reset.832786394
Directory	/workspace/32.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/32.flash_ctrl_rw_evict_all_en.1244757992
Short name	T722
Test name
Test status
Simulation time	60296800 ps
CPU time	28.91 seconds
Started	Aug 13 06:21:13 PM PDT 24
Finished	Aug 13 06:21:42 PM PDT 24
Peak memory	274188 kb
Host	smart-bfa1d495-d41a-4fef-88f3-1cf421213f01
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244757992 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict_all_en.1244757992
Directory	/workspace/32.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/32.flash_ctrl_sec_info_access.2660440934
Short name	T388
Test name
Test status
Simulation time	970552300 ps
CPU time	54.96 seconds
Started	Aug 13 06:21:13 PM PDT 24
Finished	Aug 13 06:22:08 PM PDT 24
Peak memory	263784 kb
Host	smart-a8d64a3d-d24c-45cc-b20f-17ceb925154d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2660440934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.2660440934
Directory	/workspace/32.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/32.flash_ctrl_smoke.1983205554
Short name	T585
Test name
Test status
Simulation time	95948000 ps
CPU time	121.84 seconds
Started	Aug 13 06:21:13 PM PDT 24
Finished	Aug 13 06:23:15 PM PDT 24
Peak memory	276940 kb
Host	smart-8a26c2de-7abc-4e20-8175-c8f1c8cfa803
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1983205554 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.1983205554
Directory	/workspace/32.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/33.flash_ctrl_alert_test.3646927886
Short name	T966
Test name
Test status
Simulation time	109824300 ps
CPU time	13.88 seconds
Started	Aug 13 06:21:20 PM PDT 24
Finished	Aug 13 06:21:34 PM PDT 24
Peak memory	258892 kb
Host	smart-4e8a9416-6cce-48d3-8935-8da6aaf61cf4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646927886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test. 3646927886
Directory	/workspace/33.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/33.flash_ctrl_connect.2273066329
Short name	T886
Test name
Test status
Simulation time	59060800 ps
CPU time	15.62 seconds
Started	Aug 13 06:21:20 PM PDT 24
Finished	Aug 13 06:21:36 PM PDT 24
Peak memory	284720 kb
Host	smart-dc878a0a-d265-4cc3-aeab-f29b6ccbe8e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2273066329 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.2273066329
Directory	/workspace/33.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/33.flash_ctrl_disable.4142916880
Short name	T718
Test name
Test status
Simulation time	29459200 ps
CPU time	21.69 seconds
Started	Aug 13 06:21:19 PM PDT 24
Finished	Aug 13 06:21:41 PM PDT 24
Peak memory	274032 kb
Host	smart-a525d23c-17cb-4a20-80a5-905c64f06fcc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142916880 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_disable.4142916880
Directory	/workspace/33.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/33.flash_ctrl_hw_sec_otp.4190708519
Short name	T308
Test name
Test status
Simulation time	16723723600 ps
CPU time	186.66 seconds
Started	Aug 13 06:21:12 PM PDT 24
Finished	Aug 13 06:24:19 PM PDT 24
Peak memory	263360 kb
Host	smart-e446f8b4-6fb7-4e0b-ab86-1a871f7380ba
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190708519 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_ hw_sec_otp.4190708519
Directory	/workspace/33.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/33.flash_ctrl_intr_rd.4198536081
Short name	T528
Test name
Test status
Simulation time	1523621400 ps
CPU time	231.94 seconds
Started	Aug 13 06:21:20 PM PDT 24
Finished	Aug 13 06:25:12 PM PDT 24
Peak memory	285640 kb
Host	smart-6342a2b3-654f-4ff9-9fd6-b44e02c46da2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198536081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fla sh_ctrl_intr_rd.4198536081
Directory	/workspace/33.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/33.flash_ctrl_intr_rd_slow_flash.4117808654
Short name	T759
Test name
Test status
Simulation time	24401864800 ps
CPU time	144.44 seconds
Started	Aug 13 06:21:19 PM PDT 24
Finished	Aug 13 06:23:43 PM PDT 24
Peak memory	293760 kb
Host	smart-f3ec8afc-1d62-4e4c-9fc1-0dc9c05129dc
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117808654 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd_slow_flash.4117808654
Directory	/workspace/33.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/33.flash_ctrl_otp_reset.2501838356
Short name	T892
Test name
Test status
Simulation time	151057600 ps
CPU time	131.78 seconds
Started	Aug 13 06:21:12 PM PDT 24
Finished	Aug 13 06:23:24 PM PDT 24
Peak memory	260572 kb
Host	smart-7c811850-0564-4a09-ad0b-2ed7244c4ab2
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501838356 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_o tp_reset.2501838356
Directory	/workspace/33.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/33.flash_ctrl_rw_evict.3746304588
Short name	T645
Test name
Test status
Simulation time	42146800 ps
CPU time	28.79 seconds
Started	Aug 13 06:21:19 PM PDT 24
Finished	Aug 13 06:21:48 PM PDT 24
Peak memory	276268 kb
Host	smart-c515a2b6-3e26-4c81-ab22-bb63c6db6c8a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746304588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.fl ash_ctrl_rw_evict.3746304588
Directory	/workspace/33.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/33.flash_ctrl_rw_evict_all_en.652053090
Short name	T935
Test name
Test status
Simulation time	37148800 ps
CPU time	31.23 seconds
Started	Aug 13 06:21:17 PM PDT 24
Finished	Aug 13 06:21:49 PM PDT 24
Peak memory	276144 kb
Host	smart-c5e328d8-f95e-4a04-accf-bf1ce45bf18e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652053090 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict_all_en.652053090
Directory	/workspace/33.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/33.flash_ctrl_sec_info_access.2456900278
Short name	T928
Test name
Test status
Simulation time	2303730400 ps
CPU time	73.81 seconds
Started	Aug 13 06:21:20 PM PDT 24
Finished	Aug 13 06:22:34 PM PDT 24
Peak memory	265280 kb
Host	smart-94db5b14-d092-42d0-b163-3ee7bcb69984
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2456900278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.2456900278
Directory	/workspace/33.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/33.flash_ctrl_smoke.3839178988
Short name	T360
Test name
Test status
Simulation time	51488900 ps
CPU time	127.5 seconds
Started	Aug 13 06:21:13 PM PDT 24
Finished	Aug 13 06:23:20 PM PDT 24
Peak memory	276916 kb
Host	smart-475e7809-df3b-4181-8677-1a73bdc6d95a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3839178988 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.3839178988
Directory	/workspace/33.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/34.flash_ctrl_alert_test.1942594143
Short name	T1005
Test name
Test status
Simulation time	31880500 ps
CPU time	13.86 seconds
Started	Aug 13 06:21:32 PM PDT 24
Finished	Aug 13 06:21:46 PM PDT 24
Peak memory	265756 kb
Host	smart-6b5c0e7f-4c57-448f-80bd-46d2e86bc384
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942594143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test. 1942594143
Directory	/workspace/34.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/34.flash_ctrl_connect.2105436427
Short name	T145
Test name
Test status
Simulation time	38844300 ps
CPU time	16.45 seconds
Started	Aug 13 06:21:29 PM PDT 24
Finished	Aug 13 06:21:45 PM PDT 24
Peak memory	284668 kb
Host	smart-65d36294-1dce-4750-b08c-38fc0ddcde04
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2105436427 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.2105436427
Directory	/workspace/34.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/34.flash_ctrl_disable.3029819667
Short name	T98
Test name
Test status
Simulation time	93184400 ps
CPU time	22.05 seconds
Started	Aug 13 06:21:20 PM PDT 24
Finished	Aug 13 06:21:42 PM PDT 24
Peak memory	266836 kb
Host	smart-0cd0d2f7-2bf6-4d78-972c-12df813533ba
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029819667 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_disable.3029819667
Directory	/workspace/34.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/34.flash_ctrl_hw_sec_otp.3340611427
Short name	T434
Test name
Test status
Simulation time	4522480900 ps
CPU time	127.08 seconds
Started	Aug 13 06:21:21 PM PDT 24
Finished	Aug 13 06:23:28 PM PDT 24
Peak memory	261160 kb
Host	smart-9c2e9209-7587-480c-b47b-7de7600376fa
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340611427 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_ hw_sec_otp.3340611427
Directory	/workspace/34.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/34.flash_ctrl_intr_rd.1529379951
Short name	T502
Test name
Test status
Simulation time	1705462300 ps
CPU time	269.64 seconds
Started	Aug 13 06:21:18 PM PDT 24
Finished	Aug 13 06:25:47 PM PDT 24
Peak memory	285808 kb
Host	smart-9e45128a-b255-4f79-8200-d26ee7dc81bb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529379951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.fla sh_ctrl_intr_rd.1529379951
Directory	/workspace/34.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/34.flash_ctrl_intr_rd_slow_flash.4024081929
Short name	T531
Test name
Test status
Simulation time	13101467500 ps
CPU time	269.59 seconds
Started	Aug 13 06:21:19 PM PDT 24
Finished	Aug 13 06:25:48 PM PDT 24
Peak memory	290432 kb
Host	smart-6adaad7d-5807-4f77-9ee2-400c35f82fa6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024081929 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd_slow_flash.4024081929
Directory	/workspace/34.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/34.flash_ctrl_rw_evict_all_en.304353074
Short name	T844
Test name
Test status
Simulation time	34765600 ps
CPU time	30.69 seconds
Started	Aug 13 06:21:22 PM PDT 24
Finished	Aug 13 06:21:53 PM PDT 24
Peak memory	275476 kb
Host	smart-81eb5ea0-bfa6-4f1c-89ff-d859c1e6d73d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304353074 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict_all_en.304353074
Directory	/workspace/34.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/34.flash_ctrl_sec_info_access.224437752
Short name	T356
Test name
Test status
Simulation time	2125148900 ps
CPU time	73.88 seconds
Started	Aug 13 06:21:29 PM PDT 24
Finished	Aug 13 06:22:43 PM PDT 24
Peak memory	265304 kb
Host	smart-fcde7f74-5c7c-4a37-b469-3d250842e2bc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=224437752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.224437752
Directory	/workspace/34.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/34.flash_ctrl_smoke.1716050757
Short name	T359
Test name
Test status
Simulation time	105592100 ps
CPU time	150.16 seconds
Started	Aug 13 06:21:20 PM PDT 24
Finished	Aug 13 06:23:51 PM PDT 24
Peak memory	277576 kb
Host	smart-f7d11a0a-952d-4e7b-8f22-0c53a5dcd38f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1716050757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.1716050757
Directory	/workspace/34.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/35.flash_ctrl_alert_test.3759255537
Short name	T776
Test name
Test status
Simulation time	34505600 ps
CPU time	13.35 seconds
Started	Aug 13 06:21:25 PM PDT 24
Finished	Aug 13 06:21:38 PM PDT 24
Peak memory	258840 kb
Host	smart-6af6c897-2605-485a-92b8-4d798dc65e5c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759255537 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test. 3759255537
Directory	/workspace/35.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/35.flash_ctrl_connect.576808325
Short name	T731
Test name
Test status
Simulation time	28275900 ps
CPU time	16 seconds
Started	Aug 13 06:21:27 PM PDT 24
Finished	Aug 13 06:21:43 PM PDT 24
Peak memory	284812 kb
Host	smart-ffa6249c-03f1-47fa-bde8-36abf2dc0144
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=576808325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.576808325
Directory	/workspace/35.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/35.flash_ctrl_disable.2657567797
Short name	T1054
Test name
Test status
Simulation time	25919900 ps
CPU time	20.68 seconds
Started	Aug 13 06:21:26 PM PDT 24
Finished	Aug 13 06:21:47 PM PDT 24
Peak memory	274232 kb
Host	smart-736d1fde-93a3-4482-9a9a-361a6d9e1202
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657567797 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_disable.2657567797
Directory	/workspace/35.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/35.flash_ctrl_hw_sec_otp.2467858236
Short name	T471
Test name
Test status
Simulation time	2283406500 ps
CPU time	160.86 seconds
Started	Aug 13 06:21:26 PM PDT 24
Finished	Aug 13 06:24:07 PM PDT 24
Peak memory	261552 kb
Host	smart-7e6adcea-d1c6-4ae3-ac4d-003c8098755f
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467858236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_ hw_sec_otp.2467858236
Directory	/workspace/35.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/35.flash_ctrl_intr_rd.510016733
Short name	T672
Test name
Test status
Simulation time	1056933200 ps
CPU time	120.94 seconds
Started	Aug 13 06:21:28 PM PDT 24
Finished	Aug 13 06:23:29 PM PDT 24
Peak memory	294856 kb
Host	smart-242d77f0-7ec8-45a7-ac06-f4612f1dfbf6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510016733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flas h_ctrl_intr_rd.510016733
Directory	/workspace/35.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/35.flash_ctrl_intr_rd_slow_flash.500731738
Short name	T221
Test name
Test status
Simulation time	7508918800 ps
CPU time	158.78 seconds
Started	Aug 13 06:21:29 PM PDT 24
Finished	Aug 13 06:24:08 PM PDT 24
Peak memory	293492 kb
Host	smart-9fd32ad5-43da-438e-ac44-700a474848c1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500731738 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd_slow_flash.500731738
Directory	/workspace/35.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/35.flash_ctrl_otp_reset.1142841664
Short name	T931
Test name
Test status
Simulation time	77267500 ps
CPU time	136.01 seconds
Started	Aug 13 06:21:33 PM PDT 24
Finished	Aug 13 06:23:49 PM PDT 24
Peak memory	264960 kb
Host	smart-e2b53e9f-fbf9-41a3-81e2-31d64f05e435
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142841664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_o tp_reset.1142841664
Directory	/workspace/35.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/35.flash_ctrl_rw_evict.4135442583
Short name	T995
Test name
Test status
Simulation time	29941700 ps
CPU time	28.8 seconds
Started	Aug 13 06:21:26 PM PDT 24
Finished	Aug 13 06:21:55 PM PDT 24
Peak memory	274172 kb
Host	smart-1293f557-1156-4fa5-8495-b72d1fcd7796
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135442583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.fl ash_ctrl_rw_evict.4135442583
Directory	/workspace/35.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/35.flash_ctrl_sec_info_access.963007354
Short name	T727
Test name
Test status
Simulation time	5859660200 ps
CPU time	68.24 seconds
Started	Aug 13 06:21:28 PM PDT 24
Finished	Aug 13 06:22:36 PM PDT 24
Peak memory	265648 kb
Host	smart-ff89f152-f423-4b64-b4bd-cde90b91c260
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=963007354 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.963007354
Directory	/workspace/35.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/35.flash_ctrl_smoke.1937996850
Short name	T647
Test name
Test status
Simulation time	43179800 ps
CPU time	217.07 seconds
Started	Aug 13 06:21:34 PM PDT 24
Finished	Aug 13 06:25:11 PM PDT 24
Peak memory	279848 kb
Host	smart-bc7b3fdb-7021-4961-9dcb-7fa9b540c31c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1937996850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.1937996850
Directory	/workspace/35.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/36.flash_ctrl_alert_test.3795039805
Short name	T581
Test name
Test status
Simulation time	44142700 ps
CPU time	13.59 seconds
Started	Aug 13 06:21:34 PM PDT 24
Finished	Aug 13 06:21:48 PM PDT 24
Peak memory	258744 kb
Host	smart-f60c2fc9-e045-4de2-ab59-43d3f7b8f7cf
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795039805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test. 3795039805
Directory	/workspace/36.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/36.flash_ctrl_connect.3182095595
Short name	T1079
Test name
Test status
Simulation time	25708500 ps
CPU time	15.6 seconds
Started	Aug 13 06:21:37 PM PDT 24
Finished	Aug 13 06:21:52 PM PDT 24
Peak memory	283672 kb
Host	smart-18024a9a-db1d-40ee-9256-67a7064eee42
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3182095595 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.3182095595
Directory	/workspace/36.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/36.flash_ctrl_disable.1984982484
Short name	T93
Test name
Test status
Simulation time	10118200 ps
CPU time	21.79 seconds
Started	Aug 13 06:21:34 PM PDT 24
Finished	Aug 13 06:21:56 PM PDT 24
Peak memory	266884 kb
Host	smart-ebf2d4dd-18d4-47f6-8a68-f1a8df40f1e2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984982484 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_disable.1984982484
Directory	/workspace/36.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/36.flash_ctrl_hw_sec_otp.2198633148
Short name	T1018
Test name
Test status
Simulation time	4685148800 ps
CPU time	198.49 seconds
Started	Aug 13 06:21:32 PM PDT 24
Finished	Aug 13 06:24:51 PM PDT 24
Peak memory	263656 kb
Host	smart-6a78a35a-a285-4d0a-93a3-2acc4c62bc0b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198633148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_ hw_sec_otp.2198633148
Directory	/workspace/36.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/36.flash_ctrl_intr_rd.2630917869
Short name	T1061
Test name
Test status
Simulation time	1154369600 ps
CPU time	136.83 seconds
Started	Aug 13 06:21:26 PM PDT 24
Finished	Aug 13 06:23:43 PM PDT 24
Peak memory	294808 kb
Host	smart-2e2f2c62-cf74-4581-b84e-720f126eff78
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630917869 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fla sh_ctrl_intr_rd.2630917869
Directory	/workspace/36.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.3590919213
Short name	T50
Test name
Test status
Simulation time	56597154500 ps
CPU time	476.44 seconds
Started	Aug 13 06:21:32 PM PDT 24
Finished	Aug 13 06:29:28 PM PDT 24
Peak memory	291636 kb
Host	smart-d0120932-ed67-4292-a4f3-a681fd1a4c2e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590919213 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd_slow_flash.3590919213
Directory	/workspace/36.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/36.flash_ctrl_otp_reset.2056340156
Short name	T147
Test name
Test status
Simulation time	144561300 ps
CPU time	133.08 seconds
Started	Aug 13 06:21:27 PM PDT 24
Finished	Aug 13 06:23:40 PM PDT 24
Peak memory	260708 kb
Host	smart-6c16f811-a6df-4d40-9f01-c52de9ea8139
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056340156 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_o tp_reset.2056340156
Directory	/workspace/36.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/36.flash_ctrl_rw_evict.1553502743
Short name	T210
Test name
Test status
Simulation time	28516100 ps
CPU time	31.56 seconds
Started	Aug 13 06:21:35 PM PDT 24
Finished	Aug 13 06:22:06 PM PDT 24
Peak memory	274208 kb
Host	smart-26d9149f-7ac6-496d-b647-88b4250e1e27
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553502743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.fl ash_ctrl_rw_evict.1553502743
Directory	/workspace/36.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/36.flash_ctrl_rw_evict_all_en.491518708
Short name	T404
Test name
Test status
Simulation time	167297200 ps
CPU time	28.8 seconds
Started	Aug 13 06:21:35 PM PDT 24
Finished	Aug 13 06:22:04 PM PDT 24
Peak memory	275544 kb
Host	smart-01a7cd00-6399-4075-b18d-84b2d8d4336f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491518708 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict_all_en.491518708
Directory	/workspace/36.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/36.flash_ctrl_sec_info_access.4248917781
Short name	T354
Test name
Test status
Simulation time	9864185700 ps
CPU time	75.03 seconds
Started	Aug 13 06:21:34 PM PDT 24
Finished	Aug 13 06:22:49 PM PDT 24
Peak memory	265300 kb
Host	smart-b048042b-4e22-4710-8dae-312c8f4b92d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4248917781 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.4248917781
Directory	/workspace/36.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/36.flash_ctrl_smoke.960910256
Short name	T135
Test name
Test status
Simulation time	21594600 ps
CPU time	148.81 seconds
Started	Aug 13 06:21:26 PM PDT 24
Finished	Aug 13 06:23:55 PM PDT 24
Peak memory	278616 kb
Host	smart-7bafcb4d-6407-4582-a7ae-030671d9e97b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=960910256 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.960910256
Directory	/workspace/36.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/37.flash_ctrl_alert_test.4257392535
Short name	T692
Test name
Test status
Simulation time	65027300 ps
CPU time	13.86 seconds
Started	Aug 13 06:21:43 PM PDT 24
Finished	Aug 13 06:21:57 PM PDT 24
Peak memory	265708 kb
Host	smart-49a86cdc-9cca-41f4-a5f4-a215c8b3db31
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257392535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test. 4257392535
Directory	/workspace/37.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/37.flash_ctrl_connect.3905758241
Short name	T929
Test name
Test status
Simulation time	23687100 ps
CPU time	15.86 seconds
Started	Aug 13 06:21:43 PM PDT 24
Finished	Aug 13 06:21:59 PM PDT 24
Peak memory	283572 kb
Host	smart-dd301f7e-7812-4041-a41d-d3a9423c27d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3905758241 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.3905758241
Directory	/workspace/37.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/37.flash_ctrl_disable.3318958433
Short name	T754
Test name
Test status
Simulation time	22000000 ps
CPU time	22.09 seconds
Started	Aug 13 06:21:41 PM PDT 24
Finished	Aug 13 06:22:03 PM PDT 24
Peak memory	274068 kb
Host	smart-c52f461e-bd82-4667-ad08-be0f575655de
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318958433 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_disable.3318958433
Directory	/workspace/37.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/37.flash_ctrl_intr_rd.1589404671
Short name	T943
Test name
Test status
Simulation time	2687220600 ps
CPU time	220.87 seconds
Started	Aug 13 06:21:34 PM PDT 24
Finished	Aug 13 06:25:15 PM PDT 24
Peak memory	285736 kb
Host	smart-df57b182-7bf4-42ca-9ed4-6c746fdfbeb3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589404671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.fla sh_ctrl_intr_rd.1589404671
Directory	/workspace/37.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/37.flash_ctrl_otp_reset.1072013620
Short name	T554
Test name
Test status
Simulation time	86645000 ps
CPU time	133.46 seconds
Started	Aug 13 06:21:37 PM PDT 24
Finished	Aug 13 06:23:51 PM PDT 24
Peak memory	265252 kb
Host	smart-2d695b90-9fd1-4eed-8721-4dc2f783d455
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072013620 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_o tp_reset.1072013620
Directory	/workspace/37.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/37.flash_ctrl_rw_evict.85766605
Short name	T665
Test name
Test status
Simulation time	45241800 ps
CPU time	32.1 seconds
Started	Aug 13 06:21:35 PM PDT 24
Finished	Aug 13 06:22:07 PM PDT 24
Peak memory	276332 kb
Host	smart-69545630-dec5-48d9-a913-165089d3c31a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85766605 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ =flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flas h_ctrl_rw_evict.85766605
Directory	/workspace/37.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/37.flash_ctrl_rw_evict_all_en.3737516168
Short name	T393
Test name
Test status
Simulation time	113986000 ps
CPU time	28.5 seconds
Started	Aug 13 06:21:35 PM PDT 24
Finished	Aug 13 06:22:04 PM PDT 24
Peak memory	275588 kb
Host	smart-b31b5476-02d5-4503-99cf-b62a9a2b15b7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737516168 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict_all_en.3737516168
Directory	/workspace/37.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/37.flash_ctrl_sec_info_access.4186800543
Short name	T1013
Test name
Test status
Simulation time	578252300 ps
CPU time	50.8 seconds
Started	Aug 13 06:21:41 PM PDT 24
Finished	Aug 13 06:22:32 PM PDT 24
Peak memory	263868 kb
Host	smart-15444765-4b18-4666-9df9-a319f344f082
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4186800543 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.4186800543
Directory	/workspace/37.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/37.flash_ctrl_smoke.875556828
Short name	T723
Test name
Test status
Simulation time	55478100 ps
CPU time	52.5 seconds
Started	Aug 13 06:21:35 PM PDT 24
Finished	Aug 13 06:22:28 PM PDT 24
Peak memory	271840 kb
Host	smart-7aa72412-6d8b-453b-9513-a76f4ca29a71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=875556828 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.875556828
Directory	/workspace/37.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/38.flash_ctrl_alert_test.1121997170
Short name	T802
Test name
Test status
Simulation time	60762300 ps
CPU time	13.7 seconds
Started	Aug 13 06:21:49 PM PDT 24
Finished	Aug 13 06:22:03 PM PDT 24
Peak memory	258712 kb
Host	smart-d3f6d225-d8c4-492a-a808-d0e52788d237
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121997170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test. 1121997170
Directory	/workspace/38.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/38.flash_ctrl_connect.1598882595
Short name	T938
Test name
Test status
Simulation time	23343500 ps
CPU time	15.72 seconds
Started	Aug 13 06:21:40 PM PDT 24
Finished	Aug 13 06:21:56 PM PDT 24
Peak memory	284804 kb
Host	smart-668ec43a-0984-4a7a-b85e-8b8bcd9790a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1598882595 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.1598882595
Directory	/workspace/38.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/38.flash_ctrl_disable.816419628
Short name	T431
Test name
Test status
Simulation time	10428600 ps
CPU time	20.88 seconds
Started	Aug 13 06:21:42 PM PDT 24
Finished	Aug 13 06:22:03 PM PDT 24
Peak memory	274180 kb
Host	smart-4d96031b-1a1f-431e-98ab-38154eb29813
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816419628 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_disable.816419628
Directory	/workspace/38.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/38.flash_ctrl_hw_sec_otp.1648619074
Short name	T1081
Test name
Test status
Simulation time	2283423200 ps
CPU time	73.59 seconds
Started	Aug 13 06:21:42 PM PDT 24
Finished	Aug 13 06:22:55 PM PDT 24
Peak memory	262740 kb
Host	smart-de01a8f1-6d70-4359-bdda-85e4bba7b686
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648619074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_ hw_sec_otp.1648619074
Directory	/workspace/38.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/38.flash_ctrl_intr_rd.4167223201
Short name	T1100
Test name
Test status
Simulation time	795192600 ps
CPU time	137.47 seconds
Started	Aug 13 06:21:43 PM PDT 24
Finished	Aug 13 06:24:01 PM PDT 24
Peak memory	294692 kb
Host	smart-25693574-3fb5-49f1-9e36-edef29e0d462
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167223201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.fla sh_ctrl_intr_rd.4167223201
Directory	/workspace/38.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/38.flash_ctrl_intr_rd_slow_flash.74351996
Short name	T138
Test name
Test status
Simulation time	94555991800 ps
CPU time	156.66 seconds
Started	Aug 13 06:21:41 PM PDT 24
Finished	Aug 13 06:24:18 PM PDT 24
Peak memory	293548 kb
Host	smart-d8aef2bf-c470-45ef-a76e-f3bfddd25b50
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74351996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd_slow_flash.74351996
Directory	/workspace/38.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/38.flash_ctrl_otp_reset.242031623
Short name	T763
Test name
Test status
Simulation time	149098100 ps
CPU time	129.96 seconds
Started	Aug 13 06:21:39 PM PDT 24
Finished	Aug 13 06:23:49 PM PDT 24
Peak memory	260532 kb
Host	smart-8ca8a242-ec04-49d4-83a0-7132a807a8a3
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242031623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_ot p_reset.242031623
Directory	/workspace/38.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/38.flash_ctrl_rw_evict.57976053
Short name	T409
Test name
Test status
Simulation time	44734600 ps
CPU time	28.99 seconds
Started	Aug 13 06:21:41 PM PDT 24
Finished	Aug 13 06:22:10 PM PDT 24
Peak memory	276184 kb
Host	smart-93bcf627-e6c9-49bc-8765-815ae685746c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57976053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ =flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flas h_ctrl_rw_evict.57976053
Directory	/workspace/38.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/38.flash_ctrl_sec_info_access.4177265247
Short name	T355
Test name
Test status
Simulation time	3628825800 ps
CPU time	81.36 seconds
Started	Aug 13 06:21:43 PM PDT 24
Finished	Aug 13 06:23:05 PM PDT 24
Peak memory	263788 kb
Host	smart-01911d9b-8186-4c12-a922-a98c592d227f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4177265247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.4177265247
Directory	/workspace/38.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/38.flash_ctrl_smoke.3185672922
Short name	T487
Test name
Test status
Simulation time	72690000 ps
CPU time	52.33 seconds
Started	Aug 13 06:21:42 PM PDT 24
Finished	Aug 13 06:22:34 PM PDT 24
Peak memory	271732 kb
Host	smart-93f7bce7-5db4-47b5-8f4a-6f43247dd7eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3185672922 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.3185672922
Directory	/workspace/38.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/39.flash_ctrl_alert_test.2506978201
Short name	T532
Test name
Test status
Simulation time	40961500 ps
CPU time	14.01 seconds
Started	Aug 13 06:21:56 PM PDT 24
Finished	Aug 13 06:22:10 PM PDT 24
Peak memory	258896 kb
Host	smart-710b996b-53df-4bcf-813a-3cdded1ad595
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506978201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test. 2506978201
Directory	/workspace/39.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/39.flash_ctrl_connect.3540821911
Short name	T950
Test name
Test status
Simulation time	20692700 ps
CPU time	16.14 seconds
Started	Aug 13 06:21:57 PM PDT 24
Finished	Aug 13 06:22:14 PM PDT 24
Peak memory	284800 kb
Host	smart-99cb7307-5e8f-4547-9fec-d318ad92d89b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3540821911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.3540821911
Directory	/workspace/39.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/39.flash_ctrl_disable.716744557
Short name	T96
Test name
Test status
Simulation time	20728500 ps
CPU time	20.69 seconds
Started	Aug 13 06:21:57 PM PDT 24
Finished	Aug 13 06:22:17 PM PDT 24
Peak memory	275404 kb
Host	smart-3dae7abc-0200-4699-bdf7-9b7b13784b6a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716744557 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_disable.716744557
Directory	/workspace/39.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/39.flash_ctrl_hw_sec_otp.260116198
Short name	T496
Test name
Test status
Simulation time	3839912200 ps
CPU time	34.67 seconds
Started	Aug 13 06:21:49 PM PDT 24
Finished	Aug 13 06:22:24 PM PDT 24
Peak memory	261184 kb
Host	smart-d907d2c6-6838-497d-b1c3-79f8ebbd9598
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260116198 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_h w_sec_otp.260116198
Directory	/workspace/39.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/39.flash_ctrl_intr_rd.2318096581
Short name	T876
Test name
Test status
Simulation time	6887484000 ps
CPU time	217.76 seconds
Started	Aug 13 06:21:50 PM PDT 24
Finished	Aug 13 06:25:28 PM PDT 24
Peak memory	291468 kb
Host	smart-731b5560-ada3-4edc-aea2-684c7fc73e75
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318096581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fla sh_ctrl_intr_rd.2318096581
Directory	/workspace/39.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/39.flash_ctrl_intr_rd_slow_flash.3284900355
Short name	T683
Test name
Test status
Simulation time	8150633000 ps
CPU time	156.95 seconds
Started	Aug 13 06:21:48 PM PDT 24
Finished	Aug 13 06:24:25 PM PDT 24
Peak memory	285856 kb
Host	smart-293c71bd-793a-45b0-bbff-63f70a9c07fd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284900355 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd_slow_flash.3284900355
Directory	/workspace/39.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/39.flash_ctrl_otp_reset.2265318156
Short name	T180
Test name
Test status
Simulation time	129911700 ps
CPU time	110.69 seconds
Started	Aug 13 06:21:48 PM PDT 24
Finished	Aug 13 06:23:39 PM PDT 24
Peak memory	265488 kb
Host	smart-b610fe2c-a7ee-476e-8dee-120eebd7313e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265318156 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_o tp_reset.2265318156
Directory	/workspace/39.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/39.flash_ctrl_rw_evict.1402698081
Short name	T521
Test name
Test status
Simulation time	103940300 ps
CPU time	30.57 seconds
Started	Aug 13 06:21:49 PM PDT 24
Finished	Aug 13 06:22:20 PM PDT 24
Peak memory	276216 kb
Host	smart-057a1a79-7e48-4693-a0b0-a64192ee95a6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402698081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.fl ash_ctrl_rw_evict.1402698081
Directory	/workspace/39.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/39.flash_ctrl_rw_evict_all_en.345767165
Short name	T410
Test name
Test status
Simulation time	28297500 ps
CPU time	29.07 seconds
Started	Aug 13 06:21:48 PM PDT 24
Finished	Aug 13 06:22:17 PM PDT 24
Peak memory	275528 kb
Host	smart-6c132f59-1f92-4d9d-a9f3-d8e963872bd6
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345767165 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict_all_en.345767165
Directory	/workspace/39.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/39.flash_ctrl_sec_info_access.268572175
Short name	T673
Test name
Test status
Simulation time	1952850200 ps
CPU time	59.14 seconds
Started	Aug 13 06:21:55 PM PDT 24
Finished	Aug 13 06:22:54 PM PDT 24
Peak memory	263276 kb
Host	smart-b2121cea-dcaf-40ec-acbf-cd350fae986f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=268572175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.268572175
Directory	/workspace/39.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/39.flash_ctrl_smoke.3469341633
Short name	T358
Test name
Test status
Simulation time	19627700 ps
CPU time	99.8 seconds
Started	Aug 13 06:21:49 PM PDT 24
Finished	Aug 13 06:23:29 PM PDT 24
Peak memory	277444 kb
Host	smart-03d81f36-67ce-4db7-a4a1-97a32ff70c30
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3469341633 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.3469341633
Directory	/workspace/39.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/4.flash_ctrl_alert_test.4086540889
Short name	T824
Test name
Test status
Simulation time	41415700 ps
CPU time	13.66 seconds
Started	Aug 13 06:16:49 PM PDT 24
Finished	Aug 13 06:17:02 PM PDT 24
Peak memory	258776 kb
Host	smart-5def250d-5453-49a0-9f60-1418bdafadb4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086540889 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.4 086540889
Directory	/workspace/4.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/4.flash_ctrl_connect.3454689152
Short name	T1033
Test name
Test status
Simulation time	31041400 ps
CPU time	15.64 seconds
Started	Aug 13 06:16:27 PM PDT 24
Finished	Aug 13 06:16:43 PM PDT 24
Peak memory	283532 kb
Host	smart-5540469e-0227-4a34-a97a-158f333cb2be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3454689152 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.3454689152
Directory	/workspace/4.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/4.flash_ctrl_derr_detect.3460295417
Short name	T655
Test name
Test status
Simulation time	1320710100 ps
CPU time	201.6 seconds
Started	Aug 13 06:16:21 PM PDT 24
Finished	Aug 13 06:19:43 PM PDT 24
Peak memory	281820 kb
Host	smart-92c55de3-75a5-4c21-80cf-e52d2b6bef82
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200 +rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460295417 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_derr_detect.3460295417
Directory	/workspace/4.flash_ctrl_derr_detect/latest

Test location	/workspace/coverage/default/4.flash_ctrl_disable.2311694051
Short name	T148
Test name
Test status
Simulation time	20886600 ps
CPU time	20.97 seconds
Started	Aug 13 06:16:30 PM PDT 24
Finished	Aug 13 06:16:52 PM PDT 24
Peak memory	274068 kb
Host	smart-038345c4-da96-425e-b07a-0ae1447ec6c7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311694051 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_disable.2311694051
Directory	/workspace/4.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/4.flash_ctrl_erase_suspend.769444535
Short name	T161
Test name
Test status
Simulation time	4908669300 ps
CPU time	449.42 seconds
Started	Aug 13 06:16:24 PM PDT 24
Finished	Aug 13 06:23:54 PM PDT 24
Peak memory	264012 kb
Host	smart-436dec29-2d96-405b-b90c-a77a40dc6a8c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=769444535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.769444535
Directory	/workspace/4.flash_ctrl_erase_suspend/latest

Test location	/workspace/coverage/default/4.flash_ctrl_error_mp.2004813028
Short name	T714
Test name
Test status
Simulation time	8106926800 ps
CPU time	2138.16 seconds
Started	Aug 13 06:16:22 PM PDT 24
Finished	Aug 13 06:52:01 PM PDT 24
Peak memory	265704 kb
Host	smart-df1c79ae-c6bf-4604-8917-c25571a1a3fc
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2004813028 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_mp.2004813028
Directory	/workspace/4.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/4.flash_ctrl_error_prog_type.1118663067
Short name	T839
Test name
Test status
Simulation time	2329085000 ps
CPU time	1881.26 seconds
Started	Aug 13 06:16:23 PM PDT 24
Finished	Aug 13 06:47:44 PM PDT 24
Peak memory	263784 kb
Host	smart-7a28ac72-cb35-4cca-861a-6bef34b81279
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118663067 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 4.flash_ctrl_error_prog_type.1118663067
Directory	/workspace/4.flash_ctrl_error_prog_type/latest

Test location	/workspace/coverage/default/4.flash_ctrl_error_prog_win.3943920086
Short name	T292
Test name
Test status
Simulation time	320030100 ps
CPU time	776.47 seconds
Started	Aug 13 06:16:21 PM PDT 24
Finished	Aug 13 06:29:18 PM PDT 24
Peak memory	273548 kb
Host	smart-fb15c7bf-37fe-49cd-b768-0198f95715f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3943920086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.3943920086
Directory	/workspace/4.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/4.flash_ctrl_fetch_code.1086598457
Short name	T1020
Test name
Test status
Simulation time	4472489800 ps
CPU time	25.3 seconds
Started	Aug 13 06:16:22 PM PDT 24
Finished	Aug 13 06:16:47 PM PDT 24
Peak memory	263120 kb
Host	smart-7843e55d-a207-492c-9f03-f9b3eabf8b8e
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086598457 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetch_code.1086598457
Directory	/workspace/4.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/4.flash_ctrl_fs_sup.4199709039
Short name	T76
Test name
Test status
Simulation time	1606419200 ps
CPU time	39.76 seconds
Started	Aug 13 06:16:31 PM PDT 24
Finished	Aug 13 06:17:11 PM PDT 24
Peak memory	263488 kb
Host	smart-6a393627-9520-4e69-9ff5-ca986f5d3df0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199709039 -assert nopostproc +UVM_TESTNAME=flash_ctrl_bas e_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 4.flash_ctrl_fs_sup.4199709039
Directory	/workspace/4.flash_ctrl_fs_sup/latest

Test location	/workspace/coverage/default/4.flash_ctrl_full_mem_access.1472747203
Short name	T953
Test name
Test status
Simulation time	203465881900 ps
CPU time	4244.16 seconds
Started	Aug 13 06:16:22 PM PDT 24
Finished	Aug 13 07:27:07 PM PDT 24
Peak memory	263044 kb
Host	smart-afd882e7-6bb9-47e6-94b1-29d616cde2c1
User	root
Command	/workspace/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472747203 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_c trl_full_mem_access.1472747203
Directory	/workspace/4.flash_ctrl_full_mem_access/latest

Test location	/workspace/coverage/default/4.flash_ctrl_host_ctrl_arb.1620988274
Short name	T630
Test name
Test status
Simulation time	511677986700 ps
CPU time	2242.62 seconds
Started	Aug 13 06:16:23 PM PDT 24
Finished	Aug 13 06:53:46 PM PDT 24
Peak memory	264612 kb
Host	smart-899559d0-f540-4e6b-b485-c66e865a551a
User	root
Command	/workspace/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620988274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE ST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 4.flash_ctrl_host_ctrl_arb.1620988274
Directory	/workspace/4.flash_ctrl_host_ctrl_arb/latest

Test location	/workspace/coverage/default/4.flash_ctrl_host_dir_rd.2150566497
Short name	T869
Test name
Test status
Simulation time	74858600 ps
CPU time	24.36 seconds
Started	Aug 13 06:16:15 PM PDT 24
Finished	Aug 13 06:16:40 PM PDT 24
Peak memory	265840 kb
Host	smart-9d025225-772c-4181-b970-981593b7ec4d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2150566497 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.2150566497
Directory	/workspace/4.flash_ctrl_host_dir_rd/latest

Test location	/workspace/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.3330129555
Short name	T1063
Test name
Test status
Simulation time	10057327200 ps
CPU time	71.02 seconds
Started	Aug 13 06:16:41 PM PDT 24
Finished	Aug 13 06:17:52 PM PDT 24
Peak memory	265776 kb
Host	smart-76b2dce3-f18b-406f-b8a4-2de7793d3641
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330129555 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.3330129555
Directory	/workspace/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/4.flash_ctrl_hw_read_seed_err.2680680929
Short name	T874
Test name
Test status
Simulation time	15228400 ps
CPU time	13.31 seconds
Started	Aug 13 06:16:40 PM PDT 24
Finished	Aug 13 06:16:54 PM PDT 24
Peak memory	265204 kb
Host	smart-37b5428c-6e9e-4aca-b87a-93304c9d85fe
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680680929 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_read_seed_err.2680680929
Directory	/workspace/4.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/4.flash_ctrl_hw_sec_otp.3488962175
Short name	T1067
Test name
Test status
Simulation time	10073547100 ps
CPU time	76.67 seconds
Started	Aug 13 06:16:12 PM PDT 24
Finished	Aug 13 06:17:29 PM PDT 24
Peak memory	263712 kb
Host	smart-847f0cb7-fb01-4ec2-b48c-abcf61c9f9c5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488962175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_h w_sec_otp.3488962175
Directory	/workspace/4.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/4.flash_ctrl_integrity.1065673246
Short name	T46
Test name
Test status
Simulation time	3699422900 ps
CPU time	587.53 seconds
Started	Aug 13 06:16:29 PM PDT 24
Finished	Aug 13 06:26:17 PM PDT 24
Peak memory	330568 kb
Host	smart-51be2267-6f37-43cb-ae8b-f3a17a7ed55d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065673246 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 4.flash_ctrl_integrity.1065673246
Directory	/workspace/4.flash_ctrl_integrity/latest

Test location	/workspace/coverage/default/4.flash_ctrl_intr_rd.265124270
Short name	T320
Test name
Test status
Simulation time	2791815900 ps
CPU time	180.95 seconds
Started	Aug 13 06:16:32 PM PDT 24
Finished	Aug 13 06:19:33 PM PDT 24
Peak memory	291556 kb
Host	smart-2e9b55b6-5a94-46cc-aeb9-5c4e2cbbb74d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265124270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash _ctrl_intr_rd.265124270
Directory	/workspace/4.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/4.flash_ctrl_intr_rd_slow_flash.219893005
Short name	T660
Test name
Test status
Simulation time	48034786600 ps
CPU time	302.02 seconds
Started	Aug 13 06:16:30 PM PDT 24
Finished	Aug 13 06:21:32 PM PDT 24
Peak memory	285612 kb
Host	smart-584b3ba2-ba27-4ab0-bee5-323e6c844761
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219893005 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd_slow_flash.219893005
Directory	/workspace/4.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/4.flash_ctrl_intr_wr.1229461749
Short name	T279
Test name
Test status
Simulation time	4040409800 ps
CPU time	63.86 seconds
Started	Aug 13 06:16:31 PM PDT 24
Finished	Aug 13 06:17:35 PM PDT 24
Peak memory	261208 kb
Host	smart-5eae4e58-a357-47c9-8da2-b01c5840dc99
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229461749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 4.flash_ctrl_intr_wr.1229461749
Directory	/workspace/4.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_intr_wr_slow_flash.1628641804
Short name	T418
Test name
Test status
Simulation time	156141401500 ps
CPU time	159.64 seconds
Started	Aug 13 06:16:30 PM PDT 24
Finished	Aug 13 06:19:10 PM PDT 24
Peak memory	260888 kb
Host	smart-da215272-b778-4cb7-8a89-d256a1f56dfb
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162 8641804 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.1628641804
Directory	/workspace/4.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/4.flash_ctrl_invalid_op.577328830
Short name	T832
Test name
Test status
Simulation time	2550683100 ps
CPU time	94.5 seconds
Started	Aug 13 06:16:22 PM PDT 24
Finished	Aug 13 06:17:57 PM PDT 24
Peak memory	261212 kb
Host	smart-150963bb-caac-4da7-a2a5-d0caec314d2f
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577328830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.577328830
Directory	/workspace/4.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/4.flash_ctrl_lcmgr_intg.138251674
Short name	T288
Test name
Test status
Simulation time	25987200 ps
CPU time	13.42 seconds
Started	Aug 13 06:16:41 PM PDT 24
Finished	Aug 13 06:16:54 PM PDT 24
Peak memory	260736 kb
Host	smart-8e061880-f5e9-46e4-bc0b-efcae1fbe9f4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138251674 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 4.flash_ctrl_lcmgr_intg.138251674
Directory	/workspace/4.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/4.flash_ctrl_mid_op_rst.4282062176
Short name	T78
Test name
Test status
Simulation time	1287119600 ps
CPU time	69.91 seconds
Started	Aug 13 06:16:22 PM PDT 24
Finished	Aug 13 06:17:32 PM PDT 24
Peak memory	261328 kb
Host	smart-2db5c362-e538-4e96-a51c-0cf75cd961e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4282062176 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.4282062176
Directory	/workspace/4.flash_ctrl_mid_op_rst/latest

Test location	/workspace/coverage/default/4.flash_ctrl_mp_regions.3239339468
Short name	T117
Test name
Test status
Simulation time	191344238100 ps
CPU time	1029.51 seconds
Started	Aug 13 06:16:19 PM PDT 24
Finished	Aug 13 06:33:28 PM PDT 24
Peak memory	275424 kb
Host	smart-454eb7ee-64e1-4d5b-a4bb-4990a5a36479
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239339468 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mp_regions.3239339468
Directory	/workspace/4.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/4.flash_ctrl_otp_reset.186492884
Short name	T1019
Test name
Test status
Simulation time	84625500 ps
CPU time	131.05 seconds
Started	Aug 13 06:16:21 PM PDT 24
Finished	Aug 13 06:18:32 PM PDT 24
Peak memory	265660 kb
Host	smart-07163f5d-977d-4818-8179-07e5ff5aee1c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186492884 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_otp _reset.186492884
Directory	/workspace/4.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/4.flash_ctrl_oversize_error.3202438467
Short name	T589
Test name
Test status
Simulation time	5501989300 ps
CPU time	169.69 seconds
Started	Aug 13 06:16:28 PM PDT 24
Finished	Aug 13 06:19:18 PM PDT 24
Peak memory	282368 kb
Host	smart-e4189342-3777-4765-8548-5ef25275a7ad
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=100 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202438467 -assert no postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_oversize_error.3202438467
Directory	/workspace/4.flash_ctrl_oversize_error/latest

Test location	/workspace/coverage/default/4.flash_ctrl_phy_ack_consistency.1170724140
Short name	T90
Test name
Test status
Simulation time	29446200 ps
CPU time	13.86 seconds
Started	Aug 13 06:16:41 PM PDT 24
Finished	Aug 13 06:16:55 PM PDT 24
Peak memory	265628 kb
Host	smart-a3f149b2-f3d8-4596-890b-e7fe864fbe59
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8 +otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_ check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1170724140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.1170724140
Directory	/workspace/4.flash_ctrl_phy_ack_consistency/latest

Test location	/workspace/coverage/default/4.flash_ctrl_phy_arb.497330236
Short name	T1048
Test name
Test status
Simulation time	219892700 ps
CPU time	239.15 seconds
Started	Aug 13 06:16:15 PM PDT 24
Finished	Aug 13 06:20:15 PM PDT 24
Peak memory	263700 kb
Host	smart-cb818f09-eb9c-4856-8042-c233580a682c
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=497330236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.497330236
Directory	/workspace/4.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/4.flash_ctrl_phy_host_grant_err.398509599
Short name	T417
Test name
Test status
Simulation time	117193700 ps
CPU time	13.68 seconds
Started	Aug 13 06:16:49 PM PDT 24
Finished	Aug 13 06:17:03 PM PDT 24
Peak memory	265572 kb
Host	smart-7da3da07-7a01-4f5f-92dc-761bf9d4db09
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398509599 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.398509599
Directory	/workspace/4.flash_ctrl_phy_host_grant_err/latest

Test location	/workspace/coverage/default/4.flash_ctrl_prog_reset.350508292
Short name	T969
Test name
Test status
Simulation time	5429260500 ps
CPU time	197.55 seconds
Started	Aug 13 06:16:30 PM PDT 24
Finished	Aug 13 06:19:47 PM PDT 24
Peak memory	261216 kb
Host	smart-31050f46-aadd-4d0d-a7ea-c2b79ade8b18
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350508292 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 4.flash_ctrl_prog_reset.350508292
Directory	/workspace/4.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rand_ops.303273945
Short name	T719
Test name
Test status
Simulation time	155021800 ps
CPU time	875.66 seconds
Started	Aug 13 06:16:16 PM PDT 24
Finished	Aug 13 06:30:51 PM PDT 24
Peak memory	283452 kb
Host	smart-48cfe24b-0830-477b-809c-e66f2aff7783
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=303273945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.303273945
Directory	/workspace/4.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rd_buff_evict.2239135270
Short name	T1000
Test name
Test status
Simulation time	1144107000 ps
CPU time	115.86 seconds
Started	Aug 13 06:16:10 PM PDT 24
Finished	Aug 13 06:18:06 PM PDT 24
Peak memory	263276 kb
Host	smart-fb7175c8-4050-4657-b47b-1bb677472ca1
User	root
Command	/workspace/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2239135270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.2239135270
Directory	/workspace/4.flash_ctrl_rd_buff_evict/latest

Test location	/workspace/coverage/default/4.flash_ctrl_re_evict.796827956
Short name	T549
Test name
Test status
Simulation time	119679100 ps
CPU time	34.44 seconds
Started	Aug 13 06:16:33 PM PDT 24
Finished	Aug 13 06:17:08 PM PDT 24
Peak memory	276260 kb
Host	smart-94230e8c-fed2-4fa4-9a52-d11e524702cd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796827956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas h_ctrl_re_evict.796827956
Directory	/workspace/4.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.2568834762
Short name	T774
Test name
Test status
Simulation time	18515600 ps
CPU time	22.8 seconds
Started	Aug 13 06:16:23 PM PDT 24
Finished	Aug 13 06:16:46 PM PDT 24
Peak memory	265912 kb
Host	smart-54deb72d-fa8c-431d-8672-60571ba5c209
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568834762 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_derr.2568834762
Directory	/workspace/4.flash_ctrl_read_word_sweep_derr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_read_word_sweep_serr.3403621741
Short name	T657
Test name
Test status
Simulation time	22926900 ps
CPU time	22.58 seconds
Started	Aug 13 06:16:21 PM PDT 24
Finished	Aug 13 06:16:44 PM PDT 24
Peak memory	265388 kb
Host	smart-37c440bd-5eba-4f37-a542-e4f4dd3e44c3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli - do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403621741 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla sh_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fl ash_ctrl_read_word_sweep_serr.3403621741
Directory	/workspace/4.flash_ctrl_read_word_sweep_serr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_ro.2629137982
Short name	T919
Test name
Test status
Simulation time	1016974200 ps
CPU time	113.23 seconds
Started	Aug 13 06:16:23 PM PDT 24
Finished	Aug 13 06:18:16 PM PDT 24
Peak memory	292084 kb
Host	smart-ab77f3b8-f8c9-422e-87f0-1241714b38e3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629137982 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 4.flash_ctrl_ro.2629137982
Directory	/workspace/4.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/4.flash_ctrl_ro_derr.4130693994
Short name	T575
Test name
Test status
Simulation time	1267491000 ps
CPU time	154.38 seconds
Started	Aug 13 06:16:22 PM PDT 24
Finished	Aug 13 06:18:56 PM PDT 24
Peak memory	282304 kb
Host	smart-51fd2c33-315a-404f-822a-7779b9b180be
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4130693994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.4130693994
Directory	/workspace/4.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_ro_serr.1241860718
Short name	T219
Test name
Test status
Simulation time	741275400 ps
CPU time	156.7 seconds
Started	Aug 13 06:16:22 PM PDT 24
Finished	Aug 13 06:18:59 PM PDT 24
Peak memory	294900 kb
Host	smart-c1a398c3-2516-4dfc-acc8-bfcf1106aa9d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241860718 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 4.flash_ctrl_ro_serr.1241860718
Directory	/workspace/4.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rw.1873541555
Short name	T888
Test name
Test status
Simulation time	18285354800 ps
CPU time	574.48 seconds
Started	Aug 13 06:16:23 PM PDT 24
Finished	Aug 13 06:25:57 PM PDT 24
Peak memory	310204 kb
Host	smart-8d324e2b-6aea-467c-8295-942d558bdcc3
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873541555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 4.flash_ctrl_rw.1873541555
Directory	/workspace/4.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rw_evict.3217721664
Short name	T899
Test name
Test status
Simulation time	64385600 ps
CPU time	29.32 seconds
Started	Aug 13 06:16:30 PM PDT 24
Finished	Aug 13 06:16:59 PM PDT 24
Peak memory	274176 kb
Host	smart-b87f5804-e553-4d10-bd85-e53487905e81
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217721664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.fla sh_ctrl_rw_evict.3217721664
Directory	/workspace/4.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rw_evict_all_en.400368440
Short name	T455
Test name
Test status
Simulation time	42244000 ps
CPU time	28.47 seconds
Started	Aug 13 06:16:30 PM PDT 24
Finished	Aug 13 06:16:59 PM PDT 24
Peak memory	274188 kb
Host	smart-5fc0eb35-9104-412b-87ff-083c19149ef1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400368440 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict_all_en.400368440
Directory	/workspace/4.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/4.flash_ctrl_rw_serr.2690506706
Short name	T898
Test name
Test status
Simulation time	9488045700 ps
CPU time	267.6 seconds
Started	Aug 13 06:16:21 PM PDT 24
Finished	Aug 13 06:20:49 PM PDT 24
Peak memory	295856 kb
Host	smart-81539a2b-7adb-4a0b-8d7d-005e700e7806
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690506706 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 4.flash_ctrl_rw_serr.2690506706
Directory	/workspace/4.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/4.flash_ctrl_sec_info_access.2784324352
Short name	T351
Test name
Test status
Simulation time	7107411500 ps
CPU time	75.53 seconds
Started	Aug 13 06:16:33 PM PDT 24
Finished	Aug 13 06:17:48 PM PDT 24
Peak memory	264236 kb
Host	smart-b65bec2d-8125-426a-8947-9c961b6344bd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2784324352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.2784324352
Directory	/workspace/4.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/4.flash_ctrl_serr_address.526380252
Short name	T577
Test name
Test status
Simulation time	7354396700 ps
CPU time	96.42 seconds
Started	Aug 13 06:16:19 PM PDT 24
Finished	Aug 13 06:17:55 PM PDT 24
Peak memory	265920 kb
Host	smart-915df7c1-bb74-4f11-aa62-bdd6e485909f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526380252 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_serr_address.526380252
Directory	/workspace/4.flash_ctrl_serr_address/latest

Test location	/workspace/coverage/default/4.flash_ctrl_serr_counter.1776205320
Short name	T519
Test name
Test status
Simulation time	2375195000 ps
CPU time	71.7 seconds
Started	Aug 13 06:16:21 PM PDT 24
Finished	Aug 13 06:17:33 PM PDT 24
Peak memory	274256 kb
Host	smart-29fe6139-072e-46b1-9568-f57044185884
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776205320 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 4.flash_ctrl_serr_counter.1776205320
Directory	/workspace/4.flash_ctrl_serr_counter/latest

Test location	/workspace/coverage/default/4.flash_ctrl_smoke.2932589031
Short name	T715
Test name
Test status
Simulation time	104797800 ps
CPU time	76.3 seconds
Started	Aug 13 06:16:08 PM PDT 24
Finished	Aug 13 06:17:24 PM PDT 24
Peak memory	276364 kb
Host	smart-2826043e-af4a-4bbc-b30f-952af2be3853
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2932589031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.2932589031
Directory	/workspace/4.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/4.flash_ctrl_smoke_hw.1680566157
Short name	T954
Test name
Test status
Simulation time	45778300 ps
CPU time	26.2 seconds
Started	Aug 13 06:16:09 PM PDT 24
Finished	Aug 13 06:16:36 PM PDT 24
Peak memory	260136 kb
Host	smart-c5f11810-de1e-4b10-8317-14a0dee92a6e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1680566157 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.1680566157
Directory	/workspace/4.flash_ctrl_smoke_hw/latest

Test location	/workspace/coverage/default/4.flash_ctrl_stress_all.3703155269
Short name	T57
Test name
Test status
Simulation time	290612100 ps
CPU time	466.95 seconds
Started	Aug 13 06:16:32 PM PDT 24
Finished	Aug 13 06:24:19 PM PDT 24
Peak memory	282124 kb
Host	smart-15f3c542-e3dc-4084-947c-07042531dfee
User	root
Command	/workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703155269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_s tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stres s_all.3703155269
Directory	/workspace/4.flash_ctrl_stress_all/latest

Test location	/workspace/coverage/default/4.flash_ctrl_sw_op.517343231
Short name	T608
Test name
Test status
Simulation time	78886100 ps
CPU time	24.74 seconds
Started	Aug 13 06:16:14 PM PDT 24
Finished	Aug 13 06:16:38 PM PDT 24
Peak memory	262568 kb
Host	smart-4f3da891-278d-4194-8188-165d750b4e94
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=517343231 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.517343231
Directory	/workspace/4.flash_ctrl_sw_op/latest

Test location	/workspace/coverage/default/4.flash_ctrl_wo.3553823505
Short name	T755
Test name
Test status
Simulation time	4151264300 ps
CPU time	177.64 seconds
Started	Aug 13 06:16:25 PM PDT 24
Finished	Aug 13 06:19:22 PM PDT 24
Peak memory	265828 kb
Host	smart-fb481a21-bdd9-4fe0-a8ee-e425391c176f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553823505 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 4.flash_ctrl_wo.3553823505
Directory	/workspace/4.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/40.flash_ctrl_alert_test.4016420106
Short name	T422
Test name
Test status
Simulation time	65606900 ps
CPU time	13.44 seconds
Started	Aug 13 06:22:06 PM PDT 24
Finished	Aug 13 06:22:19 PM PDT 24
Peak memory	265808 kb
Host	smart-f73b2af7-8a9d-4f61-b091-e171810421c5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016420106 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test. 4016420106
Directory	/workspace/40.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/40.flash_ctrl_connect.655162319
Short name	T963
Test name
Test status
Simulation time	25939500 ps
CPU time	13.58 seconds
Started	Aug 13 06:22:07 PM PDT 24
Finished	Aug 13 06:22:21 PM PDT 24
Peak memory	283376 kb
Host	smart-684f5135-8ceb-480a-8950-a03a00b6283d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=655162319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.655162319
Directory	/workspace/40.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/40.flash_ctrl_hw_sec_otp.855412079
Short name	T439
Test name
Test status
Simulation time	3935202600 ps
CPU time	99.34 seconds
Started	Aug 13 06:21:58 PM PDT 24
Finished	Aug 13 06:23:37 PM PDT 24
Peak memory	260988 kb
Host	smart-6e407325-22d8-472e-86a3-c72354e2b879
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855412079 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_h w_sec_otp.855412079
Directory	/workspace/40.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/40.flash_ctrl_otp_reset.50690344
Short name	T70
Test name
Test status
Simulation time	37191600 ps
CPU time	133.04 seconds
Started	Aug 13 06:22:06 PM PDT 24
Finished	Aug 13 06:24:19 PM PDT 24
Peak memory	260624 kb
Host	smart-0af43743-6c95-4c03-9a61-e2db6fdea33e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50690344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl _otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_otp _reset.50690344
Directory	/workspace/40.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/40.flash_ctrl_sec_info_access.2868772906
Short name	T619
Test name
Test status
Simulation time	351407300 ps
CPU time	50.48 seconds
Started	Aug 13 06:22:06 PM PDT 24
Finished	Aug 13 06:22:57 PM PDT 24
Peak memory	265336 kb
Host	smart-7be6de98-4113-426e-a416-d8838cd5d113
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2868772906 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.2868772906
Directory	/workspace/40.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/40.flash_ctrl_smoke.3508454171
Short name	T35
Test name
Test status
Simulation time	241150300 ps
CPU time	97.59 seconds
Started	Aug 13 06:21:59 PM PDT 24
Finished	Aug 13 06:23:37 PM PDT 24
Peak memory	276720 kb
Host	smart-c4774e91-b0fd-42ce-8292-c14d93374368
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3508454171 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.3508454171
Directory	/workspace/40.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/41.flash_ctrl_alert_test.1371835192
Short name	T806
Test name
Test status
Simulation time	62693800 ps
CPU time	13.76 seconds
Started	Aug 13 06:22:18 PM PDT 24
Finished	Aug 13 06:22:32 PM PDT 24
Peak memory	265612 kb
Host	smart-5e639e13-66a3-4d2e-9ac2-2e4ca727a700
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371835192 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test. 1371835192
Directory	/workspace/41.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/41.flash_ctrl_connect.594168435
Short name	T834
Test name
Test status
Simulation time	15208400 ps
CPU time	13.6 seconds
Started	Aug 13 06:22:16 PM PDT 24
Finished	Aug 13 06:22:30 PM PDT 24
Peak memory	283396 kb
Host	smart-241c469d-5878-426d-ac39-49904d0e2bdc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=594168435 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.594168435
Directory	/workspace/41.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/41.flash_ctrl_disable.3502244741
Short name	T1075
Test name
Test status
Simulation time	19611600 ps
CPU time	20.73 seconds
Started	Aug 13 06:22:07 PM PDT 24
Finished	Aug 13 06:22:27 PM PDT 24
Peak memory	274176 kb
Host	smart-b94a4733-a1df-4d2c-8973-691f3980e517
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502244741 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_disable.3502244741
Directory	/workspace/41.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/41.flash_ctrl_hw_sec_otp.3462641223
Short name	T601
Test name
Test status
Simulation time	6153534100 ps
CPU time	262.29 seconds
Started	Aug 13 06:22:06 PM PDT 24
Finished	Aug 13 06:26:29 PM PDT 24
Peak memory	263236 kb
Host	smart-6da6d51b-75f4-4255-879f-de1ca6bb2579
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462641223 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_ hw_sec_otp.3462641223
Directory	/workspace/41.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/41.flash_ctrl_otp_reset.197030105
Short name	T137
Test name
Test status
Simulation time	94026600 ps
CPU time	113.91 seconds
Started	Aug 13 06:22:06 PM PDT 24
Finished	Aug 13 06:24:00 PM PDT 24
Peak memory	260700 kb
Host	smart-efd6acd7-77f0-4ea8-b490-08b82ca56d92
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197030105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_ot p_reset.197030105
Directory	/workspace/41.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/41.flash_ctrl_sec_info_access.2652982553
Short name	T26
Test name
Test status
Simulation time	10435545500 ps
CPU time	75.78 seconds
Started	Aug 13 06:22:14 PM PDT 24
Finished	Aug 13 06:23:30 PM PDT 24
Peak memory	264196 kb
Host	smart-829d91b4-1139-445a-a756-b6bdc5f7b141
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2652982553 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.2652982553
Directory	/workspace/41.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/41.flash_ctrl_smoke.2844646583
Short name	T875
Test name
Test status
Simulation time	110309900 ps
CPU time	148.78 seconds
Started	Aug 13 06:22:06 PM PDT 24
Finished	Aug 13 06:24:35 PM PDT 24
Peak memory	277264 kb
Host	smart-f4ca9a18-4105-4ac0-96bf-2116d2310c3d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2844646583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.2844646583
Directory	/workspace/41.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/42.flash_ctrl_alert_test.1833410347
Short name	T491
Test name
Test status
Simulation time	141660000 ps
CPU time	13.65 seconds
Started	Aug 13 06:22:16 PM PDT 24
Finished	Aug 13 06:22:30 PM PDT 24
Peak memory	258816 kb
Host	smart-94ffa055-9cb8-4436-a342-975f04cab16b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833410347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test. 1833410347
Directory	/workspace/42.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/42.flash_ctrl_connect.1981267521
Short name	T578
Test name
Test status
Simulation time	32158800 ps
CPU time	15.96 seconds
Started	Aug 13 06:22:16 PM PDT 24
Finished	Aug 13 06:22:32 PM PDT 24
Peak memory	283604 kb
Host	smart-2abf7288-edf1-42c6-926a-7aa1e4a7c5a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1981267521 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.1981267521
Directory	/workspace/42.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/42.flash_ctrl_disable.2018220648
Short name	T343
Test name
Test status
Simulation time	24812200 ps
CPU time	20.66 seconds
Started	Aug 13 06:22:18 PM PDT 24
Finished	Aug 13 06:22:39 PM PDT 24
Peak memory	274004 kb
Host	smart-9512f72a-d8ae-4117-add6-95ba8448c9b7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018220648 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_disable.2018220648
Directory	/workspace/42.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/42.flash_ctrl_hw_sec_otp.650875001
Short name	T543
Test name
Test status
Simulation time	1985971300 ps
CPU time	70.71 seconds
Started	Aug 13 06:22:17 PM PDT 24
Finished	Aug 13 06:23:28 PM PDT 24
Peak memory	263276 kb
Host	smart-90504f35-0cb4-4df2-b16f-93a65e409e4a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650875001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_h w_sec_otp.650875001
Directory	/workspace/42.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/42.flash_ctrl_otp_reset.3907629494
Short name	T518
Test name
Test status
Simulation time	142257100 ps
CPU time	132.21 seconds
Started	Aug 13 06:22:16 PM PDT 24
Finished	Aug 13 06:24:29 PM PDT 24
Peak memory	264420 kb
Host	smart-3b2dad39-f443-4b44-bc8b-9ce340d2095d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907629494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_o tp_reset.3907629494
Directory	/workspace/42.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/42.flash_ctrl_sec_info_access.2775765730
Short name	T424
Test name
Test status
Simulation time	2540466500 ps
CPU time	64.99 seconds
Started	Aug 13 06:22:17 PM PDT 24
Finished	Aug 13 06:23:23 PM PDT 24
Peak memory	264264 kb
Host	smart-706a921b-5eed-4d58-a97c-643f405134a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2775765730 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.2775765730
Directory	/workspace/42.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/42.flash_ctrl_smoke.4282884292
Short name	T698
Test name
Test status
Simulation time	169051800 ps
CPU time	100.58 seconds
Started	Aug 13 06:22:16 PM PDT 24
Finished	Aug 13 06:23:57 PM PDT 24
Peak memory	277620 kb
Host	smart-851a23ed-7872-4b2e-8013-95a9957cff56
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4282884292 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.4282884292
Directory	/workspace/42.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/43.flash_ctrl_alert_test.3850854137
Short name	T767
Test name
Test status
Simulation time	200944400 ps
CPU time	13.95 seconds
Started	Aug 13 06:22:28 PM PDT 24
Finished	Aug 13 06:22:42 PM PDT 24
Peak memory	258796 kb
Host	smart-a19a1e16-cf0b-4491-955f-6181148b2fd0
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850854137 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test. 3850854137
Directory	/workspace/43.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/43.flash_ctrl_connect.267979083
Short name	T921
Test name
Test status
Simulation time	13565600 ps
CPU time	15.79 seconds
Started	Aug 13 06:22:28 PM PDT 24
Finished	Aug 13 06:22:44 PM PDT 24
Peak memory	283476 kb
Host	smart-c6acd04b-c37b-4f14-8e9f-2558e14730f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=267979083 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.267979083
Directory	/workspace/43.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/43.flash_ctrl_disable.2378520481
Short name	T1041
Test name
Test status
Simulation time	15546000 ps
CPU time	21.17 seconds
Started	Aug 13 06:22:28 PM PDT 24
Finished	Aug 13 06:22:49 PM PDT 24
Peak memory	274188 kb
Host	smart-c878e256-3f9c-4b58-9886-f101e591e2e4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378520481 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_disable.2378520481
Directory	/workspace/43.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/43.flash_ctrl_hw_sec_otp.2765774020
Short name	T588
Test name
Test status
Simulation time	6097011500 ps
CPU time	49.85 seconds
Started	Aug 13 06:22:29 PM PDT 24
Finished	Aug 13 06:23:19 PM PDT 24
Peak memory	261380 kb
Host	smart-b4cbc4ab-73a7-4d99-bbfb-465efb6dcf94
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765774020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_ hw_sec_otp.2765774020
Directory	/workspace/43.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/43.flash_ctrl_otp_reset.3908428025
Short name	T91
Test name
Test status
Simulation time	69733500 ps
CPU time	133.72 seconds
Started	Aug 13 06:22:29 PM PDT 24
Finished	Aug 13 06:24:43 PM PDT 24
Peak memory	260532 kb
Host	smart-bb2a906c-9d59-4c5e-8384-0a0e1cf598ea
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908428025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_o tp_reset.3908428025
Directory	/workspace/43.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/43.flash_ctrl_smoke.396803971
Short name	T560
Test name
Test status
Simulation time	33717400 ps
CPU time	123.32 seconds
Started	Aug 13 06:22:16 PM PDT 24
Finished	Aug 13 06:24:20 PM PDT 24
Peak memory	277024 kb
Host	smart-6d5ef23d-2f0f-4455-b6b6-e17ca70db532
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=396803971 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.396803971
Directory	/workspace/43.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/44.flash_ctrl_alert_test.3293292760
Short name	T460
Test name
Test status
Simulation time	65703000 ps
CPU time	13.94 seconds
Started	Aug 13 06:22:37 PM PDT 24
Finished	Aug 13 06:22:51 PM PDT 24
Peak memory	258900 kb
Host	smart-8e9b4c34-b8fb-42e7-9c40-df677cf2acf4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293292760 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test. 3293292760
Directory	/workspace/44.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/44.flash_ctrl_connect.182121016
Short name	T421
Test name
Test status
Simulation time	138605200 ps
CPU time	15.92 seconds
Started	Aug 13 06:22:38 PM PDT 24
Finished	Aug 13 06:22:54 PM PDT 24
Peak memory	284916 kb
Host	smart-92440e07-454e-4076-aff0-419781ec74c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=182121016 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.182121016
Directory	/workspace/44.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/44.flash_ctrl_disable.3944637755
Short name	T95
Test name
Test status
Simulation time	27413500 ps
CPU time	20.91 seconds
Started	Aug 13 06:22:41 PM PDT 24
Finished	Aug 13 06:23:02 PM PDT 24
Peak memory	274104 kb
Host	smart-e92a2c5f-68db-420a-8054-30c1c89046cd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944637755 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_disable.3944637755
Directory	/workspace/44.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/44.flash_ctrl_hw_sec_otp.2897792481
Short name	T448
Test name
Test status
Simulation time	2179794600 ps
CPU time	80.26 seconds
Started	Aug 13 06:22:26 PM PDT 24
Finished	Aug 13 06:23:47 PM PDT 24
Peak memory	261116 kb
Host	smart-399fc2a9-bcd9-4e28-9241-0d977b803392
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897792481 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_ hw_sec_otp.2897792481
Directory	/workspace/44.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/44.flash_ctrl_otp_reset.887570859
Short name	T679
Test name
Test status
Simulation time	73249000 ps
CPU time	111.62 seconds
Started	Aug 13 06:22:36 PM PDT 24
Finished	Aug 13 06:24:28 PM PDT 24
Peak memory	261572 kb
Host	smart-f332374f-6ebb-4f9a-8e44-b9a17822b9ed
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887570859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_ot p_reset.887570859
Directory	/workspace/44.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/44.flash_ctrl_sec_info_access.3744336628
Short name	T867
Test name
Test status
Simulation time	1205532700 ps
CPU time	62.49 seconds
Started	Aug 13 06:22:41 PM PDT 24
Finished	Aug 13 06:23:44 PM PDT 24
Peak memory	264756 kb
Host	smart-f0332a18-d3af-4ed1-a698-dd6d539b125f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3744336628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.3744336628
Directory	/workspace/44.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/44.flash_ctrl_smoke.2298203394
Short name	T1023
Test name
Test status
Simulation time	19960900 ps
CPU time	97.65 seconds
Started	Aug 13 06:22:27 PM PDT 24
Finished	Aug 13 06:24:05 PM PDT 24
Peak memory	278012 kb
Host	smart-d86a2fda-191f-42d7-8974-4f32e938423a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2298203394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.2298203394
Directory	/workspace/44.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/45.flash_ctrl_alert_test.1975789915
Short name	T922
Test name
Test status
Simulation time	88019400 ps
CPU time	13.46 seconds
Started	Aug 13 06:22:42 PM PDT 24
Finished	Aug 13 06:22:55 PM PDT 24
Peak memory	258848 kb
Host	smart-1781b5a6-98eb-4811-8b12-a257bf4b7725
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975789915 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test. 1975789915
Directory	/workspace/45.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/45.flash_ctrl_connect.3381150088
Short name	T766
Test name
Test status
Simulation time	49224000 ps
CPU time	15.77 seconds
Started	Aug 13 06:22:39 PM PDT 24
Finished	Aug 13 06:22:54 PM PDT 24
Peak memory	283428 kb
Host	smart-bd339eb4-6045-4abb-b101-9de27f47f9a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3381150088 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.3381150088
Directory	/workspace/45.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/45.flash_ctrl_disable.4196738166
Short name	T462
Test name
Test status
Simulation time	10854300 ps
CPU time	21.16 seconds
Started	Aug 13 06:22:40 PM PDT 24
Finished	Aug 13 06:23:02 PM PDT 24
Peak memory	267052 kb
Host	smart-5441fa2f-866f-4b38-8fb1-5c6d1ba71030
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196738166 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_disable.4196738166
Directory	/workspace/45.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/45.flash_ctrl_hw_sec_otp.4058907363
Short name	T1014
Test name
Test status
Simulation time	12224197600 ps
CPU time	111.46 seconds
Started	Aug 13 06:22:37 PM PDT 24
Finished	Aug 13 06:24:29 PM PDT 24
Peak memory	263316 kb
Host	smart-ba33611e-60c3-40db-a751-da100697947e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058907363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_ hw_sec_otp.4058907363
Directory	/workspace/45.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/45.flash_ctrl_otp_reset.4056744371
Short name	T1077
Test name
Test status
Simulation time	114932200 ps
CPU time	131.14 seconds
Started	Aug 13 06:22:39 PM PDT 24
Finished	Aug 13 06:24:51 PM PDT 24
Peak memory	260640 kb
Host	smart-7caaeff4-4918-41de-996e-21a800cb1070
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056744371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_o tp_reset.4056744371
Directory	/workspace/45.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/45.flash_ctrl_sec_info_access.2006008130
Short name	T349
Test name
Test status
Simulation time	1453177400 ps
CPU time	59.85 seconds
Started	Aug 13 06:22:37 PM PDT 24
Finished	Aug 13 06:23:37 PM PDT 24
Peak memory	264260 kb
Host	smart-b8a12b0b-3ad6-4722-ab41-ebb37ba0e3e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2006008130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.2006008130
Directory	/workspace/45.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/45.flash_ctrl_smoke.2438935693
Short name	T469
Test name
Test status
Simulation time	27910000 ps
CPU time	221.76 seconds
Started	Aug 13 06:22:40 PM PDT 24
Finished	Aug 13 06:26:22 PM PDT 24
Peak memory	279332 kb
Host	smart-ae984101-59a5-4648-be8d-e6d20b6c5b06
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2438935693 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.2438935693
Directory	/workspace/45.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/46.flash_ctrl_alert_test.3005155419
Short name	T524
Test name
Test status
Simulation time	170646400 ps
CPU time	13.76 seconds
Started	Aug 13 06:22:48 PM PDT 24
Finished	Aug 13 06:23:02 PM PDT 24
Peak memory	258792 kb
Host	smart-ead351c5-e2dd-4a67-9a68-3ba3ee66585b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005155419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test. 3005155419
Directory	/workspace/46.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/46.flash_ctrl_connect.2145366720
Short name	T493
Test name
Test status
Simulation time	43281900 ps
CPU time	16.28 seconds
Started	Aug 13 06:22:48 PM PDT 24
Finished	Aug 13 06:23:04 PM PDT 24
Peak memory	284712 kb
Host	smart-52d97337-e947-4edf-a626-4ba47312f4f5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2145366720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.2145366720
Directory	/workspace/46.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/46.flash_ctrl_disable.3019314963
Short name	T432
Test name
Test status
Simulation time	45562900 ps
CPU time	22.46 seconds
Started	Aug 13 06:22:50 PM PDT 24
Finished	Aug 13 06:23:13 PM PDT 24
Peak memory	274184 kb
Host	smart-ef19a8a9-ade9-4d67-9266-b53fdd51a7e7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019314963 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_disable.3019314963
Directory	/workspace/46.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/46.flash_ctrl_hw_sec_otp.879478933
Short name	T567
Test name
Test status
Simulation time	740258700 ps
CPU time	70.55 seconds
Started	Aug 13 06:22:39 PM PDT 24
Finished	Aug 13 06:23:50 PM PDT 24
Peak memory	263864 kb
Host	smart-c7fb2960-b72a-4a25-89c6-e3bf376a38aa
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879478933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_h w_sec_otp.879478933
Directory	/workspace/46.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/46.flash_ctrl_otp_reset.1027558979
Short name	T859
Test name
Test status
Simulation time	373894600 ps
CPU time	110.9 seconds
Started	Aug 13 06:22:47 PM PDT 24
Finished	Aug 13 06:24:38 PM PDT 24
Peak memory	265596 kb
Host	smart-5676e74a-eec4-4e1f-91a4-15ff7cc1e899
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027558979 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_o tp_reset.1027558979
Directory	/workspace/46.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/46.flash_ctrl_sec_info_access.1151789723
Short name	T816
Test name
Test status
Simulation time	16451385700 ps
CPU time	85.11 seconds
Started	Aug 13 06:22:48 PM PDT 24
Finished	Aug 13 06:24:13 PM PDT 24
Peak memory	264228 kb
Host	smart-6204fa25-c3a1-40b0-89d2-e23ea2a2ceed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1151789723 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.1151789723
Directory	/workspace/46.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/46.flash_ctrl_smoke.3800136355
Short name	T526
Test name
Test status
Simulation time	41602300 ps
CPU time	126.42 seconds
Started	Aug 13 06:22:39 PM PDT 24
Finished	Aug 13 06:24:46 PM PDT 24
Peak memory	276764 kb
Host	smart-21e0e662-871c-41e5-bcff-f1a377bb9334
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3800136355 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.3800136355
Directory	/workspace/46.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/47.flash_ctrl_alert_test.2709258448
Short name	T879
Test name
Test status
Simulation time	77436200 ps
CPU time	14.12 seconds
Started	Aug 13 06:22:47 PM PDT 24
Finished	Aug 13 06:23:02 PM PDT 24
Peak memory	258696 kb
Host	smart-26654701-eba0-48c2-85c3-3566be7e8897
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709258448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test. 2709258448
Directory	/workspace/47.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/47.flash_ctrl_disable.2166257688
Short name	T72
Test name
Test status
Simulation time	20406300 ps
CPU time	21.8 seconds
Started	Aug 13 06:22:49 PM PDT 24
Finished	Aug 13 06:23:11 PM PDT 24
Peak memory	274180 kb
Host	smart-c51bbdd3-0adc-4279-ba74-9b48fdfa1a80
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166257688 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_disable.2166257688
Directory	/workspace/47.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/47.flash_ctrl_hw_sec_otp.3720479193
Short name	T1044
Test name
Test status
Simulation time	669346800 ps
CPU time	64.19 seconds
Started	Aug 13 06:22:49 PM PDT 24
Finished	Aug 13 06:23:54 PM PDT 24
Peak memory	261504 kb
Host	smart-ff84e367-f29e-459d-8744-4690a7e631ae
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720479193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_ hw_sec_otp.3720479193
Directory	/workspace/47.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/47.flash_ctrl_otp_reset.2858800541
Short name	T468
Test name
Test status
Simulation time	144212500 ps
CPU time	131.93 seconds
Started	Aug 13 06:22:46 PM PDT 24
Finished	Aug 13 06:24:58 PM PDT 24
Peak memory	265512 kb
Host	smart-7937c8d1-0fe9-4e4b-b7b0-1606d9087d2e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858800541 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_o tp_reset.2858800541
Directory	/workspace/47.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/47.flash_ctrl_sec_info_access.3559185563
Short name	T385
Test name
Test status
Simulation time	2022439400 ps
CPU time	74.37 seconds
Started	Aug 13 06:22:51 PM PDT 24
Finished	Aug 13 06:24:05 PM PDT 24
Peak memory	263132 kb
Host	smart-6c8e4281-cbcf-416f-a389-4b79eab890b1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3559185563 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.3559185563
Directory	/workspace/47.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/47.flash_ctrl_smoke.628899148
Short name	T1006
Test name
Test status
Simulation time	40381800 ps
CPU time	124.94 seconds
Started	Aug 13 06:22:48 PM PDT 24
Finished	Aug 13 06:24:53 PM PDT 24
Peak memory	276820 kb
Host	smart-2746f91e-cb1d-4ffd-8f1d-3b4d734f7868
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=628899148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.628899148
Directory	/workspace/47.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/48.flash_ctrl_alert_test.354663641
Short name	T426
Test name
Test status
Simulation time	163750000 ps
CPU time	14.05 seconds
Started	Aug 13 06:22:56 PM PDT 24
Finished	Aug 13 06:23:10 PM PDT 24
Peak memory	258716 kb
Host	smart-c2121cc3-8566-44cf-9c52-4d005b37b074
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354663641 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.354663641
Directory	/workspace/48.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/48.flash_ctrl_connect.1606595435
Short name	T656
Test name
Test status
Simulation time	42383400 ps
CPU time	16.23 seconds
Started	Aug 13 06:22:57 PM PDT 24
Finished	Aug 13 06:23:14 PM PDT 24
Peak memory	283584 kb
Host	smart-d7571eea-fd30-4b3c-a7d9-fcfb6c5e6046
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1606595435 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.1606595435
Directory	/workspace/48.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/48.flash_ctrl_disable.2708758053
Short name	T729
Test name
Test status
Simulation time	91313600 ps
CPU time	21.24 seconds
Started	Aug 13 06:22:57 PM PDT 24
Finished	Aug 13 06:23:19 PM PDT 24
Peak memory	274116 kb
Host	smart-a23bb8b4-e4b8-438f-b2b8-a8cca868ac93
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708758053 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_disable.2708758053
Directory	/workspace/48.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/48.flash_ctrl_hw_sec_otp.379275048
Short name	T946
Test name
Test status
Simulation time	13306829200 ps
CPU time	124.07 seconds
Started	Aug 13 06:22:49 PM PDT 24
Finished	Aug 13 06:24:53 PM PDT 24
Peak memory	263328 kb
Host	smart-5fdfa31c-df7d-40e7-9120-6baee04fef9d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379275048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_h w_sec_otp.379275048
Directory	/workspace/48.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/48.flash_ctrl_otp_reset.3493939869
Short name	T997
Test name
Test status
Simulation time	283344200 ps
CPU time	133.88 seconds
Started	Aug 13 06:22:47 PM PDT 24
Finished	Aug 13 06:25:01 PM PDT 24
Peak memory	260712 kb
Host	smart-556e0b73-4dae-45eb-b775-a795b017e8ba
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493939869 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_o tp_reset.3493939869
Directory	/workspace/48.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/48.flash_ctrl_sec_info_access.1798972306
Short name	T352
Test name
Test status
Simulation time	2854477900 ps
CPU time	62.35 seconds
Started	Aug 13 06:23:00 PM PDT 24
Finished	Aug 13 06:24:02 PM PDT 24
Peak memory	263768 kb
Host	smart-df78b7dd-8ee4-4728-8009-dda280ca5dda
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1798972306 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.1798972306
Directory	/workspace/48.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/48.flash_ctrl_smoke.112508422
Short name	T988
Test name
Test status
Simulation time	88913800 ps
CPU time	74.41 seconds
Started	Aug 13 06:22:49 PM PDT 24
Finished	Aug 13 06:24:04 PM PDT 24
Peak memory	277604 kb
Host	smart-92166605-e6a4-408a-a1c9-95d300151929
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=112508422 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.112508422
Directory	/workspace/48.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/49.flash_ctrl_alert_test.2429468310
Short name	T893
Test name
Test status
Simulation time	143021500 ps
CPU time	13.88 seconds
Started	Aug 13 06:22:56 PM PDT 24
Finished	Aug 13 06:23:09 PM PDT 24
Peak memory	258812 kb
Host	smart-cd37d87a-75e9-4da0-af95-c21c521755ef
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429468310 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test. 2429468310
Directory	/workspace/49.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/49.flash_ctrl_connect.383939698
Short name	T430
Test name
Test status
Simulation time	16029000 ps
CPU time	15.95 seconds
Started	Aug 13 06:22:59 PM PDT 24
Finished	Aug 13 06:23:15 PM PDT 24
Peak memory	284812 kb
Host	smart-dc60f974-f0a6-403c-b94f-ec39d561d4fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=383939698 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.383939698
Directory	/workspace/49.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/49.flash_ctrl_disable.597371083
Short name	T346
Test name
Test status
Simulation time	20355400 ps
CPU time	22.05 seconds
Started	Aug 13 06:22:57 PM PDT 24
Finished	Aug 13 06:23:20 PM PDT 24
Peak memory	274032 kb
Host	smart-0cda3e30-6adb-4f92-9b6e-a54365b8ba63
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597371083 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_disable.597371083
Directory	/workspace/49.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/49.flash_ctrl_hw_sec_otp.2748253836
Short name	T477
Test name
Test status
Simulation time	5235325700 ps
CPU time	158.38 seconds
Started	Aug 13 06:23:00 PM PDT 24
Finished	Aug 13 06:25:38 PM PDT 24
Peak memory	263116 kb
Host	smart-c865260a-3bf0-4ab0-8779-057bd04b37b3
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748253836 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_ hw_sec_otp.2748253836
Directory	/workspace/49.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/49.flash_ctrl_otp_reset.2633933340
Short name	T853
Test name
Test status
Simulation time	45780000 ps
CPU time	134.57 seconds
Started	Aug 13 06:22:56 PM PDT 24
Finished	Aug 13 06:25:11 PM PDT 24
Peak memory	260536 kb
Host	smart-6c2bb7a4-c4a8-4a38-9411-38867d730844
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633933340 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_o tp_reset.2633933340
Directory	/workspace/49.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/49.flash_ctrl_sec_info_access.1124644700
Short name	T348
Test name
Test status
Simulation time	548628200 ps
CPU time	57.89 seconds
Started	Aug 13 06:23:00 PM PDT 24
Finished	Aug 13 06:23:58 PM PDT 24
Peak memory	264468 kb
Host	smart-596cfc7e-59c0-43cb-90db-f4006cd1bc68
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1124644700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.1124644700
Directory	/workspace/49.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/49.flash_ctrl_smoke.841212570
Short name	T725
Test name
Test status
Simulation time	31810700 ps
CPU time	147.99 seconds
Started	Aug 13 06:22:59 PM PDT 24
Finished	Aug 13 06:25:28 PM PDT 24
Peak memory	277540 kb
Host	smart-e80fb45a-65db-4822-b5b8-34c810c334d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=841212570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.841212570
Directory	/workspace/49.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/5.flash_ctrl_alert_test.4046264197
Short name	T748
Test name
Test status
Simulation time	39578400 ps
CPU time	13.81 seconds
Started	Aug 13 06:16:59 PM PDT 24
Finished	Aug 13 06:17:13 PM PDT 24
Peak memory	258788 kb
Host	smart-a2933249-09e4-4d82-9658-83aa4e260a22
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046264197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.4 046264197
Directory	/workspace/5.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/5.flash_ctrl_connect.25854237
Short name	T437
Test name
Test status
Simulation time	152943400 ps
CPU time	16.01 seconds
Started	Aug 13 06:16:56 PM PDT 24
Finished	Aug 13 06:17:13 PM PDT 24
Peak memory	284844 kb
Host	smart-d615f864-8bbe-41b3-92a3-37a69f66c3ca
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=25854237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.25854237
Directory	/workspace/5.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/5.flash_ctrl_disable.2276575889
Short name	T347
Test name
Test status
Simulation time	10620500 ps
CPU time	22.38 seconds
Started	Aug 13 06:16:57 PM PDT 24
Finished	Aug 13 06:17:19 PM PDT 24
Peak memory	274096 kb
Host	smart-e2bb94c4-6960-4a4e-b2b7-cf3c6fdd951a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276575889 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_disable.2276575889
Directory	/workspace/5.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/5.flash_ctrl_error_mp.313666593
Short name	T142
Test name
Test status
Simulation time	10655721100 ps
CPU time	2261.68 seconds
Started	Aug 13 06:16:48 PM PDT 24
Finished	Aug 13 06:54:30 PM PDT 24
Peak memory	265108 kb
Host	smart-8d3dd5b2-730a-45f7-9df1-830231ac0332
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=313666593 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_mp.313666593
Directory	/workspace/5.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/5.flash_ctrl_error_prog_win.3532280845
Short name	T1097
Test name
Test status
Simulation time	384074500 ps
CPU time	895.6 seconds
Started	Aug 13 06:16:39 PM PDT 24
Finished	Aug 13 06:31:35 PM PDT 24
Peak memory	271132 kb
Host	smart-889b029e-0800-41bb-98cd-c7884bcd082b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3532280845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.3532280845
Directory	/workspace/5.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/5.flash_ctrl_fetch_code.311097301
Short name	T49
Test name
Test status
Simulation time	831545200 ps
CPU time	22.92 seconds
Started	Aug 13 06:16:38 PM PDT 24
Finished	Aug 13 06:17:01 PM PDT 24
Peak memory	263136 kb
Host	smart-28c4424f-a1f9-43bc-8034-9b1d6473d499
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311097301 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetch_code.311097301
Directory	/workspace/5.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.2998340415
Short name	T825
Test name
Test status
Simulation time	10026878500 ps
CPU time	133.34 seconds
Started	Aug 13 06:16:57 PM PDT 24
Finished	Aug 13 06:19:11 PM PDT 24
Peak memory	283684 kb
Host	smart-dcea3d5c-3d38-4a5f-8e69-d93bbbdc0752
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998340415 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.2998340415
Directory	/workspace/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/5.flash_ctrl_hw_read_seed_err.3436707159
Short name	T328
Test name
Test status
Simulation time	46956600 ps
CPU time	13.43 seconds
Started	Aug 13 06:16:57 PM PDT 24
Finished	Aug 13 06:17:11 PM PDT 24
Peak memory	260696 kb
Host	smart-54f39da9-b2c6-478c-982f-45c36a9763d8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436707159 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_read_seed_err.3436707159
Directory	/workspace/5.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/5.flash_ctrl_hw_rma_reset.1141191869
Short name	T499
Test name
Test status
Simulation time	40117785600 ps
CPU time	811.84 seconds
Started	Aug 13 06:16:39 PM PDT 24
Finished	Aug 13 06:30:11 PM PDT 24
Peak memory	265036 kb
Host	smart-639b0c0d-3b36-4f04-9260-30ce651fcf5a
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141191869 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 5.flash_ctrl_hw_rma_reset.1141191869
Directory	/workspace/5.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/5.flash_ctrl_hw_sec_otp.848465748
Short name	T616
Test name
Test status
Simulation time	3208607300 ps
CPU time	114.67 seconds
Started	Aug 13 06:16:49 PM PDT 24
Finished	Aug 13 06:18:44 PM PDT 24
Peak memory	261060 kb
Host	smart-f6ec65fa-2a9d-414c-93c5-38d4067ba654
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848465748 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw _sec_otp.848465748
Directory	/workspace/5.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/5.flash_ctrl_intr_rd.181128711
Short name	T330
Test name
Test status
Simulation time	597325700 ps
CPU time	119.61 seconds
Started	Aug 13 06:16:49 PM PDT 24
Finished	Aug 13 06:18:49 PM PDT 24
Peak memory	294912 kb
Host	smart-81d7985a-688a-475e-b46d-1a2b5040ea27
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181128711 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash _ctrl_intr_rd.181128711
Directory	/workspace/5.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/5.flash_ctrl_intr_rd_slow_flash.2792919514
Short name	T506
Test name
Test status
Simulation time	24224862600 ps
CPU time	313.43 seconds
Started	Aug 13 06:16:50 PM PDT 24
Finished	Aug 13 06:22:03 PM PDT 24
Peak memory	292708 kb
Host	smart-c8d51aa2-23ce-4702-bd71-30ab3fa009ff
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792919514 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd_slow_flash.2792919514
Directory	/workspace/5.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/5.flash_ctrl_intr_wr.3011324293
Short name	T474
Test name
Test status
Simulation time	8954917600 ps
CPU time	69.57 seconds
Started	Aug 13 06:16:49 PM PDT 24
Finished	Aug 13 06:17:59 PM PDT 24
Peak memory	261064 kb
Host	smart-dd771406-b0e7-48f1-8bb3-cd39a2e709b7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011324293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 5.flash_ctrl_intr_wr.3011324293
Directory	/workspace/5.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/5.flash_ctrl_intr_wr_slow_flash.1904603449
Short name	T23
Test name
Test status
Simulation time	227577643800 ps
CPU time	209.75 seconds
Started	Aug 13 06:16:50 PM PDT 24
Finished	Aug 13 06:20:20 PM PDT 24
Peak memory	265744 kb
Host	smart-cbfe2591-ef38-4910-94a2-a999025092f1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190 4603449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.1904603449
Directory	/workspace/5.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/5.flash_ctrl_invalid_op.1046081909
Short name	T1070
Test name
Test status
Simulation time	1677649500 ps
CPU time	65.63 seconds
Started	Aug 13 06:16:49 PM PDT 24
Finished	Aug 13 06:17:55 PM PDT 24
Peak memory	264200 kb
Host	smart-afb84270-f671-4314-a6b7-2f2001fcc53d
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046081909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.1046081909
Directory	/workspace/5.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/5.flash_ctrl_lcmgr_intg.356057250
Short name	T572
Test name
Test status
Simulation time	61781100 ps
CPU time	13.39 seconds
Started	Aug 13 06:17:02 PM PDT 24
Finished	Aug 13 06:17:16 PM PDT 24
Peak memory	260736 kb
Host	smart-fc2a290d-995b-48a6-a6a8-20a2dc8403df
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356057250 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 5.flash_ctrl_lcmgr_intg.356057250
Directory	/workspace/5.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/5.flash_ctrl_mp_regions.3922206039
Short name	T144
Test name
Test status
Simulation time	10680529500 ps
CPU time	260.42 seconds
Started	Aug 13 06:16:41 PM PDT 24
Finished	Aug 13 06:21:01 PM PDT 24
Peak memory	274808 kb
Host	smart-848f8069-2276-42f0-8247-a520628c4cbc
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922206039 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_mp_regions.3922206039
Directory	/workspace/5.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/5.flash_ctrl_otp_reset.554251943
Short name	T894
Test name
Test status
Simulation time	237101500 ps
CPU time	132.4 seconds
Started	Aug 13 06:16:40 PM PDT 24
Finished	Aug 13 06:18:53 PM PDT 24
Peak memory	264980 kb
Host	smart-546a70a1-bd16-45f7-9540-4a6e17f0c5a4
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554251943 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_otp _reset.554251943
Directory	/workspace/5.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/5.flash_ctrl_phy_arb.2679943543
Short name	T538
Test name
Test status
Simulation time	237193600 ps
CPU time	352.02 seconds
Started	Aug 13 06:16:41 PM PDT 24
Finished	Aug 13 06:22:33 PM PDT 24
Peak memory	263628 kb
Host	smart-57fcbb3d-2036-4c88-b49e-a11757260b19
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2679943543 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.2679943543
Directory	/workspace/5.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/5.flash_ctrl_prog_reset.907474677
Short name	T164
Test name
Test status
Simulation time	21525300 ps
CPU time	13.65 seconds
Started	Aug 13 06:16:51 PM PDT 24
Finished	Aug 13 06:17:04 PM PDT 24
Peak memory	260116 kb
Host	smart-8000eb0c-c333-4b5e-a70b-d842ea364459
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907474677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test + UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 5.flash_ctrl_prog_reset.907474677
Directory	/workspace/5.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rand_ops.2062930966
Short name	T663
Test name
Test status
Simulation time	889554000 ps
CPU time	1031.34 seconds
Started	Aug 13 06:16:40 PM PDT 24
Finished	Aug 13 06:33:52 PM PDT 24
Peak memory	285956 kb
Host	smart-fb48991c-3eff-4c61-a7c6-1cf4315437da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2062930966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.2062930966
Directory	/workspace/5.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/5.flash_ctrl_re_evict.1323356571
Short name	T648
Test name
Test status
Simulation time	153487300 ps
CPU time	35.24 seconds
Started	Aug 13 06:16:58 PM PDT 24
Finished	Aug 13 06:17:33 PM PDT 24
Peak memory	276212 kb
Host	smart-fd769e8d-be2a-4431-b7f4-42762f94bdd2
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323356571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla sh_ctrl_re_evict.1323356571
Directory	/workspace/5.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/5.flash_ctrl_ro.2152722489
Short name	T367
Test name
Test status
Simulation time	1911015800 ps
CPU time	109.88 seconds
Started	Aug 13 06:16:49 PM PDT 24
Finished	Aug 13 06:18:39 PM PDT 24
Peak memory	289752 kb
Host	smart-c09ece50-6581-4c70-841e-67d31cf40ffd
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152722489 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 5.flash_ctrl_ro.2152722489
Directory	/workspace/5.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/5.flash_ctrl_ro_serr.2417144194
Short name	T936
Test name
Test status
Simulation time	667628100 ps
CPU time	132.52 seconds
Started	Aug 13 06:16:50 PM PDT 24
Finished	Aug 13 06:19:03 PM PDT 24
Peak memory	295920 kb
Host	smart-9ba67ad5-a756-4c7d-9427-fd6877e18b4f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417144194 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 5.flash_ctrl_ro_serr.2417144194
Directory	/workspace/5.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rw_derr.3592442817
Short name	T772
Test name
Test status
Simulation time	7443111400 ps
CPU time	261.75 seconds
Started	Aug 13 06:16:50 PM PDT 24
Finished	Aug 13 06:21:12 PM PDT 24
Peak memory	295540 kb
Host	smart-211e9561-10e8-4573-b048-553761797740
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592442817 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_derr.3592442817
Directory	/workspace/5.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rw_evict.2843071389
Short name	T986
Test name
Test status
Simulation time	94079300 ps
CPU time	29.23 seconds
Started	Aug 13 06:16:52 PM PDT 24
Finished	Aug 13 06:17:21 PM PDT 24
Peak memory	274204 kb
Host	smart-6d282a7d-454c-4b78-9a1b-febad55bb4bf
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843071389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.fla sh_ctrl_rw_evict.2843071389
Directory	/workspace/5.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rw_evict_all_en.3594190109
Short name	T481
Test name
Test status
Simulation time	56667200 ps
CPU time	28.54 seconds
Started	Aug 13 06:17:03 PM PDT 24
Finished	Aug 13 06:17:31 PM PDT 24
Peak memory	275572 kb
Host	smart-7bc00010-2f84-4937-9594-e2523ad4c971
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594190109 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict_all_en.3594190109
Directory	/workspace/5.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/5.flash_ctrl_rw_serr.2064599384
Short name	T1105
Test name
Test status
Simulation time	2304962300 ps
CPU time	295.08 seconds
Started	Aug 13 06:16:52 PM PDT 24
Finished	Aug 13 06:21:47 PM PDT 24
Peak memory	296052 kb
Host	smart-69789bd3-0977-4ed7-83d8-e1f6ba3a2282
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064599384 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 5.flash_ctrl_rw_serr.2064599384
Directory	/workspace/5.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/5.flash_ctrl_sec_info_access.2978099374
Short name	T920
Test name
Test status
Simulation time	7421165800 ps
CPU time	75.97 seconds
Started	Aug 13 06:16:56 PM PDT 24
Finished	Aug 13 06:18:12 PM PDT 24
Peak memory	264292 kb
Host	smart-b8647fce-540d-419f-b5d4-7c96bc7f0f14
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2978099374 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.2978099374
Directory	/workspace/5.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/5.flash_ctrl_smoke.1655481945
Short name	T927
Test name
Test status
Simulation time	52739900 ps
CPU time	122.74 seconds
Started	Aug 13 06:16:41 PM PDT 24
Finished	Aug 13 06:18:44 PM PDT 24
Peak memory	276420 kb
Host	smart-366a92cc-c244-4b88-b5c9-a2af5c55dabf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1655481945 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.1655481945
Directory	/workspace/5.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/5.flash_ctrl_wo.2518266645
Short name	T375
Test name
Test status
Simulation time	4243418300 ps
CPU time	183.05 seconds
Started	Aug 13 06:16:51 PM PDT 24
Finished	Aug 13 06:19:55 PM PDT 24
Peak memory	260660 kb
Host	smart-1a65170a-9e43-4373-bd04-9865142cc155
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518266645 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 5.flash_ctrl_wo.2518266645
Directory	/workspace/5.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/50.flash_ctrl_connect.2766721308
Short name	T617
Test name
Test status
Simulation time	48865700 ps
CPU time	13.88 seconds
Started	Aug 13 06:22:57 PM PDT 24
Finished	Aug 13 06:23:11 PM PDT 24
Peak memory	283572 kb
Host	smart-381159f2-7b27-49fb-8fdc-cf1dbb6c8d1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2766721308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.2766721308
Directory	/workspace/50.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/50.flash_ctrl_otp_reset.3202443687
Short name	T923
Test name
Test status
Simulation time	70982000 ps
CPU time	111.28 seconds
Started	Aug 13 06:22:54 PM PDT 24
Finished	Aug 13 06:24:46 PM PDT 24
Peak memory	261588 kb
Host	smart-28e76cb7-8c3c-487c-9682-4bdcadfb27ec
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202443687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_o tp_reset.3202443687
Directory	/workspace/50.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/51.flash_ctrl_connect.866400196
Short name	T809
Test name
Test status
Simulation time	25444200 ps
CPU time	16.18 seconds
Started	Aug 13 06:23:07 PM PDT 24
Finished	Aug 13 06:23:23 PM PDT 24
Peak memory	284756 kb
Host	smart-66602663-5065-4a71-b330-13d81a86f6d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=866400196 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.866400196
Directory	/workspace/51.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/51.flash_ctrl_otp_reset.1310173584
Short name	T183
Test name
Test status
Simulation time	78248700 ps
CPU time	132.88 seconds
Started	Aug 13 06:23:00 PM PDT 24
Finished	Aug 13 06:25:13 PM PDT 24
Peak memory	260564 kb
Host	smart-54d83d79-50ed-456e-bfd6-2137b2b8446a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310173584 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_o tp_reset.1310173584
Directory	/workspace/51.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/52.flash_ctrl_connect.1990606753
Short name	T438
Test name
Test status
Simulation time	39551900 ps
CPU time	16.16 seconds
Started	Aug 13 06:23:04 PM PDT 24
Finished	Aug 13 06:23:21 PM PDT 24
Peak memory	284732 kb
Host	smart-b90a1d70-6141-48eb-a155-eb080321d1a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1990606753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.1990606753
Directory	/workspace/52.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/52.flash_ctrl_otp_reset.562097276
Short name	T1074
Test name
Test status
Simulation time	45103100 ps
CPU time	136.29 seconds
Started	Aug 13 06:23:06 PM PDT 24
Finished	Aug 13 06:25:23 PM PDT 24
Peak memory	260948 kb
Host	smart-ceef4d92-bf9b-47ce-9e5b-222602d105d9
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562097276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_ot p_reset.562097276
Directory	/workspace/52.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/53.flash_ctrl_connect.446794413
Short name	T463
Test name
Test status
Simulation time	53143000 ps
CPU time	13.58 seconds
Started	Aug 13 06:23:05 PM PDT 24
Finished	Aug 13 06:23:19 PM PDT 24
Peak memory	283492 kb
Host	smart-805bd0fc-a8cc-419c-a3f1-84984b6390e2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=446794413 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.446794413
Directory	/workspace/53.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/53.flash_ctrl_otp_reset.3695920463
Short name	T419
Test name
Test status
Simulation time	68791800 ps
CPU time	132.33 seconds
Started	Aug 13 06:23:03 PM PDT 24
Finished	Aug 13 06:25:16 PM PDT 24
Peak memory	261596 kb
Host	smart-64a84574-3be4-47ae-aaba-05f1a15484f4
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695920463 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_o tp_reset.3695920463
Directory	/workspace/53.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/54.flash_ctrl_connect.3859976706
Short name	T542
Test name
Test status
Simulation time	51005500 ps
CPU time	15.97 seconds
Started	Aug 13 06:23:05 PM PDT 24
Finished	Aug 13 06:23:21 PM PDT 24
Peak memory	283536 kb
Host	smart-a1a892c8-6159-461d-a1d1-81c8b8c32876
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3859976706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.3859976706
Directory	/workspace/54.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/54.flash_ctrl_otp_reset.3489235551
Short name	T883
Test name
Test status
Simulation time	86761500 ps
CPU time	111.45 seconds
Started	Aug 13 06:23:07 PM PDT 24
Finished	Aug 13 06:24:59 PM PDT 24
Peak memory	260796 kb
Host	smart-95f8f99f-f193-4041-81e7-15d6be46ae45
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489235551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_o tp_reset.3489235551
Directory	/workspace/54.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/55.flash_ctrl_connect.2132777379
Short name	T955
Test name
Test status
Simulation time	55670100 ps
CPU time	13.21 seconds
Started	Aug 13 06:23:06 PM PDT 24
Finished	Aug 13 06:23:19 PM PDT 24
Peak memory	283476 kb
Host	smart-35d4fed6-f339-4c5e-8cf6-cb8a3565ad90
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2132777379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.2132777379
Directory	/workspace/55.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/55.flash_ctrl_otp_reset.1601723933
Short name	T459
Test name
Test status
Simulation time	321317800 ps
CPU time	131.7 seconds
Started	Aug 13 06:23:05 PM PDT 24
Finished	Aug 13 06:25:17 PM PDT 24
Peak memory	260600 kb
Host	smart-8539e940-d365-4899-902a-1d0e84ee8b11
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601723933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_o tp_reset.1601723933
Directory	/workspace/55.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/56.flash_ctrl_connect.3099731292
Short name	T13
Test name
Test status
Simulation time	29100800 ps
CPU time	13.4 seconds
Started	Aug 13 06:23:07 PM PDT 24
Finished	Aug 13 06:23:20 PM PDT 24
Peak memory	284744 kb
Host	smart-39907059-9b71-4e01-8d14-97ce8af414ab
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3099731292 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.3099731292
Directory	/workspace/56.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/56.flash_ctrl_otp_reset.3311021270
Short name	T185
Test name
Test status
Simulation time	134156100 ps
CPU time	133.72 seconds
Started	Aug 13 06:23:05 PM PDT 24
Finished	Aug 13 06:25:19 PM PDT 24
Peak memory	260576 kb
Host	smart-df6ed4e5-c4d9-461d-832a-971a7ffb61fe
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311021270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_o tp_reset.3311021270
Directory	/workspace/56.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/57.flash_ctrl_connect.3888396209
Short name	T926
Test name
Test status
Simulation time	23037700 ps
CPU time	16.09 seconds
Started	Aug 13 06:23:18 PM PDT 24
Finished	Aug 13 06:23:35 PM PDT 24
Peak memory	283488 kb
Host	smart-5bafb1e5-60ed-4da2-b410-8325e61a3b44
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3888396209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.3888396209
Directory	/workspace/57.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/57.flash_ctrl_otp_reset.1242561805
Short name	T670
Test name
Test status
Simulation time	41134500 ps
CPU time	131.36 seconds
Started	Aug 13 06:23:06 PM PDT 24
Finished	Aug 13 06:25:17 PM PDT 24
Peak memory	265048 kb
Host	smart-dfa04437-94f3-4f63-8527-fb085470db30
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242561805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_o tp_reset.1242561805
Directory	/workspace/57.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/58.flash_ctrl_connect.1779834530
Short name	T571
Test name
Test status
Simulation time	32351500 ps
CPU time	13.43 seconds
Started	Aug 13 06:23:22 PM PDT 24
Finished	Aug 13 06:23:35 PM PDT 24
Peak memory	284836 kb
Host	smart-b094f3a2-5927-4602-985c-93b42090e5c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1779834530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.1779834530
Directory	/workspace/58.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/58.flash_ctrl_otp_reset.108264479
Short name	T925
Test name
Test status
Simulation time	41566500 ps
CPU time	131.71 seconds
Started	Aug 13 06:23:17 PM PDT 24
Finished	Aug 13 06:25:29 PM PDT 24
Peak memory	265708 kb
Host	smart-b39abb2e-ecd4-47d6-80d4-e1ca438cb6ca
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108264479 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_ot p_reset.108264479
Directory	/workspace/58.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/59.flash_ctrl_connect.2896670716
Short name	T756
Test name
Test status
Simulation time	14772400 ps
CPU time	15.89 seconds
Started	Aug 13 06:23:18 PM PDT 24
Finished	Aug 13 06:23:34 PM PDT 24
Peak memory	283572 kb
Host	smart-db14fdce-42f0-4a86-8c16-50adde8b3b07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2896670716 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.2896670716
Directory	/workspace/59.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/59.flash_ctrl_otp_reset.1813864059
Short name	T172
Test name
Test status
Simulation time	137375500 ps
CPU time	135.04 seconds
Started	Aug 13 06:23:15 PM PDT 24
Finished	Aug 13 06:25:30 PM PDT 24
Peak memory	261476 kb
Host	smart-9f76a3e7-199d-4409-9123-b12cbb393c2b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813864059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_o tp_reset.1813864059
Directory	/workspace/59.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/6.flash_ctrl_alert_test.1741749183
Short name	T688
Test name
Test status
Simulation time	57419100 ps
CPU time	13.41 seconds
Started	Aug 13 06:17:22 PM PDT 24
Finished	Aug 13 06:17:35 PM PDT 24
Peak memory	265804 kb
Host	smart-56f552e3-51bf-4d79-9c31-829aeb54ccd4
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741749183 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.1 741749183
Directory	/workspace/6.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/6.flash_ctrl_connect.570430363
Short name	T1030
Test name
Test status
Simulation time	15287400 ps
CPU time	15.62 seconds
Started	Aug 13 06:17:14 PM PDT 24
Finished	Aug 13 06:17:30 PM PDT 24
Peak memory	283544 kb
Host	smart-6e43f921-7959-48b5-8407-372384116c45
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=570430363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.570430363
Directory	/workspace/6.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/6.flash_ctrl_disable.1489333131
Short name	T671
Test name
Test status
Simulation time	10564500 ps
CPU time	20.56 seconds
Started	Aug 13 06:17:13 PM PDT 24
Finished	Aug 13 06:17:34 PM PDT 24
Peak memory	274172 kb
Host	smart-eb6e1686-bdcd-421c-a562-39cb143fc4b0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489333131 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_disable.1489333131
Directory	/workspace/6.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/6.flash_ctrl_error_mp.3214661181
Short name	T65
Test name
Test status
Simulation time	54397274000 ps
CPU time	2467.55 seconds
Started	Aug 13 06:17:07 PM PDT 24
Finished	Aug 13 06:58:15 PM PDT 24
Peak memory	265708 kb
Host	smart-4713046e-3eb5-470a-9277-e02e80246b4e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3214661181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_mp.3214661181
Directory	/workspace/6.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/6.flash_ctrl_error_prog_win.1731471049
Short name	T126
Test name
Test status
Simulation time	2675972300 ps
CPU time	757.32 seconds
Started	Aug 13 06:16:57 PM PDT 24
Finished	Aug 13 06:29:35 PM PDT 24
Peak memory	273984 kb
Host	smart-14a7737a-1534-4e0e-a6bd-40b6a4ea9af3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1731471049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.1731471049
Directory	/workspace/6.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/6.flash_ctrl_hw_read_seed_err.77022073
Short name	T283
Test name
Test status
Simulation time	31461600 ps
CPU time	13.58 seconds
Started	Aug 13 06:17:23 PM PDT 24
Finished	Aug 13 06:17:36 PM PDT 24
Peak memory	258988 kb
Host	smart-3cb9875c-bec2-4b55-b3fc-ea694f635ad4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77022073 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_read_seed_err.77022073
Directory	/workspace/6.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/6.flash_ctrl_hw_rma_reset.821300510
Short name	T173
Test name
Test status
Simulation time	80148007900 ps
CPU time	833.03 seconds
Started	Aug 13 06:16:58 PM PDT 24
Finished	Aug 13 06:30:51 PM PDT 24
Peak memory	262624 kb
Host	smart-4cb3326b-0c68-4144-86b4-9f8f6672c65b
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821300510 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 6.flash_ctrl_hw_rma_reset.821300510
Directory	/workspace/6.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/6.flash_ctrl_hw_sec_otp.2241908940
Short name	T811
Test name
Test status
Simulation time	14930784400 ps
CPU time	120.54 seconds
Started	Aug 13 06:16:57 PM PDT 24
Finished	Aug 13 06:18:57 PM PDT 24
Peak memory	263436 kb
Host	smart-aafb0e6d-2c76-44b5-967c-8dcc25bf5a6c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241908940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_h w_sec_otp.2241908940
Directory	/workspace/6.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/6.flash_ctrl_intr_rd.1879139120
Short name	T325
Test name
Test status
Simulation time	7245678300 ps
CPU time	200.6 seconds
Started	Aug 13 06:17:07 PM PDT 24
Finished	Aug 13 06:20:28 PM PDT 24
Peak memory	292160 kb
Host	smart-080e4e97-6b00-4410-be47-12e4f0c46273
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879139120 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas h_ctrl_intr_rd.1879139120
Directory	/workspace/6.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/6.flash_ctrl_intr_rd_slow_flash.1740917067
Short name	T782
Test name
Test status
Simulation time	47194257900 ps
CPU time	305.74 seconds
Started	Aug 13 06:17:07 PM PDT 24
Finished	Aug 13 06:22:13 PM PDT 24
Peak memory	292124 kb
Host	smart-050b57b8-c8be-4c5e-95e9-662542247f4e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740917067 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd_slow_flash.1740917067
Directory	/workspace/6.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/6.flash_ctrl_intr_wr.1494488568
Short name	T1045
Test name
Test status
Simulation time	2335522700 ps
CPU time	67.73 seconds
Started	Aug 13 06:17:06 PM PDT 24
Finished	Aug 13 06:18:14 PM PDT 24
Peak memory	260572 kb
Host	smart-c495647e-39d8-4d96-8da5-c2508787575b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494488568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 6.flash_ctrl_intr_wr.1494488568
Directory	/workspace/6.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.3985322425
Short name	T17
Test name
Test status
Simulation time	23699173700 ps
CPU time	196.67 seconds
Started	Aug 13 06:17:15 PM PDT 24
Finished	Aug 13 06:20:32 PM PDT 24
Peak memory	261172 kb
Host	smart-36521a1d-b96e-4e02-a847-703f52cd71d8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398 5322425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.3985322425
Directory	/workspace/6.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/6.flash_ctrl_invalid_op.181257713
Short name	T897
Test name
Test status
Simulation time	1014401800 ps
CPU time	90.57 seconds
Started	Aug 13 06:17:05 PM PDT 24
Finished	Aug 13 06:18:36 PM PDT 24
Peak memory	264188 kb
Host	smart-ab570a6b-4749-4e5f-b625-05c663148520
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181257713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.181257713
Directory	/workspace/6.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/6.flash_ctrl_lcmgr_intg.2987458899
Short name	T1052
Test name
Test status
Simulation time	14981300 ps
CPU time	13.68 seconds
Started	Aug 13 06:17:22 PM PDT 24
Finished	Aug 13 06:17:36 PM PDT 24
Peak memory	260644 kb
Host	smart-c9fef28f-6c57-4b0d-9d32-70a75569fc32
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987458899 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 6.flash_ctrl_lcmgr_intg.2987458899
Directory	/workspace/6.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/6.flash_ctrl_mp_regions.2207582506
Short name	T642
Test name
Test status
Simulation time	3445029800 ps
CPU time	131.38 seconds
Started	Aug 13 06:17:03 PM PDT 24
Finished	Aug 13 06:19:15 PM PDT 24
Peak memory	265760 kb
Host	smart-c3babae3-f265-4055-a664-15cfb88c8d47
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207582506 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_mp_regions.2207582506
Directory	/workspace/6.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/6.flash_ctrl_otp_reset.1701974958
Short name	T684
Test name
Test status
Simulation time	156404400 ps
CPU time	109.42 seconds
Started	Aug 13 06:16:57 PM PDT 24
Finished	Aug 13 06:18:47 PM PDT 24
Peak memory	264908 kb
Host	smart-4339f686-4ee4-4061-8d7e-d0aa9c4407e5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701974958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ot p_reset.1701974958
Directory	/workspace/6.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/6.flash_ctrl_phy_arb.79509269
Short name	T128
Test name
Test status
Simulation time	26426200 ps
CPU time	68.38 seconds
Started	Aug 13 06:16:56 PM PDT 24
Finished	Aug 13 06:18:05 PM PDT 24
Peak memory	263572 kb
Host	smart-d2e6a7ac-c7d5-4c6f-80e5-29d6f5b31f9b
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=79509269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.79509269
Directory	/workspace/6.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/6.flash_ctrl_prog_reset.2084380319
Short name	T961
Test name
Test status
Simulation time	43445000 ps
CPU time	14.13 seconds
Started	Aug 13 06:17:09 PM PDT 24
Finished	Aug 13 06:17:24 PM PDT 24
Peak memory	260020 kb
Host	smart-5b5a1c08-ea5e-4614-8cf8-48ced61c4c64
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084380319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 6.flash_ctrl_prog_reset.2084380319
Directory	/workspace/6.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rand_ops.2985863628
Short name	T993
Test name
Test status
Simulation time	3086104000 ps
CPU time	1201.63 seconds
Started	Aug 13 06:16:57 PM PDT 24
Finished	Aug 13 06:36:59 PM PDT 24
Peak memory	289796 kb
Host	smart-22a5a19b-5438-483c-8f59-ffa7b51cb4d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2985863628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.2985863628
Directory	/workspace/6.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/6.flash_ctrl_re_evict.586178051
Short name	T1082
Test name
Test status
Simulation time	187724000 ps
CPU time	34.41 seconds
Started	Aug 13 06:17:16 PM PDT 24
Finished	Aug 13 06:17:51 PM PDT 24
Peak memory	276248 kb
Host	smart-536c69ee-4940-46ff-a544-21a8dce40639
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586178051 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SE Q=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas h_ctrl_re_evict.586178051
Directory	/workspace/6.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/6.flash_ctrl_ro.537583783
Short name	T1038
Test name
Test status
Simulation time	534516200 ps
CPU time	106.46 seconds
Started	Aug 13 06:17:11 PM PDT 24
Finished	Aug 13 06:18:57 PM PDT 24
Peak memory	291880 kb
Host	smart-eb996b81-5537-427c-9554-fb6e73a84d33
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537583783 -assert nopostproc +UVM_TESTNAME=flas h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 6.flash_ctrl_ro.537583783
Directory	/workspace/6.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/6.flash_ctrl_ro_serr.3892361137
Short name	T605
Test name
Test status
Simulation time	605613500 ps
CPU time	127.59 seconds
Started	Aug 13 06:17:05 PM PDT 24
Finished	Aug 13 06:19:13 PM PDT 24
Peak memory	282364 kb
Host	smart-86b242b9-6b17-43ba-ad73-e5c990e60c82
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892361137 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 6.flash_ctrl_ro_serr.3892361137
Directory	/workspace/6.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rw.962129612
Short name	T15
Test name
Test status
Simulation time	28325447500 ps
CPU time	716.32 seconds
Started	Aug 13 06:17:04 PM PDT 24
Finished	Aug 13 06:29:01 PM PDT 24
Peak memory	315136 kb
Host	smart-8d698ecc-cd01-4c96-98e6-09d64a045d97
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962129612 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw.962129612
Directory	/workspace/6.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rw_evict_all_en.3605301514
Short name	T628
Test name
Test status
Simulation time	31177100 ps
CPU time	31.53 seconds
Started	Aug 13 06:17:14 PM PDT 24
Finished	Aug 13 06:17:45 PM PDT 24
Peak memory	275516 kb
Host	smart-70f768a2-e7fc-4e29-83b6-e382b3dbfe0b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605301514 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict_all_en.3605301514
Directory	/workspace/6.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/6.flash_ctrl_rw_serr.1976489102
Short name	T365
Test name
Test status
Simulation time	20770963500 ps
CPU time	225.92 seconds
Started	Aug 13 06:17:06 PM PDT 24
Finished	Aug 13 06:20:52 PM PDT 24
Peak memory	296072 kb
Host	smart-5f292bd8-25d2-4b11-bf38-26209f2e0e1b
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976489102 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 6.flash_ctrl_rw_serr.1976489102
Directory	/workspace/6.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/6.flash_ctrl_sec_info_access.3713705871
Short name	T509
Test name
Test status
Simulation time	3109529900 ps
CPU time	82.31 seconds
Started	Aug 13 06:17:11 PM PDT 24
Finished	Aug 13 06:18:34 PM PDT 24
Peak memory	263636 kb
Host	smart-10877195-a248-4b81-88f5-6ac6f486cd33
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3713705871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.3713705871
Directory	/workspace/6.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/6.flash_ctrl_smoke.3515534147
Short name	T838
Test name
Test status
Simulation time	45389000 ps
CPU time	229.76 seconds
Started	Aug 13 06:16:57 PM PDT 24
Finished	Aug 13 06:20:47 PM PDT 24
Peak memory	279548 kb
Host	smart-360122ae-9b31-4b65-9a5e-45bba92bbdb4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3515534147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.3515534147
Directory	/workspace/6.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/6.flash_ctrl_wo.50160217
Short name	T364
Test name
Test status
Simulation time	7144860900 ps
CPU time	152.65 seconds
Started	Aug 13 06:17:05 PM PDT 24
Finished	Aug 13 06:19:38 PM PDT 24
Peak memory	260536 kb
Host	smart-0dabbf9f-911e-4d1c-9742-a8a0205b5445
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50160217 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 6.flash_ctrl_wo.50160217
Directory	/workspace/6.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/60.flash_ctrl_connect.77918004
Short name	T558
Test name
Test status
Simulation time	15079000 ps
CPU time	15.89 seconds
Started	Aug 13 06:23:18 PM PDT 24
Finished	Aug 13 06:23:34 PM PDT 24
Peak memory	283272 kb
Host	smart-33b3f47a-a850-4424-85c4-29a9447160e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=77918004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.77918004
Directory	/workspace/60.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/60.flash_ctrl_otp_reset.1813326722
Short name	T1049
Test name
Test status
Simulation time	72045400 ps
CPU time	133.97 seconds
Started	Aug 13 06:23:17 PM PDT 24
Finished	Aug 13 06:25:31 PM PDT 24
Peak memory	264472 kb
Host	smart-66b920ae-57e5-4c85-8570-aad33a989941
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813326722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_o tp_reset.1813326722
Directory	/workspace/60.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/61.flash_ctrl_connect.1901135255
Short name	T602
Test name
Test status
Simulation time	45198400 ps
CPU time	15.81 seconds
Started	Aug 13 06:23:18 PM PDT 24
Finished	Aug 13 06:23:34 PM PDT 24
Peak memory	283564 kb
Host	smart-ce79e4bf-bec8-4304-ba97-3bfa35201b27
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1901135255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.1901135255
Directory	/workspace/61.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/61.flash_ctrl_otp_reset.4188041374
Short name	T626
Test name
Test status
Simulation time	69068700 ps
CPU time	131.07 seconds
Started	Aug 13 06:23:16 PM PDT 24
Finished	Aug 13 06:25:28 PM PDT 24
Peak memory	261608 kb
Host	smart-ba37207f-d7a1-4374-b8ae-8c5cf796da44
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188041374 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_o tp_reset.4188041374
Directory	/workspace/61.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/62.flash_ctrl_connect.2965379045
Short name	T109
Test name
Test status
Simulation time	29238200 ps
CPU time	16.36 seconds
Started	Aug 13 06:23:17 PM PDT 24
Finished	Aug 13 06:23:33 PM PDT 24
Peak memory	283532 kb
Host	smart-c76dc3fa-f9c4-476b-bdba-bb50f8f2ae20
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2965379045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.2965379045
Directory	/workspace/62.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/62.flash_ctrl_otp_reset.2201479025
Short name	T1110
Test name
Test status
Simulation time	40498900 ps
CPU time	134.8 seconds
Started	Aug 13 06:23:17 PM PDT 24
Finished	Aug 13 06:25:32 PM PDT 24
Peak memory	260504 kb
Host	smart-9549da7f-ede0-4c38-a530-6fe001b4fd33
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201479025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_o tp_reset.2201479025
Directory	/workspace/62.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/63.flash_ctrl_connect.1788030397
Short name	T785
Test name
Test status
Simulation time	16530500 ps
CPU time	15.97 seconds
Started	Aug 13 06:23:18 PM PDT 24
Finished	Aug 13 06:23:35 PM PDT 24
Peak memory	284820 kb
Host	smart-44cb1d03-1bfa-4efb-916d-b79c52e7ce9d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1788030397 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.1788030397
Directory	/workspace/63.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/63.flash_ctrl_otp_reset.66373284
Short name	T1098
Test name
Test status
Simulation time	149314600 ps
CPU time	132.64 seconds
Started	Aug 13 06:23:18 PM PDT 24
Finished	Aug 13 06:25:31 PM PDT 24
Peak memory	261584 kb
Host	smart-8e09fbb9-fd66-4ca2-8da1-2ac6b63beab3
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66373284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl _otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_otp _reset.66373284
Directory	/workspace/63.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/64.flash_ctrl_connect.2951822490
Short name	T803
Test name
Test status
Simulation time	15541700 ps
CPU time	15.77 seconds
Started	Aug 13 06:23:21 PM PDT 24
Finished	Aug 13 06:23:37 PM PDT 24
Peak memory	284872 kb
Host	smart-aa1455ec-4c57-45df-80f5-c1245f6c419b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2951822490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.2951822490
Directory	/workspace/64.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/64.flash_ctrl_otp_reset.1501908679
Short name	T69
Test name
Test status
Simulation time	93554300 ps
CPU time	131.49 seconds
Started	Aug 13 06:23:21 PM PDT 24
Finished	Aug 13 06:25:33 PM PDT 24
Peak memory	265060 kb
Host	smart-db38d820-7c79-42f3-a967-a9d852cd5f9f
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501908679 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_o tp_reset.1501908679
Directory	/workspace/64.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/65.flash_ctrl_connect.380426621
Short name	T453
Test name
Test status
Simulation time	13130300 ps
CPU time	16.04 seconds
Started	Aug 13 06:23:17 PM PDT 24
Finished	Aug 13 06:23:33 PM PDT 24
Peak memory	283588 kb
Host	smart-9f9c097c-cc84-4d49-adfd-44183091c011
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=380426621 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.380426621
Directory	/workspace/65.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/65.flash_ctrl_otp_reset.925605276
Short name	T181
Test name
Test status
Simulation time	88798600 ps
CPU time	132 seconds
Started	Aug 13 06:23:17 PM PDT 24
Finished	Aug 13 06:25:29 PM PDT 24
Peak memory	264952 kb
Host	smart-a5b272ae-c918-4052-b5d5-72c38677323a
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925605276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_ot p_reset.925605276
Directory	/workspace/65.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/66.flash_ctrl_connect.3035892214
Short name	T423
Test name
Test status
Simulation time	50301700 ps
CPU time	13.58 seconds
Started	Aug 13 06:23:17 PM PDT 24
Finished	Aug 13 06:23:30 PM PDT 24
Peak memory	283480 kb
Host	smart-be8896b0-6cab-4c41-8096-294a45ed9934
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3035892214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.3035892214
Directory	/workspace/66.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/66.flash_ctrl_otp_reset.2057097249
Short name	T994
Test name
Test status
Simulation time	136448400 ps
CPU time	112.76 seconds
Started	Aug 13 06:23:18 PM PDT 24
Finished	Aug 13 06:25:11 PM PDT 24
Peak memory	260588 kb
Host	smart-97782d05-dbb8-4ec3-90ac-72c8ef2f7e01
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057097249 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_o tp_reset.2057097249
Directory	/workspace/66.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/67.flash_ctrl_connect.3393824784
Short name	T255
Test name
Test status
Simulation time	14470100 ps
CPU time	13.73 seconds
Started	Aug 13 06:23:27 PM PDT 24
Finished	Aug 13 06:23:41 PM PDT 24
Peak memory	283616 kb
Host	smart-a3213406-0d7a-40f4-b9e8-ec2bfb24c1cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3393824784 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.3393824784
Directory	/workspace/67.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/67.flash_ctrl_otp_reset.1147483363
Short name	T1080
Test name
Test status
Simulation time	129826200 ps
CPU time	134.79 seconds
Started	Aug 13 06:23:28 PM PDT 24
Finished	Aug 13 06:25:43 PM PDT 24
Peak memory	260632 kb
Host	smart-b62d6d21-c26d-4c93-9ab6-b5f9aab064a5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147483363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_o tp_reset.1147483363
Directory	/workspace/67.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/68.flash_ctrl_connect.2153865993
Short name	T661
Test name
Test status
Simulation time	39817800 ps
CPU time	15.73 seconds
Started	Aug 13 06:23:26 PM PDT 24
Finished	Aug 13 06:23:42 PM PDT 24
Peak memory	284896 kb
Host	smart-c2998c47-e101-4407-ae2f-0ef9ce7c36e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2153865993 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.2153865993
Directory	/workspace/68.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/69.flash_ctrl_connect.507680168
Short name	T1055
Test name
Test status
Simulation time	18423600 ps
CPU time	16.07 seconds
Started	Aug 13 06:23:27 PM PDT 24
Finished	Aug 13 06:23:43 PM PDT 24
Peak memory	284848 kb
Host	smart-f1c1d570-33ae-425b-86ab-8378200abdea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=507680168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.507680168
Directory	/workspace/69.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/69.flash_ctrl_otp_reset.2571871319
Short name	T742
Test name
Test status
Simulation time	106521800 ps
CPU time	133.69 seconds
Started	Aug 13 06:23:26 PM PDT 24
Finished	Aug 13 06:25:40 PM PDT 24
Peak memory	260652 kb
Host	smart-6b1e2e6c-4fe3-4acf-b586-b4331924854c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571871319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_o tp_reset.2571871319
Directory	/workspace/69.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/7.flash_ctrl_alert_test.974386450
Short name	T89
Test name
Test status
Simulation time	82387000 ps
CPU time	14.23 seconds
Started	Aug 13 06:17:32 PM PDT 24
Finished	Aug 13 06:17:47 PM PDT 24
Peak memory	258968 kb
Host	smart-ee43b71c-e8b8-498b-9501-77df9ff6f6d8
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974386450 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.974386450
Directory	/workspace/7.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/7.flash_ctrl_connect.556259493
Short name	T504
Test name
Test status
Simulation time	22786900 ps
CPU time	15.95 seconds
Started	Aug 13 06:17:36 PM PDT 24
Finished	Aug 13 06:17:52 PM PDT 24
Peak memory	284836 kb
Host	smart-6cf40598-9126-4d21-b7f2-1692f695081d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=556259493 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.556259493
Directory	/workspace/7.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/7.flash_ctrl_disable.1084442863
Short name	T539
Test name
Test status
Simulation time	29044100 ps
CPU time	20.35 seconds
Started	Aug 13 06:17:35 PM PDT 24
Finished	Aug 13 06:17:56 PM PDT 24
Peak memory	274180 kb
Host	smart-14edf9fc-a04f-4eeb-9579-c9252e97f141
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084442863 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_disable.1084442863
Directory	/workspace/7.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/7.flash_ctrl_error_mp.240782862
Short name	T231
Test name
Test status
Simulation time	10629963400 ps
CPU time	2206.58 seconds
Started	Aug 13 06:17:27 PM PDT 24
Finished	Aug 13 06:54:14 PM PDT 24
Peak memory	265692 kb
Host	smart-392207bf-d095-4c58-9629-22084c9f0b48
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=240782862 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_mp.240782862
Directory	/workspace/7.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/7.flash_ctrl_error_prog_win.730279166
Short name	T1024
Test name
Test status
Simulation time	1924593700 ps
CPU time	955.18 seconds
Started	Aug 13 06:17:21 PM PDT 24
Finished	Aug 13 06:33:17 PM PDT 24
Peak memory	273868 kb
Host	smart-541ba04c-e2cf-4994-bcaf-0d06cbbe3198
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=730279166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.730279166
Directory	/workspace/7.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/7.flash_ctrl_fetch_code.2046898842
Short name	T44
Test name
Test status
Simulation time	4908698600 ps
CPU time	23.93 seconds
Started	Aug 13 06:17:23 PM PDT 24
Finished	Aug 13 06:17:47 PM PDT 24
Peak memory	263148 kb
Host	smart-3e49b286-1baa-43b0-8421-d851b980bbb5
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046898842 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetch_code.2046898842
Directory	/workspace/7.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.3945348165
Short name	T735
Test name
Test status
Simulation time	10032969700 ps
CPU time	56.47 seconds
Started	Aug 13 06:17:36 PM PDT 24
Finished	Aug 13 06:18:33 PM PDT 24
Peak memory	272512 kb
Host	smart-cd7f527b-c98e-4d7e-b0b2-30e5a6dd836c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945348165 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.3945348165
Directory	/workspace/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/7.flash_ctrl_hw_read_seed_err.845444577
Short name	T1101
Test name
Test status
Simulation time	15166600 ps
CPU time	13.51 seconds
Started	Aug 13 06:17:36 PM PDT 24
Finished	Aug 13 06:17:50 PM PDT 24
Peak memory	260676 kb
Host	smart-2d6930b7-9dc9-4c00-96f5-4facee097c70
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845444577 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_read_seed_err.845444577
Directory	/workspace/7.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/7.flash_ctrl_hw_rma_reset.1907551587
Short name	T769
Test name
Test status
Simulation time	40126644700 ps
CPU time	863.07 seconds
Started	Aug 13 06:17:22 PM PDT 24
Finished	Aug 13 06:31:45 PM PDT 24
Peak memory	265572 kb
Host	smart-5fc74246-7456-44bf-ae03-7c1fac9b0640
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907551587 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 7.flash_ctrl_hw_rma_reset.1907551587
Directory	/workspace/7.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/7.flash_ctrl_hw_sec_otp.1222804427
Short name	T562
Test name
Test status
Simulation time	4424791900 ps
CPU time	129.35 seconds
Started	Aug 13 06:17:23 PM PDT 24
Finished	Aug 13 06:19:33 PM PDT 24
Peak memory	261128 kb
Host	smart-f8846176-319e-4683-9f89-da338966e200
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222804427 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_h w_sec_otp.1222804427
Directory	/workspace/7.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/7.flash_ctrl_intr_rd.2112745813
Short name	T216
Test name
Test status
Simulation time	1492739500 ps
CPU time	176.34 seconds
Started	Aug 13 06:17:36 PM PDT 24
Finished	Aug 13 06:20:32 PM PDT 24
Peak memory	291568 kb
Host	smart-00c1fa57-8ec5-45c5-8c50-ff0c299ba2ab
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112745813 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas h_ctrl_intr_rd.2112745813
Directory	/workspace/7.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/7.flash_ctrl_intr_rd_slow_flash.1741234657
Short name	T324
Test name
Test status
Simulation time	25548716400 ps
CPU time	304.17 seconds
Started	Aug 13 06:17:36 PM PDT 24
Finished	Aug 13 06:22:40 PM PDT 24
Peak memory	292668 kb
Host	smart-010cd556-a9b3-4c00-b543-95c5ed5a8311
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741234657 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd_slow_flash.1741234657
Directory	/workspace/7.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/7.flash_ctrl_intr_wr.3969050710
Short name	T479
Test name
Test status
Simulation time	2098729400 ps
CPU time	66.32 seconds
Started	Aug 13 06:17:38 PM PDT 24
Finished	Aug 13 06:18:44 PM PDT 24
Peak memory	265784 kb
Host	smart-51ffb1d2-169d-4e14-aaa4-ff02d698e57e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969050710 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 7.flash_ctrl_intr_wr.3969050710
Directory	/workspace/7.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/7.flash_ctrl_intr_wr_slow_flash.457043719
Short name	T902
Test name
Test status
Simulation time	437450285600 ps
CPU time	424.72 seconds
Started	Aug 13 06:17:34 PM PDT 24
Finished	Aug 13 06:24:39 PM PDT 24
Peak memory	261296 kb
Host	smart-ef199079-110b-4252-8132-41cc5053c180
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457 043719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.457043719
Directory	/workspace/7.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/7.flash_ctrl_invalid_op.4223513551
Short name	T858
Test name
Test status
Simulation time	978413200 ps
CPU time	73.98 seconds
Started	Aug 13 06:17:22 PM PDT 24
Finished	Aug 13 06:18:37 PM PDT 24
Peak memory	263900 kb
Host	smart-4a111d89-2619-48f7-9ddb-556cf935d063
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223513551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.4223513551
Directory	/workspace/7.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/7.flash_ctrl_lcmgr_intg.1273019641
Short name	T290
Test name
Test status
Simulation time	26307400 ps
CPU time	13.65 seconds
Started	Aug 13 06:17:36 PM PDT 24
Finished	Aug 13 06:17:49 PM PDT 24
Peak memory	265376 kb
Host	smart-20bf3816-ad1f-4124-acaa-e1d8b36d72db
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273019641 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 7.flash_ctrl_lcmgr_intg.1273019641
Directory	/workspace/7.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/7.flash_ctrl_mp_regions.3439624733
Short name	T842
Test name
Test status
Simulation time	63656136500 ps
CPU time	386.3 seconds
Started	Aug 13 06:17:22 PM PDT 24
Finished	Aug 13 06:23:49 PM PDT 24
Peak memory	274988 kb
Host	smart-daf6b61c-47c1-48e2-88cc-860c5ed99bb0
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439624733 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_mp_regions.3439624733
Directory	/workspace/7.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/7.flash_ctrl_otp_reset.3790022938
Short name	T436
Test name
Test status
Simulation time	76900900 ps
CPU time	109.85 seconds
Started	Aug 13 06:17:23 PM PDT 24
Finished	Aug 13 06:19:13 PM PDT 24
Peak memory	263872 kb
Host	smart-95dfdc6a-e1ba-4160-8143-f648a84aff10
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790022938 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ot p_reset.3790022938
Directory	/workspace/7.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/7.flash_ctrl_phy_arb.4012405555
Short name	T820
Test name
Test status
Simulation time	805062700 ps
CPU time	454.28 seconds
Started	Aug 13 06:17:21 PM PDT 24
Finished	Aug 13 06:24:56 PM PDT 24
Peak memory	263772 kb
Host	smart-bb3fc1e6-0511-4b3d-8e61-7e81c8e74f7d
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4012405555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.4012405555
Directory	/workspace/7.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/7.flash_ctrl_prog_reset.3731411269
Short name	T597
Test name
Test status
Simulation time	34500400 ps
CPU time	13.61 seconds
Started	Aug 13 06:17:35 PM PDT 24
Finished	Aug 13 06:17:49 PM PDT 24
Peak memory	259200 kb
Host	smart-7e0f483e-bf53-4f5f-a15c-fb179e130dd1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731411269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 7.flash_ctrl_prog_reset.3731411269
Directory	/workspace/7.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rand_ops.1286369055
Short name	T797
Test name
Test status
Simulation time	1081609300 ps
CPU time	632.01 seconds
Started	Aug 13 06:17:21 PM PDT 24
Finished	Aug 13 06:27:53 PM PDT 24
Peak memory	285052 kb
Host	smart-1727f788-e9e2-44ca-ba66-19038c4be08d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1286369055 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.1286369055
Directory	/workspace/7.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/7.flash_ctrl_ro.4057701339
Short name	T228
Test name
Test status
Simulation time	1141256800 ps
CPU time	123.17 seconds
Started	Aug 13 06:17:25 PM PDT 24
Finished	Aug 13 06:19:28 PM PDT 24
Peak memory	292316 kb
Host	smart-0b125b44-0a24-47f6-9bf9-ed16fe1bb45d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057701339 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 7.flash_ctrl_ro.4057701339
Directory	/workspace/7.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/7.flash_ctrl_ro_derr.2268457178
Short name	T207
Test name
Test status
Simulation time	1168818900 ps
CPU time	170.62 seconds
Started	Aug 13 06:17:37 PM PDT 24
Finished	Aug 13 06:20:28 PM PDT 24
Peak memory	282320 kb
Host	smart-dad359cc-f426-49b0-a449-7ced42ccf602
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2268457178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.2268457178
Directory	/workspace/7.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/7.flash_ctrl_ro_serr.2104046179
Short name	T1062
Test name
Test status
Simulation time	6118544400 ps
CPU time	125.18 seconds
Started	Aug 13 06:17:36 PM PDT 24
Finished	Aug 13 06:19:42 PM PDT 24
Peak memory	282384 kb
Host	smart-26a1aff2-a275-4d6b-b85a-6959a72f41ab
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104046179 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 7.flash_ctrl_ro_serr.2104046179
Directory	/workspace/7.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rw.593618600
Short name	T212
Test name
Test status
Simulation time	3935840700 ps
CPU time	610.57 seconds
Started	Aug 13 06:17:22 PM PDT 24
Finished	Aug 13 06:27:33 PM PDT 24
Peak memory	314812 kb
Host	smart-45151c6f-a879-4bc3-ac36-16234545bd8d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593618600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw.593618600
Directory	/workspace/7.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rw_evict.1202091949
Short name	T1043
Test name
Test status
Simulation time	154760200 ps
CPU time	28.06 seconds
Started	Aug 13 06:17:39 PM PDT 24
Finished	Aug 13 06:18:07 PM PDT 24
Peak memory	274172 kb
Host	smart-15484380-5ad4-4531-b17c-6f2a9a111bf8
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202091949 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.fla sh_ctrl_rw_evict.1202091949
Directory	/workspace/7.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/7.flash_ctrl_rw_serr.2540999800
Short name	T508
Test name
Test status
Simulation time	30718212500 ps
CPU time	308.13 seconds
Started	Aug 13 06:17:35 PM PDT 24
Finished	Aug 13 06:22:43 PM PDT 24
Peak memory	290604 kb
Host	smart-61cb05ad-5f02-4cf9-966b-f687329861ae
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540999800 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 7.flash_ctrl_rw_serr.2540999800
Directory	/workspace/7.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/7.flash_ctrl_sec_info_access.2349387569
Short name	T654
Test name
Test status
Simulation time	3562748200 ps
CPU time	71.02 seconds
Started	Aug 13 06:17:32 PM PDT 24
Finished	Aug 13 06:18:43 PM PDT 24
Peak memory	265640 kb
Host	smart-94781a95-ada1-4953-999b-7998b8d97315
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2349387569 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.2349387569
Directory	/workspace/7.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/7.flash_ctrl_smoke.2594113604
Short name	T1010
Test name
Test status
Simulation time	86103200 ps
CPU time	145.56 seconds
Started	Aug 13 06:17:22 PM PDT 24
Finished	Aug 13 06:19:48 PM PDT 24
Peak memory	279980 kb
Host	smart-1405ab95-c6ee-4ba1-aa45-514ddb73f7a1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2594113604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.2594113604
Directory	/workspace/7.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/7.flash_ctrl_wo.1216304328
Short name	T583
Test name
Test status
Simulation time	7147914400 ps
CPU time	164.31 seconds
Started	Aug 13 06:17:23 PM PDT 24
Finished	Aug 13 06:20:07 PM PDT 24
Peak memory	265896 kb
Host	smart-19536cae-5223-46e3-88c0-1e3dcc7e1144
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216304328 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 7.flash_ctrl_wo.1216304328
Directory	/workspace/7.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/70.flash_ctrl_connect.4287215026
Short name	T871
Test name
Test status
Simulation time	16034800 ps
CPU time	15.98 seconds
Started	Aug 13 06:23:29 PM PDT 24
Finished	Aug 13 06:23:45 PM PDT 24
Peak memory	283512 kb
Host	smart-549e15ff-a4c5-4855-a2be-8114b5d1bbdd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4287215026 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.4287215026
Directory	/workspace/70.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/70.flash_ctrl_otp_reset.709935381
Short name	T998
Test name
Test status
Simulation time	73619200 ps
CPU time	134.23 seconds
Started	Aug 13 06:23:27 PM PDT 24
Finished	Aug 13 06:25:41 PM PDT 24
Peak memory	261652 kb
Host	smart-f3de1a1e-b832-4bc4-95bf-8d2b4509a48f
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709935381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_ot p_reset.709935381
Directory	/workspace/70.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/71.flash_ctrl_connect.2510396517
Short name	T124
Test name
Test status
Simulation time	38452000 ps
CPU time	13.28 seconds
Started	Aug 13 06:23:29 PM PDT 24
Finished	Aug 13 06:23:42 PM PDT 24
Peak memory	284732 kb
Host	smart-6355bb58-fa43-4a4f-8398-368da06c69eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2510396517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.2510396517
Directory	/workspace/71.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/71.flash_ctrl_otp_reset.1629061240
Short name	T1060
Test name
Test status
Simulation time	156090000 ps
CPU time	112.4 seconds
Started	Aug 13 06:23:24 PM PDT 24
Finished	Aug 13 06:25:16 PM PDT 24
Peak memory	261572 kb
Host	smart-99439df0-b214-457d-ae36-6a0a9305a153
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629061240 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_o tp_reset.1629061240
Directory	/workspace/71.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/72.flash_ctrl_connect.3628794201
Short name	T711
Test name
Test status
Simulation time	46885500 ps
CPU time	13.44 seconds
Started	Aug 13 06:23:27 PM PDT 24
Finished	Aug 13 06:23:41 PM PDT 24
Peak memory	275460 kb
Host	smart-33c3d604-57e5-4e1c-9f93-40ac73b7e692
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3628794201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.3628794201
Directory	/workspace/72.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/72.flash_ctrl_otp_reset.2248600918
Short name	T758
Test name
Test status
Simulation time	153866800 ps
CPU time	113.52 seconds
Started	Aug 13 06:23:24 PM PDT 24
Finished	Aug 13 06:25:18 PM PDT 24
Peak memory	260520 kb
Host	smart-39373ead-a024-4c4a-9825-cac74cb1050d
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248600918 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_o tp_reset.2248600918
Directory	/workspace/72.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/73.flash_ctrl_connect.1306869786
Short name	T557
Test name
Test status
Simulation time	27819200 ps
CPU time	15.74 seconds
Started	Aug 13 06:23:27 PM PDT 24
Finished	Aug 13 06:23:43 PM PDT 24
Peak memory	283440 kb
Host	smart-be156b8d-5f80-4e29-8eb5-8e84e61b1fdc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1306869786 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.1306869786
Directory	/workspace/73.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/73.flash_ctrl_otp_reset.2655763366
Short name	T610
Test name
Test status
Simulation time	39202700 ps
CPU time	132.49 seconds
Started	Aug 13 06:23:27 PM PDT 24
Finished	Aug 13 06:25:40 PM PDT 24
Peak memory	265704 kb
Host	smart-96a4e98d-907b-4698-b819-da346bd7e042
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655763366 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_o tp_reset.2655763366
Directory	/workspace/73.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/74.flash_ctrl_connect.3807164898
Short name	T544
Test name
Test status
Simulation time	13838800 ps
CPU time	15.92 seconds
Started	Aug 13 06:23:27 PM PDT 24
Finished	Aug 13 06:23:43 PM PDT 24
Peak memory	283720 kb
Host	smart-6a0f18a4-539a-469d-843c-1a9df28c7c19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3807164898 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.3807164898
Directory	/workspace/74.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/74.flash_ctrl_otp_reset.334669465
Short name	T705
Test name
Test status
Simulation time	60447500 ps
CPU time	113.39 seconds
Started	Aug 13 06:23:28 PM PDT 24
Finished	Aug 13 06:25:21 PM PDT 24
Peak memory	260828 kb
Host	smart-a70a216f-c641-4b23-95a3-144a8f052ee5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334669465 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_ot p_reset.334669465
Directory	/workspace/74.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/75.flash_ctrl_connect.1657202143
Short name	T433
Test name
Test status
Simulation time	14231400 ps
CPU time	15.99 seconds
Started	Aug 13 06:23:28 PM PDT 24
Finished	Aug 13 06:23:44 PM PDT 24
Peak memory	284840 kb
Host	smart-d737dd6d-7ac2-4e99-9f99-83cbd04615b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1657202143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.1657202143
Directory	/workspace/75.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/75.flash_ctrl_otp_reset.390432110
Short name	T515
Test name
Test status
Simulation time	86273500 ps
CPU time	131.22 seconds
Started	Aug 13 06:23:29 PM PDT 24
Finished	Aug 13 06:25:40 PM PDT 24
Peak memory	260664 kb
Host	smart-197c5bb9-be15-4c46-80bd-ccca2c8e7d9f
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390432110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_ot p_reset.390432110
Directory	/workspace/75.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/76.flash_ctrl_connect.329383318
Short name	T849
Test name
Test status
Simulation time	22443800 ps
CPU time	15.62 seconds
Started	Aug 13 06:23:28 PM PDT 24
Finished	Aug 13 06:23:44 PM PDT 24
Peak memory	283464 kb
Host	smart-c17ce06e-3ba1-4a5a-826c-0689243f1c1e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=329383318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.329383318
Directory	/workspace/76.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/76.flash_ctrl_otp_reset.1789518082
Short name	T472
Test name
Test status
Simulation time	42471100 ps
CPU time	133.21 seconds
Started	Aug 13 06:23:25 PM PDT 24
Finished	Aug 13 06:25:38 PM PDT 24
Peak memory	265288 kb
Host	smart-94adfef4-499f-48ff-8e58-57aaa0beb47b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789518082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_o tp_reset.1789518082
Directory	/workspace/76.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/77.flash_ctrl_connect.962644815
Short name	T494
Test name
Test status
Simulation time	22984800 ps
CPU time	15.8 seconds
Started	Aug 13 06:23:25 PM PDT 24
Finished	Aug 13 06:23:41 PM PDT 24
Peak memory	284784 kb
Host	smart-59a30533-820a-45e5-9564-ee6a5713156b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=962644815 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.962644815
Directory	/workspace/77.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/77.flash_ctrl_otp_reset.2074447518
Short name	T184
Test name
Test status
Simulation time	147377700 ps
CPU time	132.34 seconds
Started	Aug 13 06:23:26 PM PDT 24
Finished	Aug 13 06:25:38 PM PDT 24
Peak memory	261696 kb
Host	smart-7091ce03-404f-4d21-94c6-467d016bce4b
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074447518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_o tp_reset.2074447518
Directory	/workspace/77.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/78.flash_ctrl_connect.3008536513
Short name	T738
Test name
Test status
Simulation time	47420800 ps
CPU time	13.6 seconds
Started	Aug 13 06:23:27 PM PDT 24
Finished	Aug 13 06:23:40 PM PDT 24
Peak memory	283472 kb
Host	smart-7b74b37e-e31e-47bb-aafa-5e602c7a028a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3008536513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.3008536513
Directory	/workspace/78.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/78.flash_ctrl_otp_reset.763494024
Short name	T707
Test name
Test status
Simulation time	36051500 ps
CPU time	134.1 seconds
Started	Aug 13 06:23:28 PM PDT 24
Finished	Aug 13 06:25:42 PM PDT 24
Peak memory	260524 kb
Host	smart-b98745a9-a6ed-407e-9437-1b3b3a4b3ab5
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763494024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctr l_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_ot p_reset.763494024
Directory	/workspace/78.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/79.flash_ctrl_connect.168223239
Short name	T536
Test name
Test status
Simulation time	15580700 ps
CPU time	13.71 seconds
Started	Aug 13 06:23:26 PM PDT 24
Finished	Aug 13 06:23:40 PM PDT 24
Peak memory	284816 kb
Host	smart-54971584-38cc-4668-8099-633d7cf00057
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=168223239 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.168223239
Directory	/workspace/79.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/79.flash_ctrl_otp_reset.1407298525
Short name	T105
Test name
Test status
Simulation time	41699500 ps
CPU time	135.6 seconds
Started	Aug 13 06:23:27 PM PDT 24
Finished	Aug 13 06:25:43 PM PDT 24
Peak memory	261608 kb
Host	smart-a06f9dcb-d158-4b22-be88-6ddb515cce1e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407298525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_o tp_reset.1407298525
Directory	/workspace/79.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/8.flash_ctrl_alert_test.3537227435
Short name	T877
Test name
Test status
Simulation time	300062300 ps
CPU time	15.01 seconds
Started	Aug 13 06:17:55 PM PDT 24
Finished	Aug 13 06:18:10 PM PDT 24
Peak memory	258740 kb
Host	smart-d98e272f-ed88-4a6d-9735-8d9cb47d9620
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537227435 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.3 537227435
Directory	/workspace/8.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/8.flash_ctrl_connect.3391491717
Short name	T944
Test name
Test status
Simulation time	23216200 ps
CPU time	13.47 seconds
Started	Aug 13 06:17:56 PM PDT 24
Finished	Aug 13 06:18:09 PM PDT 24
Peak memory	283532 kb
Host	smart-8754cf31-e2ee-4d81-b4d7-97032db368d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3391491717 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.3391491717
Directory	/workspace/8.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/8.flash_ctrl_disable.1811450362
Short name	T1092
Test name
Test status
Simulation time	20270300 ps
CPU time	21.82 seconds
Started	Aug 13 06:17:56 PM PDT 24
Finished	Aug 13 06:18:18 PM PDT 24
Peak memory	273704 kb
Host	smart-f63852c1-c95e-4482-bb3c-6f342422e8f0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811450362 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_disable.1811450362
Directory	/workspace/8.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/8.flash_ctrl_error_mp.1246693798
Short name	T119
Test name
Test status
Simulation time	50530683800 ps
CPU time	2166.23 seconds
Started	Aug 13 06:17:46 PM PDT 24
Finished	Aug 13 06:53:53 PM PDT 24
Peak memory	265120 kb
Host	smart-d6e6c31f-48c3-4d67-9fe9-fa246d7b5a22
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1246693798 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_mp.1246693798
Directory	/workspace/8.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/8.flash_ctrl_error_prog_win.3555193575
Short name	T775
Test name
Test status
Simulation time	3324055000 ps
CPU time	892.17 seconds
Started	Aug 13 06:17:48 PM PDT 24
Finished	Aug 13 06:32:40 PM PDT 24
Peak memory	271080 kb
Host	smart-bc982381-0424-4fec-8af4-14ec18bee526
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3555193575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.3555193575
Directory	/workspace/8.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/8.flash_ctrl_fetch_code.1953417847
Short name	T885
Test name
Test status
Simulation time	909641900 ps
CPU time	21.82 seconds
Started	Aug 13 06:17:46 PM PDT 24
Finished	Aug 13 06:18:07 PM PDT 24
Peak memory	263132 kb
Host	smart-2ffe75de-8f61-44bb-a6a0-371352ba95d5
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953417847 -assert nopostproc +UVM_TESTNAME=flash_ctr l_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetch_code.1953417847
Directory	/workspace/8.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.3683466880
Short name	T196
Test name
Test status
Simulation time	10033749900 ps
CPU time	60.05 seconds
Started	Aug 13 06:17:56 PM PDT 24
Finished	Aug 13 06:18:56 PM PDT 24
Peak memory	289800 kb
Host	smart-79a9624b-445d-4bbe-bc61-52542dc10cec
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683466880 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.3683466880
Directory	/workspace/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.1947569506
Short name	T284
Test name
Test status
Simulation time	22332700 ps
CPU time	13.58 seconds
Started	Aug 13 06:17:57 PM PDT 24
Finished	Aug 13 06:18:10 PM PDT 24
Peak memory	265436 kb
Host	smart-fa765e94-511c-4f30-95b9-1dce56a8075a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947569506 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_read_seed_err.1947569506
Directory	/workspace/8.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/8.flash_ctrl_hw_rma_reset.1282328942
Short name	T621
Test name
Test status
Simulation time	160181914100 ps
CPU time	880.25 seconds
Started	Aug 13 06:17:47 PM PDT 24
Finished	Aug 13 06:32:27 PM PDT 24
Peak memory	265424 kb
Host	smart-3d9f6b9f-8ecf-4007-80d0-d8196a4f42b0
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282328942 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 8.flash_ctrl_hw_rma_reset.1282328942
Directory	/workspace/8.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/8.flash_ctrl_hw_sec_otp.2605176643
Short name	T666
Test name
Test status
Simulation time	2735072700 ps
CPU time	77.81 seconds
Started	Aug 13 06:17:47 PM PDT 24
Finished	Aug 13 06:19:05 PM PDT 24
Peak memory	263288 kb
Host	smart-6f169114-256f-436a-88b4-337ffcaca60e
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605176643 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_h w_sec_otp.2605176643
Directory	/workspace/8.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/8.flash_ctrl_intr_rd.4052826219
Short name	T728
Test name
Test status
Simulation time	1665010800 ps
CPU time	114.55 seconds
Started	Aug 13 06:17:48 PM PDT 24
Finished	Aug 13 06:19:42 PM PDT 24
Peak memory	291512 kb
Host	smart-1da277ec-5410-42ec-a3dd-5810dded5a84
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052826219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas h_ctrl_intr_rd.4052826219
Directory	/workspace/8.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/8.flash_ctrl_intr_rd_slow_flash.422041452
Short name	T730
Test name
Test status
Simulation time	23442553600 ps
CPU time	149.01 seconds
Started	Aug 13 06:17:46 PM PDT 24
Finished	Aug 13 06:20:15 PM PDT 24
Peak memory	293752 kb
Host	smart-9cda9afb-0af8-43d5-9533-f83e39b4ed6d
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422041452 -assert nopostpro c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd_slow_flash.422041452
Directory	/workspace/8.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/8.flash_ctrl_intr_wr.1212649616
Short name	T971
Test name
Test status
Simulation time	8077112000 ps
CPU time	71.13 seconds
Started	Aug 13 06:17:49 PM PDT 24
Finished	Aug 13 06:19:00 PM PDT 24
Peak memory	265736 kb
Host	smart-21e418a1-9f35-4f54-a114-59c3e5b2cbda
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212649616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 8.flash_ctrl_intr_wr.1212649616
Directory	/workspace/8.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_intr_wr_slow_flash.2791299940
Short name	T473
Test name
Test status
Simulation time	42306231300 ps
CPU time	199.99 seconds
Started	Aug 13 06:17:46 PM PDT 24
Finished	Aug 13 06:21:06 PM PDT 24
Peak memory	265700 kb
Host	smart-5286994e-133a-4bf5-bea6-54adf390c642
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279 1299940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.2791299940
Directory	/workspace/8.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/8.flash_ctrl_invalid_op.1188462324
Short name	T573
Test name
Test status
Simulation time	978207000 ps
CPU time	76.68 seconds
Started	Aug 13 06:17:42 PM PDT 24
Finished	Aug 13 06:18:59 PM PDT 24
Peak memory	264108 kb
Host	smart-05b646a3-bf20-4483-afb6-c4ea656685c5
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188462324 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.1188462324
Directory	/workspace/8.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/8.flash_ctrl_lcmgr_intg.525850072
Short name	T171
Test name
Test status
Simulation time	63379100 ps
CPU time	13.8 seconds
Started	Aug 13 06:17:56 PM PDT 24
Finished	Aug 13 06:18:10 PM PDT 24
Peak memory	260324 kb
Host	smart-547827f3-a9d2-4bab-a5b9-a6635ab6e9f1
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525850072 -assert nopostproc +UVM_TESTNAME =flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 8.flash_ctrl_lcmgr_intg.525850072
Directory	/workspace/8.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/8.flash_ctrl_mp_regions.4190478668
Short name	T639
Test name
Test status
Simulation time	6940987600 ps
CPU time	116.47 seconds
Started	Aug 13 06:17:50 PM PDT 24
Finished	Aug 13 06:19:47 PM PDT 24
Peak memory	265784 kb
Host	smart-f77a90d0-ee80-4634-aa19-20307d384324
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190478668 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_mp_regions.4190478668
Directory	/workspace/8.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/8.flash_ctrl_otp_reset.3721138522
Short name	T837
Test name
Test status
Simulation time	269324700 ps
CPU time	131.01 seconds
Started	Aug 13 06:17:48 PM PDT 24
Finished	Aug 13 06:19:59 PM PDT 24
Peak memory	261492 kb
Host	smart-49efe941-3727-4279-a776-b7e6ba133c13
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721138522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ot p_reset.3721138522
Directory	/workspace/8.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/8.flash_ctrl_phy_arb.1132953797
Short name	T836
Test name
Test status
Simulation time	87740500 ps
CPU time	407.43 seconds
Started	Aug 13 06:17:47 PM PDT 24
Finished	Aug 13 06:24:34 PM PDT 24
Peak memory	263772 kb
Host	smart-03e192cf-c12d-4f92-b776-9ec2937fd845
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1132953797 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.1132953797
Directory	/workspace/8.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/8.flash_ctrl_prog_reset.3467841962
Short name	T980
Test name
Test status
Simulation time	19961386000 ps
CPU time	168.63 seconds
Started	Aug 13 06:17:49 PM PDT 24
Finished	Aug 13 06:20:38 PM PDT 24
Peak memory	265832 kb
Host	smart-215a9cd4-69da-4d25-b629-f437ebac9ae0
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467841962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 8.flash_ctrl_prog_reset.3467841962
Directory	/workspace/8.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rand_ops.4247419158
Short name	T63
Test name
Test status
Simulation time	4624091000 ps
CPU time	811.79 seconds
Started	Aug 13 06:17:46 PM PDT 24
Finished	Aug 13 06:31:18 PM PDT 24
Peak memory	284404 kb
Host	smart-909fe243-7427-487d-9707-d7b8af891b14
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4247419158 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.4247419158
Directory	/workspace/8.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/8.flash_ctrl_re_evict.2932510774
Short name	T550
Test name
Test status
Simulation time	142397300 ps
CPU time	35.05 seconds
Started	Aug 13 06:17:56 PM PDT 24
Finished	Aug 13 06:18:31 PM PDT 24
Peak memory	274228 kb
Host	smart-9082bbe1-ced5-4da6-8455-c46a002edb7c
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932510774 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla sh_ctrl_re_evict.2932510774
Directory	/workspace/8.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/8.flash_ctrl_ro.2359641272
Short name	T778
Test name
Test status
Simulation time	7452699600 ps
CPU time	115.15 seconds
Started	Aug 13 06:17:45 PM PDT 24
Finished	Aug 13 06:19:40 PM PDT 24
Peak memory	289944 kb
Host	smart-c15a84ed-d870-4b2f-bb90-ea537fd5e319
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359641272 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 8.flash_ctrl_ro.2359641272
Directory	/workspace/8.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/8.flash_ctrl_ro_derr.2271687346
Short name	T658
Test name
Test status
Simulation time	635049600 ps
CPU time	146.93 seconds
Started	Aug 13 06:17:48 PM PDT 24
Finished	Aug 13 06:20:15 PM PDT 24
Peak memory	282424 kb
Host	smart-a5a9afc1-ed6d-4019-b889-0ed9f313060f
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2271687346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.2271687346
Directory	/workspace/8.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw.4176556370
Short name	T812
Test name
Test status
Simulation time	14972452900 ps
CPU time	648.96 seconds
Started	Aug 13 06:17:44 PM PDT 24
Finished	Aug 13 06:28:33 PM PDT 24
Peak memory	310860 kb
Host	smart-71c99c2d-2389-41ec-9487-161e7d40df2a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176556370 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_tes t +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam e 8.flash_ctrl_rw.4176556370
Directory	/workspace/8.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw_evict.2236067565
Short name	T568
Test name
Test status
Simulation time	28490900 ps
CPU time	29.83 seconds
Started	Aug 13 06:17:43 PM PDT 24
Finished	Aug 13 06:18:13 PM PDT 24
Peak memory	274184 kb
Host	smart-8eb6a417-0ec4-47a2-b31b-eeb8b43caad4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236067565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.fla sh_ctrl_rw_evict.2236067565
Directory	/workspace/8.flash_ctrl_rw_evict/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw_evict_all_en.3004951769
Short name	T890
Test name
Test status
Simulation time	29575800 ps
CPU time	30.88 seconds
Started	Aug 13 06:17:47 PM PDT 24
Finished	Aug 13 06:18:18 PM PDT 24
Peak memory	276112 kb
Host	smart-6681ee5e-744e-4841-9731-3cabe1ce924e
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004951769 -assert nopostproc +UVM_TESTNAME= flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict_all_en.3004951769
Directory	/workspace/8.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/8.flash_ctrl_rw_serr.581362439
Short name	T904
Test name
Test status
Simulation time	8199818100 ps
CPU time	163.26 seconds
Started	Aug 13 06:17:45 PM PDT 24
Finished	Aug 13 06:20:28 PM PDT 24
Peak memory	295932 kb
Host	smart-4904c2a0-3181-464b-a868-65f9580fe4e4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581362439 -assert nopostproc +UVM_TESTNAME=flash_ ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 8.flash_ctrl_rw_serr.581362439
Directory	/workspace/8.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/8.flash_ctrl_sec_info_access.13923640
Short name	T201
Test name
Test status
Simulation time	738575700 ps
CPU time	60.96 seconds
Started	Aug 13 06:17:56 PM PDT 24
Finished	Aug 13 06:18:57 PM PDT 24
Peak memory	264236 kb
Host	smart-469253fc-2115-4c8e-af5c-50a6788ec3be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=13923640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.13923640
Directory	/workspace/8.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/8.flash_ctrl_smoke.1613042277
Short name	T631
Test name
Test status
Simulation time	62224200 ps
CPU time	52.36 seconds
Started	Aug 13 06:17:37 PM PDT 24
Finished	Aug 13 06:18:29 PM PDT 24
Peak memory	271868 kb
Host	smart-8761fdfa-3e85-4775-916a-ce502d83a453
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1613042277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.1613042277
Directory	/workspace/8.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/8.flash_ctrl_wo.82061643
Short name	T696
Test name
Test status
Simulation time	4059483900 ps
CPU time	162.75 seconds
Started	Aug 13 06:17:47 PM PDT 24
Finished	Aug 13 06:20:30 PM PDT 24
Peak memory	260016 kb
Host	smart-30e63bc3-8022-417b-9923-545a46596742
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82061643 -assert nopostproc +UVM_TESTNAME=flash_ct rl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 8.flash_ctrl_wo.82061643
Directory	/workspace/8.flash_ctrl_wo/latest

Test location	/workspace/coverage/default/9.flash_ctrl_alert_test.2177721181
Short name	T458
Test name
Test status
Simulation time	97345000 ps
CPU time	13.71 seconds
Started	Aug 13 06:18:05 PM PDT 24
Finished	Aug 13 06:18:19 PM PDT 24
Peak memory	258864 kb
Host	smart-76e69cde-0071-4cd8-afc4-fcd3dbeef789
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177721181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.2 177721181
Directory	/workspace/9.flash_ctrl_alert_test/latest

Test location	/workspace/coverage/default/9.flash_ctrl_connect.4162728191
Short name	T123
Test name
Test status
Simulation time	14574500 ps
CPU time	15.88 seconds
Started	Aug 13 06:18:00 PM PDT 24
Finished	Aug 13 06:18:16 PM PDT 24
Peak memory	284844 kb
Host	smart-75b5f68f-98b4-403f-b7d3-654ebdaded7e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4162728191 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.4162728191
Directory	/workspace/9.flash_ctrl_connect/latest

Test location	/workspace/coverage/default/9.flash_ctrl_disable.1237698327
Short name	T189
Test name
Test status
Simulation time	11434400 ps
CPU time	22 seconds
Started	Aug 13 06:18:06 PM PDT 24
Finished	Aug 13 06:18:28 PM PDT 24
Peak memory	274168 kb
Host	smart-30160909-78f8-4dd4-8afd-726ad5725dab
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237698327 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_disable.1237698327
Directory	/workspace/9.flash_ctrl_disable/latest

Test location	/workspace/coverage/default/9.flash_ctrl_error_mp.573503226
Short name	T1088
Test name
Test status
Simulation time	10010245900 ps
CPU time	2469.5 seconds
Started	Aug 13 06:17:57 PM PDT 24
Finished	Aug 13 06:59:06 PM PDT 24
Peak memory	265708 kb
Host	smart-182407e8-5c04-476f-9939-fb9318cfb004
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +op_readonly_on_info1_partition=0 +op_readonly_on_info2_part ition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=573503226 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_mp.573503226
Directory	/workspace/9.flash_ctrl_error_mp/latest

Test location	/workspace/coverage/default/9.flash_ctrl_error_prog_win.1845133541
Short name	T813
Test name
Test status
Simulation time	6007622500 ps
CPU time	850.51 seconds
Started	Aug 13 06:17:54 PM PDT 24
Finished	Aug 13 06:32:05 PM PDT 24
Peak memory	273736 kb
Host	smart-7dfcf550-b7f3-4676-9d8f-c493403e9a65
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1845133541 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.1845133541
Directory	/workspace/9.flash_ctrl_error_prog_win/latest

Test location	/workspace/coverage/default/9.flash_ctrl_fetch_code.921885454
Short name	T941
Test name
Test status
Simulation time	939391400 ps
CPU time	25.06 seconds
Started	Aug 13 06:17:55 PM PDT 24
Finished	Aug 13 06:18:20 PM PDT 24
Peak memory	263108 kb
Host	smart-ae7cf5f9-86a8-42fb-a46f-602eb94b6945
User	root
Command	/workspace/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921885454 -assert nopostproc +UVM_TESTNAME=flash_ctrl _base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetch_code.921885454
Directory	/workspace/9.flash_ctrl_fetch_code/latest

Test location	/workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.2490602486
Short name	T1096
Test name
Test status
Simulation time	10012363400 ps
CPU time	129.4 seconds
Started	Aug 13 06:18:06 PM PDT 24
Finished	Aug 13 06:20:15 PM PDT 24
Peak memory	351956 kb
Host	smart-68844490-1522-4559-9d5d-1f1306387272
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490602486 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.2490602486
Directory	/workspace/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location	/workspace/coverage/default/9.flash_ctrl_hw_read_seed_err.2776488162
Short name	T1095
Test name
Test status
Simulation time	27367600 ps
CPU time	13.34 seconds
Started	Aug 13 06:18:08 PM PDT 24
Finished	Aug 13 06:18:21 PM PDT 24
Peak memory	258832 kb
Host	smart-e5dada5a-68dc-4681-858e-1ba88d70e801
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776488162 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_read_seed_err.2776488162
Directory	/workspace/9.flash_ctrl_hw_read_seed_err/latest

Test location	/workspace/coverage/default/9.flash_ctrl_hw_rma_reset.3424929373
Short name	T507
Test name
Test status
Simulation time	100143226800 ps
CPU time	896.39 seconds
Started	Aug 13 06:17:54 PM PDT 24
Finished	Aug 13 06:32:51 PM PDT 24
Peak memory	261556 kb
Host	smart-af2141ce-4cf9-449a-ae1f-5fc6a3e75403
User	root
Command	/workspace/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424929373 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_te st +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 9.flash_ctrl_hw_rma_reset.3424929373
Directory	/workspace/9.flash_ctrl_hw_rma_reset/latest

Test location	/workspace/coverage/default/9.flash_ctrl_hw_sec_otp.1730452822
Short name	T545
Test name
Test status
Simulation time	16976026500 ps
CPU time	125.56 seconds
Started	Aug 13 06:17:57 PM PDT 24
Finished	Aug 13 06:20:02 PM PDT 24
Peak memory	263716 kb
Host	smart-c20f0fae-5511-4455-9567-a5866105812c
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730452822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_h w_sec_otp.1730452822
Directory	/workspace/9.flash_ctrl_hw_sec_otp/latest

Test location	/workspace/coverage/default/9.flash_ctrl_intr_rd.4112663824
Short name	T40
Test name
Test status
Simulation time	29641329700 ps
CPU time	325.03 seconds
Started	Aug 13 06:18:01 PM PDT 24
Finished	Aug 13 06:23:26 PM PDT 24
Peak memory	285564 kb
Host	smart-2990a406-f84a-4883-9d30-e918b8d5baa4
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112663824 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas h_ctrl_intr_rd.4112663824
Directory	/workspace/9.flash_ctrl_intr_rd/latest

Test location	/workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.1899664706
Short name	T480
Test name
Test status
Simulation time	5809647600 ps
CPU time	140.72 seconds
Started	Aug 13 06:18:06 PM PDT 24
Finished	Aug 13 06:20:27 PM PDT 24
Peak memory	293516 kb
Host	smart-7613c89c-2176-4f14-97af-d5118d6a2461
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899664706 -assert nopostpr oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd_slow_flash.1899664706
Directory	/workspace/9.flash_ctrl_intr_rd_slow_flash/latest

Test location	/workspace/coverage/default/9.flash_ctrl_intr_wr.4119952684
Short name	T1085
Test name
Test status
Simulation time	7175705800 ps
CPU time	68.82 seconds
Started	Aug 13 06:18:05 PM PDT 24
Finished	Aug 13 06:19:14 PM PDT 24
Peak memory	262096 kb
Host	smart-d595acfd-b0ca-4a67-bd0a-7037b7defe20
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119952684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 9.flash_ctrl_intr_wr.4119952684
Directory	/workspace/9.flash_ctrl_intr_wr/latest

Test location	/workspace/coverage/default/9.flash_ctrl_intr_wr_slow_flash.1371101346
Short name	T435
Test name
Test status
Simulation time	83716487400 ps
CPU time	226.71 seconds
Started	Aug 13 06:18:04 PM PDT 24
Finished	Aug 13 06:21:51 PM PDT 24
Peak memory	260260 kb
Host	smart-34c5f841-f92b-4c10-a4fd-26221766c7ef
User	root
Command	/workspace/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137 1101346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.1371101346
Directory	/workspace/9.flash_ctrl_intr_wr_slow_flash/latest

Test location	/workspace/coverage/default/9.flash_ctrl_invalid_op.2114760761
Short name	T223
Test name
Test status
Simulation time	19017862800 ps
CPU time	78.22 seconds
Started	Aug 13 06:17:55 PM PDT 24
Finished	Aug 13 06:19:13 PM PDT 24
Peak memory	261212 kb
Host	smart-8b24cd23-0e96-4645-887f-b7b9e247a687
User	root
Command	/workspace/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114760761 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_o p_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.2114760761
Directory	/workspace/9.flash_ctrl_invalid_op/latest

Test location	/workspace/coverage/default/9.flash_ctrl_lcmgr_intg.1422210414
Short name	T960
Test name
Test status
Simulation time	16180400 ps
CPU time	13.43 seconds
Started	Aug 13 06:18:08 PM PDT 24
Finished	Aug 13 06:18:21 PM PDT 24
Peak memory	260688 kb
Host	smart-8184b41b-08d7-412c-9825-8087b112b8b5
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422210414 -assert nopostproc +UVM_TESTNAM E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 9.flash_ctrl_lcmgr_intg.1422210414
Directory	/workspace/9.flash_ctrl_lcmgr_intg/latest

Test location	/workspace/coverage/default/9.flash_ctrl_mp_regions.1925544868
Short name	T1022
Test name
Test status
Simulation time	43165039100 ps
CPU time	363.59 seconds
Started	Aug 13 06:17:56 PM PDT 24
Finished	Aug 13 06:24:00 PM PDT 24
Peak memory	274880 kb
Host	smart-3d88e736-1042-428b-a673-5f55d326b46f
User	root
Command	/workspace/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err +op_readonly_on_info1_partition=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925544868 -asser t nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_mp_regions.1925544868
Directory	/workspace/9.flash_ctrl_mp_regions/latest

Test location	/workspace/coverage/default/9.flash_ctrl_otp_reset.2342947538
Short name	T975
Test name
Test status
Simulation time	69158400 ps
CPU time	132.27 seconds
Started	Aug 13 06:17:55 PM PDT 24
Finished	Aug 13 06:20:08 PM PDT 24
Peak memory	261504 kb
Host	smart-fcec83fc-9081-420b-bb97-6e6775c28b75
User	root
Command	/workspace/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342947538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ct rl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ot p_reset.2342947538
Directory	/workspace/9.flash_ctrl_otp_reset/latest

Test location	/workspace/coverage/default/9.flash_ctrl_phy_arb.3616337852
Short name	T700
Test name
Test status
Simulation time	87813100 ps
CPU time	194.38 seconds
Started	Aug 13 06:17:56 PM PDT 24
Finished	Aug 13 06:21:10 PM PDT 24
Peak memory	263688 kb
Host	smart-784d0c8a-380c-4438-960b-132aae20b626
User	root
Command	/workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3616337852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.3616337852
Directory	/workspace/9.flash_ctrl_phy_arb/latest

Test location	/workspace/coverage/default/9.flash_ctrl_prog_reset.4029450040
Short name	T697
Test name
Test status
Simulation time	21360300 ps
CPU time	13.89 seconds
Started	Aug 13 06:18:01 PM PDT 24
Finished	Aug 13 06:18:15 PM PDT 24
Peak memory	259536 kb
Host	smart-bfdf0b49-dcb9-4236-bdfb-aacb7e539401
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029450040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 9.flash_ctrl_prog_reset.4029450040
Directory	/workspace/9.flash_ctrl_prog_reset/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rand_ops.1340783208
Short name	T151
Test name
Test status
Simulation time	289979300 ps
CPU time	696.73 seconds
Started	Aug 13 06:17:55 PM PDT 24
Finished	Aug 13 06:29:31 PM PDT 24
Peak memory	283092 kb
Host	smart-81836939-f3c3-4a40-be24-645c8b041a51
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1340783208 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.1340783208
Directory	/workspace/9.flash_ctrl_rand_ops/latest

Test location	/workspace/coverage/default/9.flash_ctrl_re_evict.1523592160
Short name	T222
Test name
Test status
Simulation time	68347300 ps
CPU time	34.32 seconds
Started	Aug 13 06:18:05 PM PDT 24
Finished	Aug 13 06:18:40 PM PDT 24
Peak memory	276168 kb
Host	smart-51b93d27-67b4-47a3-b417-41a0a54fa46a
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523592160 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_S EQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.fla sh_ctrl_re_evict.1523592160
Directory	/workspace/9.flash_ctrl_re_evict/latest

Test location	/workspace/coverage/default/9.flash_ctrl_ro.2682426243
Short name	T947
Test name
Test status
Simulation time	2414265900 ps
CPU time	131.7 seconds
Started	Aug 13 06:17:54 PM PDT 24
Finished	Aug 13 06:20:06 PM PDT 24
Peak memory	291992 kb
Host	smart-a5b1aa9c-7573-4fc5-91eb-09137efe23a7
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682426243 -assert nopostproc +UVM_TESTNAME=fla sh_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 9.flash_ctrl_ro.2682426243
Directory	/workspace/9.flash_ctrl_ro/latest

Test location	/workspace/coverage/default/9.flash_ctrl_ro_derr.1528846775
Short name	T258
Test name
Test status
Simulation time	610676000 ps
CPU time	161.02 seconds
Started	Aug 13 06:17:56 PM PDT 24
Finished	Aug 13 06:20:37 PM PDT 24
Peak memory	282396 kb
Host	smart-95189108-756a-41ae-8d64-522da09c6319
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1528846775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.1528846775
Directory	/workspace/9.flash_ctrl_ro_derr/latest

Test location	/workspace/coverage/default/9.flash_ctrl_ro_serr.1832464624
Short name	T870
Test name
Test status
Simulation time	632052800 ps
CPU time	140.42 seconds
Started	Aug 13 06:17:55 PM PDT 24
Finished	Aug 13 06:20:15 PM PDT 24
Peak memory	282416 kb
Host	smart-0c6fa365-a58e-499e-a581-7c3b0ce85e47
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832464624 -assert nopostproc +UVM_ TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 9.flash_ctrl_ro_serr.1832464624
Directory	/workspace/9.flash_ctrl_ro_serr/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rw.208076066
Short name	T1031
Test name
Test status
Simulation time	8827519700 ps
CPU time	588.81 seconds
Started	Aug 13 06:17:54 PM PDT 24
Finished	Aug 13 06:27:43 PM PDT 24
Peak memory	310508 kb
Host	smart-bf8ae7a0-9dab-4afd-9687-402bf4fdf7e9
User	root
Command	/workspace/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208076066 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw.208076066
Directory	/workspace/9.flash_ctrl_rw/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rw_derr.2340420133
Short name	T1056
Test name
Test status
Simulation time	1138554700 ps
CPU time	174.2 seconds
Started	Aug 13 06:18:04 PM PDT 24
Finished	Aug 13 06:20:58 PM PDT 24
Peak memory	282444 kb
Host	smart-29c208d7-7f7c-434a-ab78-c0f1db3dd762
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340420133 -as sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_derr.2340420133
Directory	/workspace/9.flash_ctrl_rw_derr/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rw_evict_all_en.382469919
Short name	T412
Test name
Test status
Simulation time	78346600 ps
CPU time	28.8 seconds
Started	Aug 13 06:18:05 PM PDT 24
Finished	Aug 13 06:18:34 PM PDT 24
Peak memory	268068 kb
Host	smart-b005e035-5e1d-4b3f-9bd3-155b66fe7611
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382469919 -assert nopostproc +UVM_TESTNAME=f lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict_all_en.382469919
Directory	/workspace/9.flash_ctrl_rw_evict_all_en/latest

Test location	/workspace/coverage/default/9.flash_ctrl_rw_serr.2485867534
Short name	T368
Test name
Test status
Simulation time	2798995200 ps
CPU time	190.88 seconds
Started	Aug 13 06:17:55 PM PDT 24
Finished	Aug 13 06:21:06 PM PDT 24
Peak memory	282396 kb
Host	smart-f6850639-c8d5-4b78-ba2b-60045ad36578
User	root
Command	/workspace/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=1000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485867534 -assert nopostproc +UVM_TESTNAME=flash _ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 9.flash_ctrl_rw_serr.2485867534
Directory	/workspace/9.flash_ctrl_rw_serr/latest

Test location	/workspace/coverage/default/9.flash_ctrl_sec_info_access.1003328840
Short name	T384
Test name
Test status
Simulation time	586519900 ps
CPU time	67.83 seconds
Started	Aug 13 06:18:05 PM PDT 24
Finished	Aug 13 06:19:13 PM PDT 24
Peak memory	264324 kb
Host	smart-d07df67c-6db5-4f51-b567-3b0999e2a64a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1003328840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.1003328840
Directory	/workspace/9.flash_ctrl_sec_info_access/latest

Test location	/workspace/coverage/default/9.flash_ctrl_smoke.1902389923
Short name	T30
Test name
Test status
Simulation time	158835700 ps
CPU time	192.81 seconds
Started	Aug 13 06:17:55 PM PDT 24
Finished	Aug 13 06:21:07 PM PDT 24
Peak memory	278724 kb
Host	smart-606db18e-6d54-413e-89ca-d8a07f8a74cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1902389923 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.1902389923
Directory	/workspace/9.flash_ctrl_smoke/latest

Test location	/workspace/coverage/default/9.flash_ctrl_wo.115520407
Short name	T702
Test name
Test status
Simulation time	5801767000 ps
CPU time	131.18 seconds
Started	Aug 13 06:17:56 PM PDT 24
Finished	Aug 13 06:20:07 PM PDT 24
Peak memory	259940 kb
Host	smart-91ae2fd4-d2d5-4823-be36-e364185a2d84
User	root
Command	/workspace/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115520407 -assert nopostproc +UVM_TESTNAME=flash_c trl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 9.flash_ctrl_wo.115520407
Directory	/workspace/9.flash_ctrl_wo/latest

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