Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	27452404	1		T1	15910		T2	9544		T3	35155
full_word	7880304	1		T1	34966		T2	4405		T3	19060

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	35332418	1		T1	50876		T2	13949		T3	54215
auto[TlIntgErrCmd]	103	1		T107	3		T109	3		T227	2
auto[TlIntgErrData]	82	1		T107	3		T109	3		T227	1
auto[TlIntgErrBoth]	105	1		T107	4		T109	4		T227	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30732225	1		T1	40852		T2	9208		T3	39945
auto[1]	4600483	1		T1	10024		T2	4741		T3	14270

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	26682102	1		T1	10958		T2	9207		T3	33317
auto[TlIntgErrNone]	partial	auto[1]	770040	1		T1	4952		T2	337		T3	1838
auto[TlIntgErrNone]	full_word	auto[0]	4049999	1		T1	29894		T2	1		T3	6628
auto[TlIntgErrNone]	full_word	auto[1]	3830277	1		T1	5072		T2	4404		T3	12432
auto[TlIntgErrCmd]	partial	auto[0]	35	1		T107	1		T242	2		T244	2
auto[TlIntgErrCmd]	partial	auto[1]	58	1		T107	2		T109	3		T227	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T286	1		T287	1		T274	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T281	1		T274	1		T382	2
auto[TlIntgErrData]	partial	auto[0]	37	1		T107	2		T109	1		T227	1
auto[TlIntgErrData]	partial	auto[1]	35	1		T107	1		T109	2		T242	4
auto[TlIntgErrData]	full_word	auto[0]	4	1		T243	1		T286	1		T274	1
auto[TlIntgErrData]	full_word	auto[1]	6	1		T243	1		T281	1		T274	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1		T107	1		T109	1		T227	5
auto[TlIntgErrBoth]	partial	auto[1]	55	1		T107	3		T109	2		T242	5
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T242	1		T244	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T109	1		T227	2		T287	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	21440	1		T107	8		T108	129		T109	10
full_word	3798380	1		T1	16958		T4	235		T22	10

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3819546	1		T1	16958		T4	235		T22	10
auto[TlIntgErrCmd]	80	1		T107	1		T109	2		T227	2
auto[TlIntgErrData]	101	1		T107	3		T109	2		T227	5
auto[TlIntgErrBoth]	93	1		T107	5		T109	6		T227	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3792218	1		T1	16958		T4	235		T22	10
auto[1]	27602	1		T107	5		T108	138		T109	3

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1489	1		T108	6		T224	3		T225	53
auto[TlIntgErrNone]	partial	auto[1]	19701	1		T108	123		T224	21		T225	365
auto[TlIntgErrNone]	full_word	auto[0]	3790619	1		T1	16958		T4	235		T22	10
auto[TlIntgErrNone]	full_word	auto[1]	7737	1		T108	15		T224	3		T225	92
auto[TlIntgErrCmd]	partial	auto[0]	24	1		T109	2		T243	1		T281	3
auto[TlIntgErrCmd]	partial	auto[1]	53	1		T107	1		T227	2		T242	5
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T274	1		T268	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	1	1		T381	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	46	1		T107	3		T109	1		T227	2
auto[TlIntgErrData]	partial	auto[1]	48	1		T109	1		T227	3		T242	3
auto[TlIntgErrData]	full_word	auto[0]	4	1		T242	1		T269	1		T382	2
auto[TlIntgErrData]	full_word	auto[1]	3	1		T382	1		T268	1		T381	1
auto[TlIntgErrBoth]	partial	auto[0]	31	1		T107	1		T109	4		T242	2
auto[TlIntgErrBoth]	partial	auto[1]	48	1		T107	3		T109	2		T227	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T281	1		T286	1		T382	1
auto[TlIntgErrBoth]	full_word	auto[1]	11	1		T107	1		T227	1		T242	2