Unified Coverage Report :: Group :: dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg

Group : dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	98.41	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_lockable_field_cov.sv

315 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
lockable_field_cov_of_flash_ctrl_core_reg_block.addr.start	50.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.control.erase_sel	50.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.control.info_sel	50.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.control.num	50.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.control.op	50.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.control.partition_sel	50.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.control.prog_sel	50.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.control.start	50.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.normal	50.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.repair	50.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_bank_cfg_shadowed.erase_en_0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_bank_cfg_shadowed.erase_en_1	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_0.base	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_0.size	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_1.base	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_1.size	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_2.base	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_2.size	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_3.base	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_3.size	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_4.base	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_4.size	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_5.base	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_5.size	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_6.base	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_6.size	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_7.base	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_7.size	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr1.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr1.field1	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr10.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr11.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr12.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr13.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr13.field1	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr14.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr14.field1	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr15.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr15.field1	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr16.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr16.field1	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr17.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr17.field1	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr18.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr19.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field1	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field2	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field3	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field4	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field5	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field6	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field7	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field8	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field9	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr4.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr4.field1	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr4.field2	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr4.field3	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field1	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field2	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field3	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field4	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field1	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field2	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field3	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field4	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field5	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field6	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field7	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field8	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr7.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr7.field1	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr8.field0	100.00	1	100	1	64	64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr9.field0	100.00	1	100	1	64	64

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.addr.start

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.addr.start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	1	1	50.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.addr.start

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	1	1	50.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.control.erase_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.erase_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	1	1	50.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.erase_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	1	1	50.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.control.info_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.info_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	1	1	50.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.info_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	1	1	50.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.control.num

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.num

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	1	1	50.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.num

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	1	1	50.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.control.op

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	1	1	50.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.op

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	1	1	50.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.control.partition_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.partition_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	1	1	50.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.partition_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	1	1	50.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.control.prog_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.prog_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	1	1	50.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.prog_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	1	1	50.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.control.start

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.start

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	1	1	50.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.start

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	1	1	50.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.normal

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.normal

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	1	1	50.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.normal

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	1	1	50.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.repair

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
50.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.repair

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	1	1	50.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.repair

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	1	1	50.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.ecc_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.ecc_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.ecc_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.erase_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.erase_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.erase_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.he_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.he_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.he_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.prog_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.prog_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.prog_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.rd_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.rd_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.rd_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.scramble_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.scramble_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.scramble_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.ecc_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.ecc_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.ecc_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.erase_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.erase_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.erase_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.he_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.he_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.he_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.prog_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.prog_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.prog_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.rd_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.rd_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.rd_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.scramble_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.scramble_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.scramble_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.ecc_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.ecc_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.ecc_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.erase_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.erase_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.erase_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.he_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.he_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.he_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.prog_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.prog_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.prog_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.rd_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.rd_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.rd_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.scramble_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.scramble_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.scramble_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.ecc_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.ecc_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.ecc_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.erase_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.erase_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.erase_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.he_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.he_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.he_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.prog_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.prog_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.prog_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.rd_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.rd_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.rd_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.scramble_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.scramble_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.scramble_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.ecc_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.ecc_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.ecc_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.erase_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.erase_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.erase_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.he_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.he_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.he_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.prog_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.prog_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.prog_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.rd_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.rd_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.rd_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.scramble_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.scramble_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.scramble_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.ecc_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.ecc_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.ecc_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.erase_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.erase_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.erase_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.he_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.he_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.he_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.prog_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.prog_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.prog_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.rd_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.rd_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.rd_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.scramble_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.scramble_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.scramble_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.ecc_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.ecc_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.ecc_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.erase_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.erase_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.erase_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.he_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.he_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.he_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.prog_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.prog_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.prog_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.rd_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.rd_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.rd_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.scramble_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.scramble_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.scramble_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.ecc_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.ecc_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.ecc_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.erase_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.erase_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.erase_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.he_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.he_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.he_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.prog_en

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.prog_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.prog_en

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_regwen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[0]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1118	1		T70	128		T71	1		T107	10

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_regwen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[0]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	960	1		T211	8		T222	8		T383	5

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_regwen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[0]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1151	1		T211	8		T222	8		T383	8

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_regwen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[0]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1162	1		T211	8		T222	8		T383	8

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_regwen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[0]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	947	1		T211	8		T222	8		T383	8

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_regwen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[0]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	864	1		T211	6		T383	8		T384	3

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_regwen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[0]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	768	1		T211	3		T222	8		T383	6

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_regwen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[0]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	35	1		T211	7		T222	7		T383	7

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_regwen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[0]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	970	1		T95	6		T96	4		T97	3

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_regwen

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[0]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1035	1		T95	3		T96	6		T97	3

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	322	1		T70	24		T107	2		T109	3
auto[1]	779	1		T70	64		T71	1		T107	8

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	522	1		T70	64		T107	2		T109	2
auto[1]	776	1		T70	64		T71	1		T107	8

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	397	1		T70	40		T107	1		T109	3
auto[1]	778	1		T70	64		T71	1		T107	8

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	284	1		T70	16		T107	2		T109	3
auto[1]	772	1		T70	64		T71	1		T107	8

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	444	1		T70	48		T107	2		T109	3
auto[1]	747	1		T70	64		T71	1		T107	8

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	479	1		T70	56		T107	1		T109	3
auto[1]	773	1		T70	64		T71	1		T107	8

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	362	1		T70	32		T107	2		T109	3
auto[1]	774	1		T70	64		T71	1		T107	7

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	625	1		T70	24		T107	1		T109	4
auto[1]	640	1		T70	64		T71	1		T107	8

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	746	1		T70	64		T107	1		T109	4
auto[1]	724	1		T70	64		T71	1		T107	9

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	673	1		T70	40		T107	1		T109	4
auto[1]	679	1		T70	64		T71	1		T107	8

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	600	1		T70	16		T107	1		T109	3
auto[1]	632	1		T70	64		T71	1		T107	8

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	700	1		T70	48		T107	1		T109	3
auto[1]	692	1		T70	64		T71	1		T107	9

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	720	1		T70	56		T107	1		T109	4
auto[1]	703	1		T70	64		T71	1		T107	8

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	652	1		T70	32		T109	3		T252	1
auto[1]	657	1		T70	64		T71	1		T107	9

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	430	1		T70	24		T107	1		T109	4
auto[1]	626	1		T70	64		T71	1		T107	9

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	631	1		T70	64		T109	4		T252	2
auto[1]	631	1		T70	64		T71	1		T107	9

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	510	1		T70	40		T109	3		T252	2
auto[1]	631	1		T70	64		T71	1		T107	8

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	390	1		T70	16		T107	1		T109	4
auto[1]	630	1		T70	64		T71	1		T107	9

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	515	1		T70	48		T107	1		T109	4
auto[1]	639	1		T70	64		T71	1		T107	9

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	591	1		T70	56		T107	1		T109	4
auto[1]	631	1		T70	64		T71	1		T107	8

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	470	1		T70	32		T107	1		T109	4
auto[1]	627	1		T70	64		T107	8		T108	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	480	1		T70	88		T107	1		T108	1
auto[1]	452	1		T71	1		T107	9		T109	8

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	640	1		T70	128		T107	1		T108	1
auto[1]	490	1		T71	1		T107	8		T109	7

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	544	1		T70	104		T107	1		T108	1
auto[1]	478	1		T71	1		T107	9		T109	8

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	452	1		T70	80		T107	1		T108	1
auto[1]	444	1		T71	1		T107	9		T109	7

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	454	1		T70	112		T107	1		T108	1
auto[1]	477	1		T71	1		T107	9		T109	8

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	605	1		T70	120		T107	1		T108	1
auto[1]	479	1		T71	1		T107	8		T109	8

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	513	1		T70	96		T107	1		T108	1
auto[1]	461	1		T71	1		T107	9		T109	8

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	544	1		T70	88		T107	1		T109	3
auto[1]	655	1		T71	1		T107	9		T108	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	646	1		T70	128		T107	1		T109	3
auto[1]	726	1		T71	1		T107	8		T108	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	627	1		T70	104		T107	1		T109	3
auto[1]	656	1		T71	1		T107	9		T108	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	506	1		T70	80		T107	1		T109	3
auto[1]	646	1		T71	1		T107	8		T108	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	663	1		T70	112		T107	1		T109	3
auto[1]	651	1		T71	1		T107	9		T108	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	706	1		T70	120		T107	1		T109	3
auto[1]	652	1		T71	1		T107	9		T108	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	582	1		T70	96		T107	1		T109	2
auto[1]	654	1		T71	1		T107	8		T108	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	429	1		T70	24		T71	1		T107	2
auto[1]	680	1		T70	64		T107	8		T109	7

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	595	1		T70	64		T71	1		T107	2
auto[1]	723	1		T70	64		T107	8		T109	8

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	502	1		T70	40		T107	2		T108	1
auto[1]	586	1		T70	64		T107	8		T109	7

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	405	1		T70	16		T71	1		T107	2
auto[1]	664	1		T70	64		T107	8		T109	7

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	536	1		T70	48		T71	1		T107	2
auto[1]	706	1		T70	64		T107	8		T109	6

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	562	1		T70	56		T71	1		T107	2
auto[1]	709	1		T70	64		T107	8		T109	7

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	468	1		T70	32		T71	1		T107	2
auto[1]	630	1		T70	64		T107	8		T109	8

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	281	1		T70	24		T107	1		T109	5
auto[1]	823	1		T70	64		T71	1		T107	7

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	444	1		T70	64		T107	1		T109	7
auto[1]	866	1		T70	64		T71	1		T107	9

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	347	1		T70	40		T107	1		T109	7
auto[1]	835	1		T70	64		T71	1		T107	8

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	249	1		T70	16		T107	1		T109	7
auto[1]	816	1		T70	64		T71	1		T107	8

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	375	1		T70	48		T107	1		T109	7
auto[1]	749	1		T70	64		T71	1		T107	9

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	412	1		T70	56		T107	1		T109	7
auto[1]	753	1		T70	64		T71	1		T107	9

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	314	1		T70	32		T107	1		T109	6
auto[1]	826	1		T70	64		T71	1		T107	6

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	397	1		T70	88		T109	4		T241	1
auto[1]	751	1		T71	1		T107	9		T108	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	592	1		T70	128		T109	4		T241	1
auto[1]	761	1		T71	1		T107	10		T108	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	470	1		T70	104		T109	4		T241	1
auto[1]	717	1		T71	1		T107	10		T108	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	357	1		T70	80		T109	4		T241	1
auto[1]	756	1		T71	1		T107	9		T108	1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	515	1		T70	112		T109	4		T241	1
auto[1]	759	1		T71	1		T107	8		T108	1