Unified Coverage Report :: Module :: flash_phy_rd_buf_dep

Module : flash_phy_rd_buf_dep

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.59	100.00	86.36			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.59	100.00	86.36			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.59	100.00	86.36			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.60	100.00	90.39			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.59	100.00	86.36			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.59	100.00	86.36			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.54	100.00	90.17			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : flash_phy_rd_buf_dep

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	48	7	7	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
ALWAYS	76	6	6	100.00
ALWAYS	90	3	3	100.00
CONT_ASSIGN	97	1	1	100.00
ALWAYS	116	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
			MISSING_ELSE
54	1	1
55	1	1
			MISSING_ELSE
61	1	1
62	1	1
65	1	1
66	1	1
71	1	1
72	1	1
76	1	1
77	1	1
79	1	1
80	1	1
			MISSING_ELSE
82	1	1
83	1	1
			MISSING_ELSE
90	1	1
91	1	1
92	1	1
97	1	1
116		unreachable
117		unreachable
118		unreachable

---

Cond Coverage for Module : flash_phy_rd_buf_dep

	Total	Covered	Percent
Conditions	22	19	86.36
Logical	22	19	86.36
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T19

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T19
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T19

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T3,T19
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T23
1	1	Covered	T1,T3,T19

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T3,T19
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T22,T23
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T19

---

Branch Coverage for Module : flash_phy_rd_buf_dep

	Line No.	Total	Covered	Percent
Branches		13	13	100.00
TERNARY	71	2	2	100.00
TERNARY	72	2	2	100.00
IF	51	2	2	100.00
IF	54	2	2	100.00
IF	76	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	((incr_buf_sel == decr_buf_sel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T19

	LineNo.	Expression
-1-:	72	((incr_buf_sel == decr_buf_sel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T19

	LineNo.	Expression
-1-:	51	if (wr_buf_i[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	54	if (rd_buf_i[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	79	if (fin_cnt_incr)
-3-:	82	if (fin_cnt_decr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T19
0	0	-	Covered	T1,T2,T3
0	-	1	Covered	T1,T3,T19
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_rd_buf_dep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferDecrUnderRun_A	771027290	6810111	0	0
BufferDepRsp_A	771027290	769339630	0	0
BufferIncrOverFlow_A	771027290	6810123	0	0
DepBufferRspOrder_A	771027291	16831096	0	0

BufferDecrUnderRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771027290	6810111	0	0
T1	245428	43559	0	0
T2	58246	0	0	0
T3	823144	5904	0	0
T4	15084	310	0	0
T5	0	17211	0	0
T9	6862	0	0	0
T17	2804	0	0	0
T18	6596	0	0	0
T19	4486	146	0	0
T20	2954	0	0	0
T21	3442	0	0	0
T22	0	10	0	0
T23	0	746	0	0
T25	0	48	0	0
T26	0	63	0	0
T42	0	127	0	0
T43	0	30	0	0
T45	0	8595	0	0
T47	0	2408	0	0

BufferDepRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771027290	769339630	0	0
T1	245428	245396	0	0
T2	58246	58106	0	0
T3	823144	786042	0	0
T4	15084	14968	0	0
T9	6862	5622	0	0
T17	2804	2508	0	0
T18	6596	6402	0	0
T19	4486	4354	0	0
T20	2954	2846	0	0
T21	3442	3332	0	0

BufferIncrOverFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771027290	6810123	0	0
T1	245428	43559	0	0
T2	58246	0	0	0
T3	823144	5904	0	0
T4	15084	310	0	0
T5	0	17211	0	0
T9	6862	0	0	0
T17	2804	0	0	0
T18	6596	0	0	0
T19	4486	146	0	0
T20	2954	0	0	0
T21	3442	0	0	0
T22	0	10	0	0
T23	0	746	0	0
T25	0	48	0	0
T26	0	63	0	0
T42	0	127	0	0
T43	0	30	0	0
T45	0	8595	0	0
T47	0	2408	0	0

DepBufferRspOrder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771027291	16831096	0	0
T1	245428	43600	0	0
T2	58246	32	0	0
T3	823144	13776	0	0
T4	15084	342	0	0
T5	0	8177	0	0
T9	6862	117	0	0
T11	0	131072	0	0
T17	2804	64	0	0
T18	6596	32	0	0
T19	4486	178	0	0
T20	2954	32	0	0
T21	3442	32	0	0
T23	0	478	0	0
T25	0	5	0	0
T26	0	26	0	0
T42	0	100	0	0
T43	0	30	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	48	7	7	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
ALWAYS	76	6	6	100.00
ALWAYS	90	3	3	100.00
CONT_ASSIGN	97	1	1	100.00
ALWAYS	116	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
			MISSING_ELSE
54	1	1
55	1	1
			MISSING_ELSE
61	1	1
62	1	1
65	1	1
66	1	1
71	1	1
72	1	1
76	1	1
77	1	1
79	1	1
80	1	1
			MISSING_ELSE
82	1	1
83	1	1
			MISSING_ELSE
90	1	1
91	1	1
92	1	1
97	1	1
116		unreachable
117		unreachable
118		unreachable

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

	Total	Covered	Percent
Conditions	22	19	86.36
Logical	22	19	86.36
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T22,T23
1	1	Covered	T1,T3,T4

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T22,T23
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

	Line No.	Total	Covered	Percent
Branches		13	13	100.00
TERNARY	71	2	2	100.00
TERNARY	72	2	2	100.00
IF	51	2	2	100.00
IF	54	2	2	100.00
IF	76	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	((incr_buf_sel == decr_buf_sel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	72	((incr_buf_sel == decr_buf_sel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	51	if (wr_buf_i[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	54	if (rd_buf_i[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	79	if (fin_cnt_incr)
-3-:	82	if (fin_cnt_decr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	-	Covered	T1,T2,T3
0	-	1	Covered	T1,T3,T4
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferDecrUnderRun_A	385513645	3503031	0	0
BufferDepRsp_A	385513645	384669815	0	0
BufferIncrOverFlow_A	385513645	3503039	0	0
DepBufferRspOrder_A	385513645	8936130	0	0

BufferDecrUnderRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	3503031	0	0
T1	122714	20043	0	0
T2	29123	0	0	0
T3	411572	5904	0	0
T4	7542	154	0	0
T5	0	9034	0	0
T9	3431	0	0	0
T17	1402	0	0	0
T18	3298	0	0	0
T19	2243	0	0	0
T20	1477	0	0	0
T21	1721	0	0	0
T22	0	10	0	0
T23	0	268	0	0
T25	0	43	0	0
T26	0	37	0	0
T42	0	27	0	0
T47	0	2408	0	0

BufferDepRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	384669815	0	0
T1	122714	122698	0	0
T2	29123	29053	0	0
T3	411572	393021	0	0
T4	7542	7484	0	0
T9	3431	2811	0	0
T17	1402	1254	0	0
T18	3298	3201	0	0
T19	2243	2177	0	0
T20	1477	1423	0	0
T21	1721	1666	0	0

BufferIncrOverFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	3503039	0	0
T1	122714	20043	0	0
T2	29123	0	0	0
T3	411572	5904	0	0
T4	7542	154	0	0
T5	0	9034	0	0
T9	3431	0	0	0
T17	1402	0	0	0
T18	3298	0	0	0
T19	2243	0	0	0
T20	1477	0	0	0
T21	1721	0	0	0
T22	0	10	0	0
T23	0	268	0	0
T25	0	43	0	0
T26	0	37	0	0
T42	0	27	0	0
T47	0	2408	0	0

DepBufferRspOrder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	8936130	0	0
T1	122714	20084	0	0
T2	29123	32	0	0
T3	411572	13776	0	0
T4	7542	186	0	0
T9	3431	117	0	0
T17	1402	64	0	0
T18	3298	32	0	0
T19	2243	32	0	0
T20	1477	32	0	0
T21	1721	32	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	48	7	7	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
ALWAYS	76	6	6	100.00
ALWAYS	90	3	3	100.00
CONT_ASSIGN	97	1	1	100.00
ALWAYS	116	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
			MISSING_ELSE
54	1	1
55	1	1
			MISSING_ELSE
61	1	1
62	1	1
65	1	1
66	1	1
71	1	1
72	1	1
76	1	1
77	1	1
79	1	1
80	1	1
			MISSING_ELSE
82	1	1
83	1	1
			MISSING_ELSE
90	1	1
91	1	1
92	1	1
97	1	1
116		unreachable
117		unreachable
118		unreachable

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

	Total	Covered	Percent
Conditions	22	19	86.36
Logical	22	19	86.36
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T110,T111
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T19,T4

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T19,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T19,T4

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T19,T4
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T23,T143
1	1	Covered	T1,T19,T4

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T19,T4
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T23,T143
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T19,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

	Line No.	Total	Covered	Percent
Branches		13	13	100.00
TERNARY	71	2	2	100.00
TERNARY	72	2	2	100.00
IF	51	2	2	100.00
IF	54	2	2	100.00
IF	76	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	((incr_buf_sel == decr_buf_sel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T19,T4

	LineNo.	Expression
-1-:	72	((incr_buf_sel == decr_buf_sel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T19,T4

	LineNo.	Expression
-1-:	51	if (wr_buf_i[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T19,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	54	if (rd_buf_i[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T19,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	79	if (fin_cnt_incr)
-3-:	82	if (fin_cnt_decr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T19,T4
0	0	-	Covered	T1,T2,T3
0	-	1	Covered	T1,T19,T4
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferDecrUnderRun_A	385513645	3307080	0	0
BufferDepRsp_A	385513645	384669815	0	0
BufferIncrOverFlow_A	385513645	3307084	0	0
DepBufferRspOrder_A	385513646	7894966	0	0

BufferDecrUnderRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	3307080	0	0
T1	122714	23516	0	0
T2	29123	0	0	0
T3	411572	0	0	0
T4	7542	156	0	0
T5	0	8177	0	0
T9	3431	0	0	0
T17	1402	0	0	0
T18	3298	0	0	0
T19	2243	146	0	0
T20	1477	0	0	0
T21	1721	0	0	0
T23	0	478	0	0
T25	0	5	0	0
T26	0	26	0	0
T42	0	100	0	0
T43	0	30	0	0
T45	0	8595	0	0

BufferDepRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	384669815	0	0
T1	122714	122698	0	0
T2	29123	29053	0	0
T3	411572	393021	0	0
T4	7542	7484	0	0
T9	3431	2811	0	0
T17	1402	1254	0	0
T18	3298	3201	0	0
T19	2243	2177	0	0
T20	1477	1423	0	0
T21	1721	1666	0	0

BufferIncrOverFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	3307084	0	0
T1	122714	23516	0	0
T2	29123	0	0	0
T3	411572	0	0	0
T4	7542	156	0	0
T5	0	8177	0	0
T9	3431	0	0	0
T17	1402	0	0	0
T18	3298	0	0	0
T19	2243	146	0	0
T20	1477	0	0	0
T21	1721	0	0	0
T23	0	478	0	0
T25	0	5	0	0
T26	0	26	0	0
T42	0	100	0	0
T43	0	30	0	0
T45	0	8595	0	0

DepBufferRspOrder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513646	7894966	0	0
T1	122714	23516	0	0
T2	29123	0	0	0
T3	411572	0	0	0
T4	7542	156	0	0
T5	0	8177	0	0
T9	3431	0	0	0
T11	0	131072	0	0
T17	1402	0	0	0
T18	3298	0	0	0
T19	2243	146	0	0
T20	1477	0	0	0
T21	1721	0	0	0
T23	0	478	0	0
T25	0	5	0	0
T26	0	26	0	0
T42	0	100	0	0
T43	0	30	0	0