Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T22

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T22
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T22
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T22

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T22
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T22

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T22

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1542054580	1538679260	0	0
CheckNGreaterZero_A	4168	4168	0	0
GntImpliesReady_A	1542054580	409705165	0	0
GntImpliesValid_A	1542054580	409705165	0	0
GrantKnown_A	1542054580	1538679260	0	0
IdxKnown_A	1542054580	1538679260	0	0
IndexIsCorrect_A	1542054580	409705165	0	0
NoReadyValidNoGrant_A	1542054580	180646245	0	0
Priority_A	1542054580	434038458	0	0
ReadyAndValidImplyGrant_A	1542054580	409705165	0	0
ReqAndReadyImplyGrant_A	1542054580	409705165	0	0
ReqImpliesValid_A	1542054580	434038458	0	0
ValidKnown_A	1542054580	1538679260	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1542054580	1538679260	0	0
T1	490856	490792	0	0
T2	116492	116212	0	0
T3	1646288	1572084	0	0
T4	30168	29936	0	0
T9	13724	11244	0	0
T17	5608	5016	0	0
T18	13192	12804	0	0
T19	8972	8708	0	0
T20	5908	5692	0	0
T21	6884	6664	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4168	4168	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T9	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0
T21	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1542054580	409705165	0	0
T1	490856	87200	0	0
T2	116492	34910	0	0
T3	1646288	357544	0	0
T4	30168	6284	0	0
T5	0	94410	0	0
T9	13724	258	0	0
T11	0	255794	0	0
T17	5608	148	0	0
T18	13192	64	0	0
T19	8972	356	0	0
T20	5908	64	0	0
T21	6884	64	0	0
T25	0	142	0	0
T42	0	2042	0	0
T66	0	16556	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1542054580	409705165	0	0
T1	490856	87200	0	0
T2	116492	34910	0	0
T3	1646288	357544	0	0
T4	30168	6284	0	0
T5	0	94410	0	0
T9	13724	258	0	0
T11	0	255794	0	0
T17	5608	148	0	0
T18	13192	64	0	0
T19	8972	356	0	0
T20	5908	64	0	0
T21	6884	64	0	0
T25	0	142	0	0
T42	0	2042	0	0
T66	0	16556	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1542054580	1538679260	0	0
T1	490856	490792	0	0
T2	116492	116212	0	0
T3	1646288	1572084	0	0
T4	30168	29936	0	0
T9	13724	11244	0	0
T17	5608	5016	0	0
T18	13192	12804	0	0
T19	8972	8708	0	0
T20	5908	5692	0	0
T21	6884	6664	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1542054580	1538679260	0	0
T1	490856	490792	0	0
T2	116492	116212	0	0
T3	1646288	1572084	0	0
T4	30168	29936	0	0
T9	13724	11244	0	0
T17	5608	5016	0	0
T18	13192	12804	0	0
T19	8972	8708	0	0
T20	5908	5692	0	0
T21	6884	6664	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1542054580	409705165	0	0
T1	490856	87200	0	0
T2	116492	34910	0	0
T3	1646288	357544	0	0
T4	30168	6284	0	0
T5	0	94410	0	0
T9	13724	258	0	0
T11	0	255794	0	0
T17	5608	148	0	0
T18	13192	64	0	0
T19	8972	356	0	0
T20	5908	64	0	0
T21	6884	64	0	0
T25	0	142	0	0
T42	0	2042	0	0
T66	0	16556	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1542054580	180646245	0	0
T1	490856	2696124	0	0
T2	116492	256	0	0
T3	1646288	91944	0	0
T4	30168	2304	0	0
T5	0	57470	0	0
T9	13724	936	0	0
T11	0	1048576	0	0
T17	5608	512	0	0
T18	13192	256	0	0
T19	8972	656	0	0
T20	5908	256	0	0
T21	6884	256	0	0
T23	0	1416	0	0
T25	0	28	0	0
T26	0	154	0	0
T42	0	310	0	0
T43	0	94	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1542054580	434038458	0	0
T1	490856	560700	0	0
T2	116492	34910	0	0
T3	1646288	357544	0	0
T4	30168	6844	0	0
T5	0	104544	0	0
T9	13724	258	0	0
T11	0	255794	0	0
T17	5608	148	0	0
T18	13192	64	0	0
T19	8972	356	0	0
T20	5908	64	0	0
T21	6884	64	0	0
T25	0	142	0	0
T42	0	2042	0	0
T66	0	16556	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1542054580	409705165	0	0
T1	490856	87200	0	0
T2	116492	34910	0	0
T3	1646288	357544	0	0
T4	30168	6284	0	0
T5	0	94410	0	0
T9	13724	258	0	0
T11	0	255794	0	0
T17	5608	148	0	0
T18	13192	64	0	0
T19	8972	356	0	0
T20	5908	64	0	0
T21	6884	64	0	0
T25	0	142	0	0
T42	0	2042	0	0
T66	0	16556	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1542054580	409705165	0	0
T1	490856	87200	0	0
T2	116492	34910	0	0
T3	1646288	357544	0	0
T4	30168	6284	0	0
T5	0	94410	0	0
T9	13724	258	0	0
T11	0	255794	0	0
T17	5608	148	0	0
T18	13192	64	0	0
T19	8972	356	0	0
T20	5908	64	0	0
T21	6884	64	0	0
T25	0	142	0	0
T42	0	2042	0	0
T66	0	16556	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1542054580	434038458	0	0
T1	490856	560700	0	0
T2	116492	34910	0	0
T3	1646288	357544	0	0
T4	30168	6844	0	0
T5	0	104544	0	0
T9	13724	258	0	0
T11	0	255794	0	0
T17	5608	148	0	0
T18	13192	64	0	0
T19	8972	356	0	0
T20	5908	64	0	0
T21	6884	64	0	0
T25	0	142	0	0
T42	0	2042	0	0
T66	0	16556	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1542054580	1538679260	0	0
T1	490856	490792	0	0
T2	116492	116212	0	0
T3	1646288	1572084	0	0
T4	30168	29936	0	0
T9	13724	11244	0	0
T17	5608	5016	0	0
T18	13192	12804	0	0
T19	8972	8708	0	0
T20	5908	5692	0	0
T21	6884	6664	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T22

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T22
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T22
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T22

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T22
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T22

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T22

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	385513645	384669815	0	0
CheckNGreaterZero_A	1042	1042	0	0
GntImpliesReady_A	385513645	107826674	0	0
GntImpliesValid_A	385513645	107826674	0	0
GrantKnown_A	385513645	384669815	0	0
IdxKnown_A	385513645	384669815	0	0
IndexIsCorrect_A	385513645	107826674	0	0
NoReadyValidNoGrant_A	385513645	47094067	0	0
Priority_A	385513645	113942078	0	0
ReadyAndValidImplyGrant_A	385513645	107826674	0	0
ReqAndReadyImplyGrant_A	385513645	107826674	0	0
ReqImpliesValid_A	385513645	113942078	0	0
ValidKnown_A	385513645	384669815	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	384669815	0	0
T1	122714	122698	0	0
T2	29123	29053	0	0
T3	411572	393021	0	0
T4	7542	7484	0	0
T9	3431	2811	0	0
T17	1402	1254	0	0
T18	3298	3201	0	0
T19	2243	2177	0	0
T20	1477	1423	0	0
T21	1721	1666	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	107826674	0	0
T1	122714	20084	0	0
T2	29123	7975	0	0
T3	411572	178772	0	0
T4	7542	912	0	0
T9	3431	129	0	0
T17	1402	64	0	0
T18	3298	32	0	0
T19	2243	32	0	0
T20	1477	32	0	0
T21	1721	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	107826674	0	0
T1	122714	20084	0	0
T2	29123	7975	0	0
T3	411572	178772	0	0
T4	7542	912	0	0
T9	3431	129	0	0
T17	1402	64	0	0
T18	3298	32	0	0
T19	2243	32	0	0
T20	1477	32	0	0
T21	1721	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	384669815	0	0
T1	122714	122698	0	0
T2	29123	29053	0	0
T3	411572	393021	0	0
T4	7542	7484	0	0
T9	3431	2811	0	0
T17	1402	1254	0	0
T18	3298	3201	0	0
T19	2243	2177	0	0
T20	1477	1423	0	0
T21	1721	1666	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	384669815	0	0
T1	122714	122698	0	0
T2	29123	29053	0	0
T3	411572	393021	0	0
T4	7542	7484	0	0
T9	3431	2811	0	0
T17	1402	1254	0	0
T18	3298	3201	0	0
T19	2243	2177	0	0
T20	1477	1423	0	0
T21	1721	1666	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	107826674	0	0
T1	122714	20084	0	0
T2	29123	7975	0	0
T3	411572	178772	0	0
T4	7542	912	0	0
T9	3431	129	0	0
T17	1402	64	0	0
T18	3298	32	0	0
T19	2243	32	0	0
T20	1477	32	0	0
T21	1721	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	47094067	0	0
T1	122714	628744	0	0
T2	29123	128	0	0
T3	411572	45972	0	0
T4	7542	500	0	0
T9	3431	468	0	0
T17	1402	256	0	0
T18	3298	128	0	0
T19	2243	128	0	0
T20	1477	128	0	0
T21	1721	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	113942078	0	0
T1	122714	129438	0	0
T2	29123	7975	0	0
T3	411572	178772	0	0
T4	7542	965	0	0
T9	3431	129	0	0
T17	1402	64	0	0
T18	3298	32	0	0
T19	2243	32	0	0
T20	1477	32	0	0
T21	1721	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	107826674	0	0
T1	122714	20084	0	0
T2	29123	7975	0	0
T3	411572	178772	0	0
T4	7542	912	0	0
T9	3431	129	0	0
T17	1402	64	0	0
T18	3298	32	0	0
T19	2243	32	0	0
T20	1477	32	0	0
T21	1721	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	107826674	0	0
T1	122714	20084	0	0
T2	29123	7975	0	0
T3	411572	178772	0	0
T4	7542	912	0	0
T9	3431	129	0	0
T17	1402	64	0	0
T18	3298	32	0	0
T19	2243	32	0	0
T20	1477	32	0	0
T21	1721	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	113942078	0	0
T1	122714	129438	0	0
T2	29123	7975	0	0
T3	411572	178772	0	0
T4	7542	965	0	0
T9	3431	129	0	0
T17	1402	64	0	0
T18	3298	32	0	0
T19	2243	32	0	0
T20	1477	32	0	0
T21	1721	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	384669815	0	0
T1	122714	122698	0	0
T2	29123	29053	0	0
T3	411572	393021	0	0
T4	7542	7484	0	0
T9	3431	2811	0	0
T17	1402	1254	0	0
T18	3298	3201	0	0
T19	2243	2177	0	0
T20	1477	1423	0	0
T21	1721	1666	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T22

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T22
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T22
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T22

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T22
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T22

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T22

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	385513645	384669815	0	0
CheckNGreaterZero_A	1042	1042	0	0
GntImpliesReady_A	385513645	107826608	0	0
GntImpliesValid_A	385513645	107826608	0	0
GrantKnown_A	385513645	384669815	0	0
IdxKnown_A	385513645	384669815	0	0
IndexIsCorrect_A	385513645	107826608	0	0
NoReadyValidNoGrant_A	385513645	47094012	0	0
Priority_A	385513645	113942067	0	0
ReadyAndValidImplyGrant_A	385513645	107826608	0	0
ReqAndReadyImplyGrant_A	385513645	107826608	0	0
ReqImpliesValid_A	385513645	113942067	0	0
ValidKnown_A	385513645	384669815	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	384669815	0	0
T1	122714	122698	0	0
T2	29123	29053	0	0
T3	411572	393021	0	0
T4	7542	7484	0	0
T9	3431	2811	0	0
T17	1402	1254	0	0
T18	3298	3201	0	0
T19	2243	2177	0	0
T20	1477	1423	0	0
T21	1721	1666	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	107826608	0	0
T1	122714	20084	0	0
T2	29123	7975	0	0
T3	411572	178772	0	0
T4	7542	912	0	0
T9	3431	129	0	0
T17	1402	64	0	0
T18	3298	32	0	0
T19	2243	32	0	0
T20	1477	32	0	0
T21	1721	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	107826608	0	0
T1	122714	20084	0	0
T2	29123	7975	0	0
T3	411572	178772	0	0
T4	7542	912	0	0
T9	3431	129	0	0
T17	1402	64	0	0
T18	3298	32	0	0
T19	2243	32	0	0
T20	1477	32	0	0
T21	1721	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	384669815	0	0
T1	122714	122698	0	0
T2	29123	29053	0	0
T3	411572	393021	0	0
T4	7542	7484	0	0
T9	3431	2811	0	0
T17	1402	1254	0	0
T18	3298	3201	0	0
T19	2243	2177	0	0
T20	1477	1423	0	0
T21	1721	1666	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	384669815	0	0
T1	122714	122698	0	0
T2	29123	29053	0	0
T3	411572	393021	0	0
T4	7542	7484	0	0
T9	3431	2811	0	0
T17	1402	1254	0	0
T18	3298	3201	0	0
T19	2243	2177	0	0
T20	1477	1423	0	0
T21	1721	1666	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	107826608	0	0
T1	122714	20084	0	0
T2	29123	7975	0	0
T3	411572	178772	0	0
T4	7542	912	0	0
T9	3431	129	0	0
T17	1402	64	0	0
T18	3298	32	0	0
T19	2243	32	0	0
T20	1477	32	0	0
T21	1721	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	47094012	0	0
T1	122714	628744	0	0
T2	29123	128	0	0
T3	411572	45972	0	0
T4	7542	500	0	0
T9	3431	468	0	0
T17	1402	256	0	0
T18	3298	128	0	0
T19	2243	128	0	0
T20	1477	128	0	0
T21	1721	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	113942067	0	0
T1	122714	129438	0	0
T2	29123	7975	0	0
T3	411572	178772	0	0
T4	7542	965	0	0
T9	3431	129	0	0
T17	1402	64	0	0
T18	3298	32	0	0
T19	2243	32	0	0
T20	1477	32	0	0
T21	1721	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	107826608	0	0
T1	122714	20084	0	0
T2	29123	7975	0	0
T3	411572	178772	0	0
T4	7542	912	0	0
T9	3431	129	0	0
T17	1402	64	0	0
T18	3298	32	0	0
T19	2243	32	0	0
T20	1477	32	0	0
T21	1721	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	107826608	0	0
T1	122714	20084	0	0
T2	29123	7975	0	0
T3	411572	178772	0	0
T4	7542	912	0	0
T9	3431	129	0	0
T17	1402	64	0	0
T18	3298	32	0	0
T19	2243	32	0	0
T20	1477	32	0	0
T21	1721	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	113942067	0	0
T1	122714	129438	0	0
T2	29123	7975	0	0
T3	411572	178772	0	0
T4	7542	965	0	0
T9	3431	129	0	0
T17	1402	64	0	0
T18	3298	32	0	0
T19	2243	32	0	0
T20	1477	32	0	0
T21	1721	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	384669815	0	0
T1	122714	122698	0	0
T2	29123	29053	0	0
T3	411572	393021	0	0
T4	7542	7484	0	0
T9	3431	2811	0	0
T17	1402	1254	0	0
T18	3298	3201	0	0
T19	2243	2177	0	0
T20	1477	1423	0	0
T21	1721	1666	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T17
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T17
1	1	Covered	T1,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T17

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T17

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	385513645	384669815	0	0
CheckNGreaterZero_A	1042	1042	0	0
GntImpliesReady_A	385513645	97026048	0	0
GntImpliesValid_A	385513645	97026048	0	0
GrantKnown_A	385513645	384669815	0	0
IdxKnown_A	385513645	384669815	0	0
IndexIsCorrect_A	385513645	97026048	0	0
NoReadyValidNoGrant_A	385513645	43229082	0	0
Priority_A	385513645	103077264	0	0
ReadyAndValidImplyGrant_A	385513645	97026048	0	0
ReqAndReadyImplyGrant_A	385513645	97026048	0	0
ReqImpliesValid_A	385513645	103077264	0	0
ValidKnown_A	385513645	384669815	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	384669815	0	0
T1	122714	122698	0	0
T2	29123	29053	0	0
T3	411572	393021	0	0
T4	7542	7484	0	0
T9	3431	2811	0	0
T17	1402	1254	0	0
T18	3298	3201	0	0
T19	2243	2177	0	0
T20	1477	1423	0	0
T21	1721	1666	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	97026048	0	0
T1	122714	23516	0	0
T2	29123	9480	0	0
T3	411572	0	0	0
T4	7542	2230	0	0
T5	0	47205	0	0
T9	3431	0	0	0
T11	0	127897	0	0
T17	1402	10	0	0
T18	3298	0	0	0
T19	2243	146	0	0
T20	1477	0	0	0
T21	1721	0	0	0
T25	0	71	0	0
T42	0	1021	0	0
T66	0	8278	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	97026048	0	0
T1	122714	23516	0	0
T2	29123	9480	0	0
T3	411572	0	0	0
T4	7542	2230	0	0
T5	0	47205	0	0
T9	3431	0	0	0
T11	0	127897	0	0
T17	1402	10	0	0
T18	3298	0	0	0
T19	2243	146	0	0
T20	1477	0	0	0
T21	1721	0	0	0
T25	0	71	0	0
T42	0	1021	0	0
T66	0	8278	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	384669815	0	0
T1	122714	122698	0	0
T2	29123	29053	0	0
T3	411572	393021	0	0
T4	7542	7484	0	0
T9	3431	2811	0	0
T17	1402	1254	0	0
T18	3298	3201	0	0
T19	2243	2177	0	0
T20	1477	1423	0	0
T21	1721	1666	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	384669815	0	0
T1	122714	122698	0	0
T2	29123	29053	0	0
T3	411572	393021	0	0
T4	7542	7484	0	0
T9	3431	2811	0	0
T17	1402	1254	0	0
T18	3298	3201	0	0
T19	2243	2177	0	0
T20	1477	1423	0	0
T21	1721	1666	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	97026048	0	0
T1	122714	23516	0	0
T2	29123	9480	0	0
T3	411572	0	0	0
T4	7542	2230	0	0
T5	0	47205	0	0
T9	3431	0	0	0
T11	0	127897	0	0
T17	1402	10	0	0
T18	3298	0	0	0
T19	2243	146	0	0
T20	1477	0	0	0
T21	1721	0	0	0
T25	0	71	0	0
T42	0	1021	0	0
T66	0	8278	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	43229082	0	0
T1	122714	719318	0	0
T2	29123	0	0	0
T3	411572	0	0	0
T4	7542	652	0	0
T5	0	28735	0	0
T9	3431	0	0	0
T11	0	524288	0	0
T17	1402	0	0	0
T18	3298	0	0	0
T19	2243	200	0	0
T20	1477	0	0	0
T21	1721	0	0	0
T23	0	708	0	0
T25	0	14	0	0
T26	0	77	0	0
T42	0	155	0	0
T43	0	47	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	103077264	0	0
T1	122714	150912	0	0
T2	29123	9480	0	0
T3	411572	0	0	0
T4	7542	2457	0	0
T5	0	52272	0	0
T9	3431	0	0	0
T11	0	127897	0	0
T17	1402	10	0	0
T18	3298	0	0	0
T19	2243	146	0	0
T20	1477	0	0	0
T21	1721	0	0	0
T25	0	71	0	0
T42	0	1021	0	0
T66	0	8278	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	97026048	0	0
T1	122714	23516	0	0
T2	29123	9480	0	0
T3	411572	0	0	0
T4	7542	2230	0	0
T5	0	47205	0	0
T9	3431	0	0	0
T11	0	127897	0	0
T17	1402	10	0	0
T18	3298	0	0	0
T19	2243	146	0	0
T20	1477	0	0	0
T21	1721	0	0	0
T25	0	71	0	0
T42	0	1021	0	0
T66	0	8278	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	97026048	0	0
T1	122714	23516	0	0
T2	29123	9480	0	0
T3	411572	0	0	0
T4	7542	2230	0	0
T5	0	47205	0	0
T9	3431	0	0	0
T11	0	127897	0	0
T17	1402	10	0	0
T18	3298	0	0	0
T19	2243	146	0	0
T20	1477	0	0	0
T21	1721	0	0	0
T25	0	71	0	0
T42	0	1021	0	0
T66	0	8278	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	103077264	0	0
T1	122714	150912	0	0
T2	29123	9480	0	0
T3	411572	0	0	0
T4	7542	2457	0	0
T5	0	52272	0	0
T9	3431	0	0	0
T11	0	127897	0	0
T17	1402	10	0	0
T18	3298	0	0	0
T19	2243	146	0	0
T20	1477	0	0	0
T21	1721	0	0	0
T25	0	71	0	0
T42	0	1021	0	0
T66	0	8278	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	384669815	0	0
T1	122714	122698	0	0
T2	29123	29053	0	0
T3	411572	393021	0	0
T4	7542	7484	0	0
T9	3431	2811	0	0
T17	1402	1254	0	0
T18	3298	3201	0	0
T19	2243	2177	0	0
T20	1477	1423	0	0
T21	1721	1666	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T17
1	0	Covered	T1,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T17
1	1	Covered	T1,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T17

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T2,T17

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	385513645	384669815	0	0
CheckNGreaterZero_A	1042	1042	0	0
GntImpliesReady_A	385513645	97025835	0	0
GntImpliesValid_A	385513645	97025835	0	0
GrantKnown_A	385513645	384669815	0	0
IdxKnown_A	385513645	384669815	0	0
IndexIsCorrect_A	385513645	97025835	0	0
NoReadyValidNoGrant_A	385513645	43229084	0	0
Priority_A	385513645	103077049	0	0
ReadyAndValidImplyGrant_A	385513645	97025835	0	0
ReqAndReadyImplyGrant_A	385513645	97025835	0	0
ReqImpliesValid_A	385513645	103077049	0	0
ValidKnown_A	385513645	384669815	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	384669815	0	0
T1	122714	122698	0	0
T2	29123	29053	0	0
T3	411572	393021	0	0
T4	7542	7484	0	0
T9	3431	2811	0	0
T17	1402	1254	0	0
T18	3298	3201	0	0
T19	2243	2177	0	0
T20	1477	1423	0	0
T21	1721	1666	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	97025835	0	0
T1	122714	23516	0	0
T2	29123	9480	0	0
T3	411572	0	0	0
T4	7542	2230	0	0
T5	0	47205	0	0
T9	3431	0	0	0
T11	0	127897	0	0
T17	1402	10	0	0
T18	3298	0	0	0
T19	2243	146	0	0
T20	1477	0	0	0
T21	1721	0	0	0
T25	0	71	0	0
T42	0	1021	0	0
T66	0	8278	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	97025835	0	0
T1	122714	23516	0	0
T2	29123	9480	0	0
T3	411572	0	0	0
T4	7542	2230	0	0
T5	0	47205	0	0
T9	3431	0	0	0
T11	0	127897	0	0
T17	1402	10	0	0
T18	3298	0	0	0
T19	2243	146	0	0
T20	1477	0	0	0
T21	1721	0	0	0
T25	0	71	0	0
T42	0	1021	0	0
T66	0	8278	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	384669815	0	0
T1	122714	122698	0	0
T2	29123	29053	0	0
T3	411572	393021	0	0
T4	7542	7484	0	0
T9	3431	2811	0	0
T17	1402	1254	0	0
T18	3298	3201	0	0
T19	2243	2177	0	0
T20	1477	1423	0	0
T21	1721	1666	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	384669815	0	0
T1	122714	122698	0	0
T2	29123	29053	0	0
T3	411572	393021	0	0
T4	7542	7484	0	0
T9	3431	2811	0	0
T17	1402	1254	0	0
T18	3298	3201	0	0
T19	2243	2177	0	0
T20	1477	1423	0	0
T21	1721	1666	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	97025835	0	0
T1	122714	23516	0	0
T2	29123	9480	0	0
T3	411572	0	0	0
T4	7542	2230	0	0
T5	0	47205	0	0
T9	3431	0	0	0
T11	0	127897	0	0
T17	1402	10	0	0
T18	3298	0	0	0
T19	2243	146	0	0
T20	1477	0	0	0
T21	1721	0	0	0
T25	0	71	0	0
T42	0	1021	0	0
T66	0	8278	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	43229084	0	0
T1	122714	719318	0	0
T2	29123	0	0	0
T3	411572	0	0	0
T4	7542	652	0	0
T5	0	28735	0	0
T9	3431	0	0	0
T11	0	524288	0	0
T17	1402	0	0	0
T18	3298	0	0	0
T19	2243	200	0	0
T20	1477	0	0	0
T21	1721	0	0	0
T23	0	708	0	0
T25	0	14	0	0
T26	0	77	0	0
T42	0	155	0	0
T43	0	47	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	103077049	0	0
T1	122714	150912	0	0
T2	29123	9480	0	0
T3	411572	0	0	0
T4	7542	2457	0	0
T5	0	52272	0	0
T9	3431	0	0	0
T11	0	127897	0	0
T17	1402	10	0	0
T18	3298	0	0	0
T19	2243	146	0	0
T20	1477	0	0	0
T21	1721	0	0	0
T25	0	71	0	0
T42	0	1021	0	0
T66	0	8278	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	97025835	0	0
T1	122714	23516	0	0
T2	29123	9480	0	0
T3	411572	0	0	0
T4	7542	2230	0	0
T5	0	47205	0	0
T9	3431	0	0	0
T11	0	127897	0	0
T17	1402	10	0	0
T18	3298	0	0	0
T19	2243	146	0	0
T20	1477	0	0	0
T21	1721	0	0	0
T25	0	71	0	0
T42	0	1021	0	0
T66	0	8278	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	97025835	0	0
T1	122714	23516	0	0
T2	29123	9480	0	0
T3	411572	0	0	0
T4	7542	2230	0	0
T5	0	47205	0	0
T9	3431	0	0	0
T11	0	127897	0	0
T17	1402	10	0	0
T18	3298	0	0	0
T19	2243	146	0	0
T20	1477	0	0	0
T21	1721	0	0	0
T25	0	71	0	0
T42	0	1021	0	0
T66	0	8278	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	103077049	0	0
T1	122714	150912	0	0
T2	29123	9480	0	0
T3	411572	0	0	0
T4	7542	2457	0	0
T5	0	52272	0	0
T9	3431	0	0	0
T11	0	127897	0	0
T17	1402	10	0	0
T18	3298	0	0	0
T19	2243	146	0	0
T20	1477	0	0	0
T21	1721	0	0	0
T25	0	71	0	0
T42	0	1021	0	0
T66	0	8278	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	384669815	0	0
T1	122714	122698	0	0
T2	29123	29053	0	0
T3	411572	393021	0	0
T4	7542	7484	0	0
T9	3431	2811	0	0
T17	1402	1254	0	0
T18	3298	3201	0	0
T19	2243	2177	0	0
T20	1477	1423	0	0
T21	1721	1666	0	0