Unified Coverage Report :: Module :: flash_phy_prog

Module : flash_phy_prog

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	96.92		100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog	99.38	100.00	96.92		100.00	100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog	99.38	100.00	96.92		100.00	100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	96.92		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.49	100.00	96.92	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.06	100.00	92.45		100.00	97.83	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	100.00	100.00		100.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	96.92		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.65	100.00	96.92	95.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.55	100.00	84.91		100.00	97.83	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	97.50	100.00		95.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Module : flash_phy_prog

	Total	Covered	Percent
Conditions	65	63	96.92
Logical	65	63	96.92
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T17

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T17

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T164,T86,T190
1	0	Covered	T164,T86,T190

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T17
1	1	Covered	T164,T86,T190

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T164,T86,T190
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T17

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T17
1	Covered	T2,T4,T66

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T17
1	0	Covered	T2,T3,T17
1	1	Covered	T2,T3,T17

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T17

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T17
1	1	Covered	T2,T4,T66

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T12,T13
1	Covered	T2,T4,T66

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T17
1	0	Covered	T2,T3,T17
1	1	Covered	T2,T3,T17

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T2,T3,T17
1	Covered	T2,T3,T17

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T17
1	0	Covered	T2,T3,T17
1	1	Covered	T2,T4,T66

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T6,T12,T13
1	Covered	T2,T4,T66

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T2,T4,T66
1	Covered	T3,T17,T5

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T17,T5
1	1	Covered	T3,T17,T5

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T17,T5
1	1	Covered	T3,T17,T5

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T17
1	1	0	Covered	T2,T3,T17
1	1	1	Covered	T2,T3,T4

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : flash_phy_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T3,T17,T5
StCalcMask	237	Covered	T3,T17,T5
StCalcPlainEcc	215	Covered	T2,T3,T17
StDisabled	193	Covered	T9,T10,T11
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T2,T3,T17
StPostPack	218	Covered	T2,T4,T66
StPrePack	195	Covered	T2,T4,T66
StReqFlash	237	Covered	T2,T3,T4
StScrambleData	244	Covered	T3,T17,T5
StWaitFlash	270	Covered	T2,T3,T4

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T3,T5,T25
StCalcMask->StScrambleData	244	Covered	T3,T17,T5
StCalcPlainEcc->StCalcMask	237	Covered	T3,T17,T5
StCalcPlainEcc->StReqFlash	237	Covered	T2,T4,T66
StIdle->StDisabled	193	Covered	T9,T10,T11
StIdle->StPackData	197	Covered	T2,T3,T17
StIdle->StPrePack	195	Covered	T2,T4,T66
StPackData->StCalcPlainEcc	215	Covered	T2,T3,T17
StPackData->StPostPack	218	Covered	T2,T4,T66
StPostPack->StCalcPlainEcc	231	Covered	T2,T4,T66
StPrePack->StPackData	205	Covered	T2,T4,T66
StReqFlash->StIdle	273	Covered	T2,T3,T4
StReqFlash->StWaitFlash	270	Covered	T2,T3,T4
StScrambleData->StCalcEcc	252	Covered	T3,T17,T5
StWaitFlash->StIdle	280	Covered	T2,T3,T4

---

Branch Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T17
0	0	1	Covered	T2,T3,T17
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T66
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T17
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T66
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T12,T13
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T17
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T66
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T17
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T2,T3,T17
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T2,T4,T66
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T6,T12,T13
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T3,T17,T5
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T2,T4,T66
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T3,T17,T5
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T3,T17,T5
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T3,T17,T5
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T3,T17,T5
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T17,T5
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T2,T3,T4
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T2,T3,T4
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T2,T3,T4
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T2,T3,T4
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T3,T4
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T4
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T6,T16

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T2,T3,T4
0	0	1	-	-	Covered	T3,T17,T5
0	0	0	1	-	Covered	T3,T17,T5
0	0	0	0	1	Covered	T2,T3,T17
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T17
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	771027290	2439664	0	0
PostPackRule_A	771027290	1878	0	0
PrePackRule_A	771027290	1350	0	0
WidthCheck_A	2084	2084	0	0
u_state_regs_A	771027290	769339630	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771027290	2439664	0	0
T2	58246	47	0	0
T3	823144	371	0	0
T4	15084	7	0	0
T5	0	529	0	0
T9	6862	0	0	0
T11	0	65920	0	0
T17	2804	0	0	0
T18	6596	0	0	0
T19	4486	0	0	0
T20	2954	0	0	0
T21	3442	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T42	0	5	0	0
T43	0	4	0	0
T45	0	155	0	0
T47	0	145	0	0
T63	3088	0	0	0
T65	0	1	0	0
T66	0	57	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771027290	1878	0	0
T2	58246	33	0	0
T3	823144	0	0	0
T4	15084	5	0	0
T9	6862	0	0	0
T17	2804	0	0	0
T18	6596	0	0	0
T19	4486	0	0	0
T20	2954	0	0	0
T21	3442	0	0	0
T35	0	7	0	0
T42	0	3	0	0
T43	0	4	0	0
T49	0	2	0	0
T63	3088	0	0	0
T66	0	32	0	0
T73	0	2	0	0
T74	0	3	0	0
T143	0	1	0	0
T232	0	2	0	0
T233	0	46	0	0
T234	0	2	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771027290	1350	0	0
T2	58246	16	0	0
T3	823144	0	0	0
T4	15084	2	0	0
T9	6862	0	0	0
T17	2804	0	0	0
T18	6596	0	0	0
T19	4486	0	0	0
T20	2954	0	0	0
T21	3442	0	0	0
T35	0	7	0	0
T42	0	3	0	0
T43	0	2	0	0
T48	0	1	0	0
T63	3088	0	0	0
T66	0	23	0	0
T73	0	5	0	0
T74	0	7	0	0
T90	0	13	0	0
T143	0	2	0	0
T233	0	27	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2084	2084	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T9	2	2	0	0
T17	2	2	0	0
T18	2	2	0	0
T19	2	2	0	0
T20	2	2	0	0
T21	2	2	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	771027290	769339630	0	0
T1	245428	245396	0	0
T2	58246	58106	0	0
T3	823144	786042	0	0
T4	15084	14968	0	0
T9	6862	5622	0	0
T17	2804	2508	0	0
T18	6596	6402	0	0
T19	4486	4354	0	0
T20	2954	2846	0	0
T21	3442	3332	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	63	96.92
Logical	65	63	96.92
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T164,T86,T190
1	0	Covered	T164,T86,T190

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T164,T86,T190

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T164,T86,T190
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T4,T66

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T4,T66

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T12,T13
1	Covered	T2,T4,T66

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T66
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T4,T66

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T6,T12,T13
1	Covered	T2,T4,T66

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T2,T4,T66
1	Covered	T3,T5,T11

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T3,T4

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T11
1	1	Covered	T3,T5,T11

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T11
1	1	Covered	T3,T5,T11

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T2,T3,T4
1	1	1	Covered	T2,T3,T4

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T3,T5,T11
StCalcMask	237	Covered	T3,T5,T11
StCalcPlainEcc	215	Covered	T2,T3,T4
StDisabled	193	Covered	T9,T10,T11
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T2,T3,T4
StPostPack	218	Covered	T2,T4,T66
StPrePack	195	Covered	T2,T4,T66
StReqFlash	237	Covered	T2,T3,T4
StScrambleData	244	Covered	T3,T5,T11
StWaitFlash	270	Covered	T2,T3,T4

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T3,T5,T11
StCalcMask->StScrambleData	244	Covered	T3,T5,T11
StCalcPlainEcc->StCalcMask	237	Covered	T3,T5,T11
StCalcPlainEcc->StReqFlash	237	Covered	T2,T4,T66
StIdle->StDisabled	193	Covered	T9,T10,T11
StIdle->StPackData	197	Covered	T2,T3,T4
StIdle->StPrePack	195	Covered	T2,T4,T66
StPackData->StCalcPlainEcc	215	Covered	T2,T3,T4
StPackData->StPostPack	218	Covered	T2,T4,T66
StPostPack->StCalcPlainEcc	231	Covered	T2,T4,T66
StPrePack->StPackData	205	Covered	T2,T4,T66
StReqFlash->StIdle	273	Covered	T2,T3,T4
StReqFlash->StWaitFlash	270	Covered	T2,T3,T4
StScrambleData->StCalcEcc	252	Covered	T3,T5,T11
StWaitFlash->StIdle	280	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T66
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T66
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T12,T13
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T66
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T2,T4,T66
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T6,T12,T13
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T3,T5,T11
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T2,T4,T66
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T3,T5,T11
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T3,T5,T11
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T3,T5,T11
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T3,T5,T11
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T11
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T2,T3,T4
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T2,T3,T4
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T2,T3,T4
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T2,T3,T4
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T3,T4
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T4
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T6,T16

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T2,T3,T4
0	0	1	-	-	Covered	T3,T5,T11
0	0	0	1	-	Covered	T3,T5,T11
0	0	0	0	1	Covered	T2,T3,T4
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	385513645	1233263	0	0
PostPackRule_A	385513645	928	0	0
PrePackRule_A	385513645	670	0	0
WidthCheck_A	1042	1042	0	0
u_state_regs_A	385513645	384669815	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	1233263	0	0
T2	29123	21	0	0
T3	411572	371	0	0
T4	7542	2	0	0
T5	0	150	0	0
T9	3431	0	0	0
T11	0	33152	0	0
T17	1402	0	0	0
T18	3298	0	0	0
T19	2243	0	0	0
T20	1477	0	0	0
T21	1721	0	0	0
T42	0	3	0	0
T43	0	1	0	0
T47	0	145	0	0
T63	1544	0	0	0
T65	0	1	0	0
T66	0	22	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	928	0	0
T2	29123	14	0	0
T3	411572	0	0	0
T4	7542	2	0	0
T9	3431	0	0	0
T17	1402	0	0	0
T18	3298	0	0	0
T19	2243	0	0	0
T20	1477	0	0	0
T21	1721	0	0	0
T42	0	2	0	0
T43	0	1	0	0
T49	0	1	0	0
T63	1544	0	0	0
T66	0	12	0	0
T143	0	1	0	0
T232	0	2	0	0
T233	0	21	0	0
T234	0	2	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	670	0	0
T2	29123	8	0	0
T3	411572	0	0	0
T4	7542	1	0	0
T9	3431	0	0	0
T17	1402	0	0	0
T18	3298	0	0	0
T19	2243	0	0	0
T20	1477	0	0	0
T21	1721	0	0	0
T35	0	3	0	0
T42	0	2	0	0
T63	1544	0	0	0
T66	0	11	0	0
T73	0	2	0	0
T74	0	2	0	0
T90	0	13	0	0
T143	0	2	0	0
T233	0	18	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	384669815	0	0
T1	122714	122698	0	0
T2	29123	29053	0	0
T3	411572	393021	0	0
T4	7542	7484	0	0
T9	3431	2811	0	0
T17	1402	1254	0	0
T18	3298	3201	0	0
T19	2243	2177	0	0
T20	1477	1423	0	0
T21	1721	1666	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	63	96.92
Logical	65	63	96.92
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T4

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T4

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T235,T236
1	0	Covered	T7,T235,T236

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T17,T4
1	1	Covered	T7,T235,T236

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T235,T236
1	0	Covered	T1,T2,T19

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T4

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T2,T17,T4
1	Covered	T2,T4,T66

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T17,T4
1	0	Covered	T2,T17,T4
1	1	Covered	T2,T17,T4

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T17,T4

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T17,T4
1	1	Covered	T2,T4,T66

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T12,T13
1	Covered	T2,T4,T66

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T17,T4
1	0	Covered	T2,T17,T4
1	1	Covered	T2,T17,T4

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T2,T17,T4
1	Covered	T2,T17,T4

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T17,T4
1	0	Covered	T2,T17,T4
1	1	Covered	T2,T4,T66

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T6,T12,T13
1	Covered	T2,T4,T66

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T2,T4,T66
1	Covered	T17,T5,T25

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T2,T4,T66
1	Covered	T2,T4,T66

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T2,T4,T66
1	Covered	T2,T4,T66

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T66
1	1	Covered	T2,T4,T66

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T25,T11
1	0	Covered	T17,T5,T25
1	1	Covered	T17,T5,T25

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T25,T11
1	0	Covered	T17,T5,T25
1	1	Covered	T17,T5,T25

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T17,T4
1	1	0	Covered	T2,T17,T4
1	1	1	Covered	T2,T4,T66

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T66

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T19,T4

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T17,T5,T25
StCalcMask	237	Covered	T17,T5,T25
StCalcPlainEcc	215	Covered	T2,T17,T4
StDisabled	193	Covered	T9,T10,T11
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T2,T17,T4
StPostPack	218	Covered	T2,T4,T66
StPrePack	195	Covered	T2,T4,T66
StReqFlash	237	Covered	T2,T4,T66
StScrambleData	244	Covered	T17,T5,T25
StWaitFlash	270	Covered	T2,T4,T66

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T5,T25,T26
StCalcMask->StScrambleData	244	Covered	T17,T5,T25
StCalcPlainEcc->StCalcMask	237	Covered	T17,T5,T25
StCalcPlainEcc->StReqFlash	237	Covered	T2,T4,T66
StIdle->StDisabled	193	Covered	T9,T10,T11
StIdle->StPackData	197	Covered	T2,T17,T4
StIdle->StPrePack	195	Covered	T2,T4,T66
StPackData->StCalcPlainEcc	215	Covered	T2,T17,T4
StPackData->StPostPack	218	Covered	T2,T4,T66
StPostPack->StCalcPlainEcc	231	Covered	T2,T4,T66
StPrePack->StPackData	205	Covered	T2,T4,T66
StReqFlash->StIdle	273	Covered	T2,T4,T66
StReqFlash->StWaitFlash	270	Covered	T2,T4,T66
StScrambleData->StCalcEcc	252	Covered	T17,T5,T25
StWaitFlash->StIdle	280	Covered	T2,T4,T66

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T17,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T17,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T4,T66
0	1	Covered	T1,T19,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T17,T4
0	0	1	Covered	T2,T17,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T66
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T17,T4
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T66
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T12,T13
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T17,T4
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T66
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T2,T17,T4
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T2,T17,T4
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T2,T4,T66
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T6,T12,T13
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T17,T5,T25
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T2,T4,T66
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T17,T5,T25
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T17,T5,T25
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T17,T5,T25
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T17,T5,T25
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T5,T25
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T2,T4,T66
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T2,T4,T66
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T2,T4,T66
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T2,T4,T66
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T4,T66
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T4,T66
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T9,T10,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T6,T16

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T2,T4,T66
0	0	1	-	-	Covered	T17,T5,T25
0	0	0	1	-	Covered	T17,T5,T25
0	0	0	0	1	Covered	T2,T17,T4
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T17,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	385513645	1206401	0	0
PostPackRule_A	385513645	950	0	0
PrePackRule_A	385513645	680	0	0
WidthCheck_A	1042	1042	0	0
u_state_regs_A	385513645	384669815	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	1206401	0	0
T2	29123	26	0	0
T3	411572	0	0	0
T4	7542	5	0	0
T5	0	379	0	0
T9	3431	0	0	0
T11	0	32768	0	0
T17	1402	0	0	0
T18	3298	0	0	0
T19	2243	0	0	0
T20	1477	0	0	0
T21	1721	0	0	0
T25	0	1	0	0
T26	0	1	0	0
T42	0	2	0	0
T43	0	3	0	0
T45	0	155	0	0
T63	1544	0	0	0
T66	0	35	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	950	0	0
T2	29123	19	0	0
T3	411572	0	0	0
T4	7542	3	0	0
T9	3431	0	0	0
T17	1402	0	0	0
T18	3298	0	0	0
T19	2243	0	0	0
T20	1477	0	0	0
T21	1721	0	0	0
T35	0	7	0	0
T42	0	1	0	0
T43	0	3	0	0
T49	0	1	0	0
T63	1544	0	0	0
T66	0	20	0	0
T73	0	2	0	0
T74	0	3	0	0
T233	0	25	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	680	0	0
T2	29123	8	0	0
T3	411572	0	0	0
T4	7542	1	0	0
T9	3431	0	0	0
T17	1402	0	0	0
T18	3298	0	0	0
T19	2243	0	0	0
T20	1477	0	0	0
T21	1721	0	0	0
T35	0	4	0	0
T42	0	1	0	0
T43	0	2	0	0
T48	0	1	0	0
T63	1544	0	0	0
T66	0	12	0	0
T73	0	3	0	0
T74	0	5	0	0
T233	0	9	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	385513645	384669815	0	0
T1	122714	122698	0	0
T2	29123	29053	0	0
T3	411572	393021	0	0
T4	7542	7484	0	0
T9	3431	2811	0	0
T17	1402	1254	0	0
T18	3298	3201	0	0
T19	2243	2177	0	0
T20	1477	1423	0	0
T21	1721	1666	0	0