Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 97.92 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block] 95.83 1 100 1 64 64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block] 100.00 1 100 1 64 64



Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
95.83 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 1 15 93.75


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 1 15 93.75 100 1 1 0


Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 18629 1 T105 1014 T68 161 T106 597
full_word 3783330 1 T6 16703 T7 16103 T23 30


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 3801677 1 T6 16703 T7 16103 T23 30
auto[TlIntgErrCmd] 84 1 T107 5 T241 4 T240 5
auto[TlIntgErrData] 104 1 T107 7 T241 4 T240 2
auto[TlIntgErrBoth] 94 1 T107 7 T241 2 T240 3


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3778708 1 T6 16703 T7 16103 T23 30
auto[1] 23251 1 T105 1349 T68 238 T106 831


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 1 15 93.75 1


Automatically Generated Cross Bins for cr_all

Uncovered bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTNUMBER
[auto[TlIntgErrBoth]] [full_word] [auto[0]] 0 1 1


Covered bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 1163 1 T105 32 T68 12 T106 48
auto[TlIntgErrNone] partial auto[1] 17205 1 T105 982 T68 149 T106 549
auto[TlIntgErrNone] full_word auto[0] 3777435 1 T6 16703 T7 16103 T23 30
auto[TlIntgErrNone] full_word auto[1] 5874 1 T105 367 T68 89 T106 282
auto[TlIntgErrCmd] partial auto[0] 20 1 T107 1 T240 3 T343 1
auto[TlIntgErrCmd] partial auto[1] 53 1 T107 3 T241 4 T240 2
auto[TlIntgErrCmd] full_word auto[0] 5 1 T107 1 T265 1 T272 1
auto[TlIntgErrCmd] full_word auto[1] 6 1 T266 2 T272 1 T345 1
auto[TlIntgErrData] partial auto[0] 51 1 T107 3 T241 1 T343 2
auto[TlIntgErrData] partial auto[1] 45 1 T107 4 T241 2 T240 2
auto[TlIntgErrData] full_word auto[0] 4 1 T241 1 T271 1 T272 1
auto[TlIntgErrData] full_word auto[1] 4 1 T341 1 T271 1 T344 1
auto[TlIntgErrBoth] partial auto[0] 30 1 T107 4 T241 2 T240 2
auto[TlIntgErrBoth] partial auto[1] 62 1 T107 3 T240 1 T343 2
auto[TlIntgErrBoth] full_word auto[1] 2 1 T341 1 T265 1 - -


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 25798485 1 T1 3236 T2 151 T3 7680
full_word 7744346 1 T1 5116 T2 76 T3 10228


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 33542531 1 T1 8352 T2 227 T3 17908
auto[TlIntgErrCmd] 96 1 T107 4 T241 5 T240 4
auto[TlIntgErrData] 103 1 T107 5 T241 3 T240 3
auto[TlIntgErrBoth] 101 1 T107 11 T241 2 T240 3


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 29151521 1 T1 2883 T2 58 T3 14787
auto[1] 4391310 1 T1 5469 T2 169 T3 3121


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 25141192 1 T1 2882 T2 57 T3 7537
auto[TlIntgErrNone] partial auto[1] 657018 1 T1 354 T2 94 T3 143
auto[TlIntgErrNone] full_word auto[0] 4010194 1 T1 1 T2 1 T3 7250
auto[TlIntgErrNone] full_word auto[1] 3734127 1 T1 5115 T2 75 T3 2978
auto[TlIntgErrCmd] partial auto[0] 37 1 T107 2 T241 2 T343 2
auto[TlIntgErrCmd] partial auto[1] 51 1 T107 1 T241 3 T240 4
auto[TlIntgErrCmd] full_word auto[0] 5 1 T107 1 T341 1 T266 1
auto[TlIntgErrCmd] full_word auto[1] 3 1 T265 1 T344 1 T346 1
auto[TlIntgErrData] partial auto[0] 46 1 T107 4 T241 3 T240 1
auto[TlIntgErrData] partial auto[1] 49 1 T107 1 T240 1 T343 2
auto[TlIntgErrData] full_word auto[0] 4 1 T342 1 T266 1 T265 1
auto[TlIntgErrData] full_word auto[1] 4 1 T240 1 T343 1 T341 1
auto[TlIntgErrBoth] partial auto[0] 38 1 T107 8 T240 1 T341 2
auto[TlIntgErrBoth] partial auto[1] 54 1 T107 2 T241 2 T240 1
auto[TlIntgErrBoth] full_word auto[0] 5 1 T107 1 T240 1 T266 1
auto[TlIntgErrBoth] full_word auto[1] 4 1 T343 1 T342 1 T265 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%