Group : dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg
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Group : dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 98.41 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_lockable_field_cov.sv

315 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
lockable_field_cov_of_flash_ctrl_core_reg_block.addr.start 50.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.control.erase_sel 50.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.control.info_sel 50.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.control.num 50.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.control.op 50.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.control.partition_sel 50.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.control.prog_sel 50.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.control.start 50.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.normal 50.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.repair 50.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_bank_cfg_shadowed.erase_en_0 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_bank_cfg_shadowed.erase_en_1 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_0.base 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_0.size 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_1.base 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_1.size 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_2.base 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_2.size 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_3.base 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_3.size 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_4.base 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_4.size 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_5.base 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_5.size 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_6.base 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_6.size 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_7.base 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_7.size 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr1.field0 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr1.field1 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr10.field0 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr11.field0 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr12.field0 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr13.field0 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr13.field1 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr14.field0 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr14.field1 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr15.field0 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr15.field1 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr16.field0 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr16.field1 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr17.field0 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr17.field1 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr18.field0 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr19.field0 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field0 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field1 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field2 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field3 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field4 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field5 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field6 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field7 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field8 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field9 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr4.field0 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr4.field1 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr4.field2 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr4.field3 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field0 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field1 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field2 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field3 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field4 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field0 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field1 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field2 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field3 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field4 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field5 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field6 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field7 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field8 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr7.field0 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr7.field1 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr8.field0 100.00 1 100 1 64 64
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr9.field0 100.00 1 100 1 64 64




Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.addr.start
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.addr.start

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.addr.start
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.control.erase_sel
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.erase_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.erase_sel
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.control.info_sel
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.info_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.info_sel
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.control.num
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.num

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.num
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.control.op
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.op

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.op
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.control.partition_sel
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.partition_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.partition_sel
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.control.prog_sel
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.prog_sel

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.prog_sel
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.control.start
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.start

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.control.start
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.normal
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.normal

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.normal
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.repair
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.repair

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.prog_type_en.repair
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 1 1 50.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.ecc_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.ecc_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.ecc_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.erase_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.erase_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.erase_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.he_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.he_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.he_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.prog_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.prog_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.prog_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.rd_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.rd_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.rd_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.scramble_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.scramble_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_0.scramble_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.ecc_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.ecc_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.ecc_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.erase_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.erase_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.erase_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.he_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.he_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.he_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.prog_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.prog_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.prog_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.rd_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.rd_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.rd_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.scramble_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.scramble_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_1.scramble_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.ecc_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.ecc_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.ecc_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.erase_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.erase_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.erase_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.he_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.he_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.he_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.prog_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.prog_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.prog_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.rd_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.rd_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.rd_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.scramble_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.scramble_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_2.scramble_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.ecc_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.ecc_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.ecc_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.erase_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.erase_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.erase_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.he_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.he_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.he_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.prog_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.prog_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.prog_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.rd_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.rd_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.rd_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.scramble_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.scramble_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_3.scramble_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.ecc_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.ecc_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.ecc_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.erase_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.erase_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.erase_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.he_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.he_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.he_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.prog_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.prog_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.prog_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.rd_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.rd_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.rd_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.scramble_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.scramble_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_4.scramble_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.ecc_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.ecc_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.ecc_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.erase_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.erase_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.erase_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.he_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.he_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.he_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.prog_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.prog_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.prog_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.rd_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.rd_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.rd_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.scramble_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.scramble_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_5.scramble_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.ecc_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.ecc_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.ecc_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.erase_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.erase_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.erase_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.he_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.he_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.he_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.prog_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.prog_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.prog_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.rd_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.rd_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.rd_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.scramble_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.scramble_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_6.scramble_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.ecc_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.ecc_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.ecc_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.erase_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.erase_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.erase_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.he_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.he_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.he_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2



Group Instance : lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.prog_en
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.prog_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_7.prog_en
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1188 1 T68 1 T69 2 T107 20


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 939 1 T256 4 T232 8 T117 8


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1050 1 T256 8 T232 8 T117 6


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1060 1 T256 8 T232 8 T117 8


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 806 1 T256 8 T232 7 T117 8


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 703 1 T256 8 T232 8 T117 8


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 729 1 T256 8 T232 8 T117 5


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 35 1 T256 7 T232 7 T117 7


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 776 1 T86 8 T87 4 T88 6


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_regwen

Uncovered bins
NAMECOUNTAT LEASTNUMBER
[auto[0]] 0 1 1


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 888 1 T86 3 T87 4 T88 6


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 339 1 T69 2 T107 2 T248 2
auto[1] 537 1 T68 1 T107 17 T108 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 494 1 T69 2 T107 3 T248 2
auto[1] 656 1 T68 1 T107 16 T108 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 403 1 T69 2 T107 3 T248 2
auto[1] 718 1 T68 1 T107 17 T108 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 306 1 T69 2 T107 3 T248 2
auto[1] 691 1 T68 1 T107 17 T108 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 430 1 T69 2 T107 3 T248 2
auto[1] 719 1 T68 1 T107 17 T108 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 382 1 T69 2 T107 2 T248 2
auto[1] 738 1 T68 1 T107 16 T108 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 371 1 T69 2 T107 3 T248 2
auto[1] 618 1 T68 1 T107 14 T108 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 250 1 T69 2 T107 6 T241 2
auto[1] 717 1 T68 1 T107 13 T248 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 414 1 T69 2 T107 7 T241 2
auto[1] 749 1 T68 1 T107 12 T248 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 312 1 T69 2 T107 6 T241 2
auto[1] 725 1 T68 1 T107 13 T248 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 217 1 T69 2 T107 6 T241 2
auto[1] 706 1 T68 1 T107 12 T248 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 346 1 T69 2 T107 6 T241 2
auto[1] 616 1 T68 1 T107 13 T250 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 377 1 T69 2 T107 6 T241 2
auto[1] 740 1 T68 1 T107 13 T248 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 281 1 T69 2 T107 7 T241 1
auto[1] 719 1 T68 1 T107 12 T248 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 274 1 T68 1 T107 3 T250 1
auto[1] 528 1 T69 2 T107 16 T248 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 346 1 T68 1 T107 3 T250 1
auto[1] 651 1 T69 2 T107 17 T248 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 309 1 T68 1 T107 3 T241 2
auto[1] 573 1 T69 2 T107 16 T248 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 256 1 T68 1 T107 3 T250 1
auto[1] 497 1 T69 2 T107 16 T248 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 323 1 T68 1 T107 3 T250 1
auto[1] 598 1 T69 2 T107 16 T248 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 332 1 T68 1 T107 3 T241 2
auto[1] 617 1 T69 2 T107 14 T248 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 286 1 T68 1 T107 3 T241 2
auto[1] 542 1 T69 2 T107 17 T248 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 259 1 T69 1 T107 5 T248 1
auto[1] 754 1 T68 1 T69 1 T107 14


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 423 1 T69 1 T107 5 T248 1
auto[1] 792 1 T68 1 T69 1 T107 14


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 327 1 T69 1 T107 5 T248 1
auto[1] 600 1 T68 1 T69 1 T107 15


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 230 1 T107 4 T248 1 T301 1
auto[1] 740 1 T69 2 T107 14 T248 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 354 1 T69 1 T107 3 T248 1
auto[1] 595 1 T68 1 T107 14 T248 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 388 1 T69 1 T107 5 T248 1
auto[1] 782 1 T68 1 T69 1 T107 14


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 293 1 T69 1 T107 5 T248 1
auto[1] 756 1 T68 1 T69 1 T107 14


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 203 1 T68 1 T107 3 T248 1
auto[1] 678 1 T69 2 T107 17 T248 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 281 1 T68 1 T107 3 T248 1
auto[1] 773 1 T69 2 T107 16 T248 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 238 1 T68 1 T107 3 T248 1
auto[1] 635 1 T69 2 T107 17 T248 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 188 1 T68 1 T107 3 T248 1
auto[1] 515 1 T69 2 T107 17 T248 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 256 1 T68 1 T107 3 T248 1
auto[1] 683 1 T69 2 T107 16 T248 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 270 1 T68 1 T107 3 T248 1
auto[1] 766 1 T69 2 T107 14 T248 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 220 1 T68 1 T107 3 T248 1
auto[1] 600 1 T69 2 T107 17 T248 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 313 1 T107 8 T241 2 T236 1
auto[1] 651 1 T68 1 T69 2 T107 12


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 438 1 T107 8 T241 2 T236 1
auto[1] 726 1 T68 1 T69 1 T107 11


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 366 1 T107 8 T241 2 T236 1
auto[1] 682 1 T68 1 T69 2 T107 11


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 194 1 T107 8 T241 2 T236 1
auto[1] 624 1 T68 1 T69 2 T107 9


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 387 1 T107 8 T241 2 T236 1
auto[1] 702 1 T68 1 T69 2 T107 12


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 310 1 T107 7 T241 2 T236 1
auto[1] 717 1 T68 1 T69 2 T107 11


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 339 1 T107 7 T241 2 T236 1
auto[1] 669 1 T68 1 T69 2 T107 11


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 198 1 T68 1 T107 2 T248 1
auto[1] 665 1 T69 2 T107 16 T248 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 317 1 T68 1 T107 4 T248 1
auto[1] 741 1 T69 2 T107 14 T248 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 248 1 T68 1 T107 4 T248 1
auto[1] 700 1 T69 2 T107 15 T248 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 177 1 T68 1 T107 4 T248 1
auto[1] 650 1 T69 2 T107 16 T248 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 264 1 T68 1 T107 3 T108 2
auto[1] 709 1 T69 2 T107 13 T248 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 295 1 T68 1 T107 4 T248 1
auto[1] 731 1 T69 2 T107 13 T248 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 222 1 T68 1 T107 3 T248 1
auto[1] 677 1 T69 2 T107 14 T248 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 360 1 T68 1 T69 1 T107 9
auto[1] 527 1 T69 1 T107 10 T248 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 526 1 T68 1 T69 1 T107 9
auto[1] 571 1 T69 1 T107 9 T248 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 424 1 T68 1 T107 9 T248 1
auto[1] 547 1 T69 2 T107 11 T248 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 294 1 T68 1 T69 1 T107 9
auto[1] 564 1 T69 1 T107 11 T248 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 462 1 T68 1 T69 1 T107 9
auto[1] 556 1 T69 1 T107 11 T248 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%