Group : dv_base_reg_pkg::dv_base_shadowed_field_cov::shadow_field_errs_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : dv_base_reg_pkg::dv_base_shadowed_field_cov::shadow_field_errs_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
50.00 50.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_shadowed_field_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
flash_ctrl_core_reg_block.mp_bank_cfg_shadowed.erase_en_0_shadowed_errs_cov 50.00 1 100 1 64 64
flash_ctrl_core_reg_block.mp_bank_cfg_shadowed.erase_en_1_shadowed_errs_cov 50.00 1 100 1 64 64




Group Instance : flash_ctrl_core_reg_block.mp_bank_cfg_shadowed.erase_en_0_shadowed_errs_cov
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance flash_ctrl_core_reg_block.mp_bank_cfg_shadowed.erase_en_0_shadowed_errs_cov

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance flash_ctrl_core_reg_block.mp_bank_cfg_shadowed.erase_en_0_shadowed_errs_cov
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_storage_err 1 0 1 100.00 100 1 1 0
cp_update_err 1 1 0 0.00 100 1 1 0



Group Instance : flash_ctrl_core_reg_block.mp_bank_cfg_shadowed.erase_en_1_shadowed_errs_cov
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance flash_ctrl_core_reg_block.mp_bank_cfg_shadowed.erase_en_1_shadowed_errs_cov

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 1 1 50.00


Variables for Group Instance flash_ctrl_core_reg_block.mp_bank_cfg_shadowed.erase_en_1_shadowed_errs_cov
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_storage_err 1 0 1 100.00 100 1 1 0
cp_update_err 1 1 0 0.00 100 1 1 0


Summary for Variable cp_storage_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_storage_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
storage_err 14416 1 T1 162 T22 12 T23 8



Summary for Variable cp_update_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for cp_update_err

Uncovered bins
NAMECOUNTAT LEASTNUMBER
update_err 0 1 1


Summary for Variable cp_storage_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_storage_err

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
storage_err 14416 1 T1 162 T22 12 T23 8



Summary for Variable cp_update_err

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 1 0 0.00


User Defined Bins for cp_update_err

Uncovered bins
NAMECOUNTAT LEASTNUMBER
update_err 0 1 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%