Module Definition
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Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.54 100.00 90.17 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 100.00 86.36 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.65 100.00 90.61 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : flash_phy_rd_buf_dep
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS4877100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
ALWAYS7666100.00
ALWAYS9033100.00
CONT_ASSIGN9711100.00
ALWAYS11600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE
54 1 1
55 1 1
MISSING_ELSE
61 1 1
62 1 1
65 1 1
66 1 1
71 1 1
72 1 1
76 1 1
77 1 1
79 1 1
80 1 1
MISSING_ELSE
82 1 1
83 1 1
MISSING_ELSE
90 1 1
91 1 1
92 1 1
97 1 1
116 unreachable
117 unreachable
118 unreachable


Cond Coverage for Module : flash_phy_rd_buf_dep
TotalCoveredPercent
Conditions221986.36
Logical221986.36
Non-Logical00
Event00

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT3,T5,T6

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT3,T5,T6
110Not Covered
111CoveredT3,T5,T6

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------
-1-StatusTests
0CoveredT3,T5,T6
1CoveredT1,T2,T3

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T23,T24
11CoveredT3,T5,T6

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------
-1-StatusTests
0CoveredT3,T5,T6
1CoveredT1,T2,T3

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---
-1--2-StatusTests
01CoveredT7,T23,T24
10CoveredT1,T2,T3
11CoveredT3,T5,T6

Branch Coverage for Module : flash_phy_rd_buf_dep
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 71 2 2 100.00
TERNARY 72 2 2 100.00
IF 51 2 2 100.00
IF 54 2 2 100.00
IF 76 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 ((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T5,T6


LineNo. Expression -1-: 72 ((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T5,T6


LineNo. Expression -1-: 51 if (wr_buf_i[i])

Branches:
-1-StatusTests
1 Covered T3,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 54 if (rd_buf_i[i])

Branches:
-1-StatusTests
1 Covered T3,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 76 if ((!rst_ni)) -2-: 79 if (fin_cnt_incr) -3-: 82 if (fin_cnt_decr)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T3,T5,T6
0 0 - Covered T1,T2,T3
0 - 1 Covered T3,T5,T6
0 - 0 Covered T1,T2,T3


Assert Coverage for Module : flash_phy_rd_buf_dep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferDecrUnderRun_A 763076802 6863062 0 0
BufferDepRsp_A 763076802 761494308 0 0
BufferIncrOverFlow_A 763076802 6863074 0 0
DepBufferRspOrder_A 763076803 16670427 0 0


BufferDecrUnderRun_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 763076802 6863062 0 0
T3 126610 512 0 0
T4 211758 0 0 0
T5 112660 512 0 0
T6 337142 43583 0 0
T7 247988 43927 0 0
T8 49444 19377 0 0
T12 3338 0 0 0
T14 0 83 0 0
T20 1391 0 0 0
T21 218751 0 0 0
T22 159898 449 0 0
T23 17846 48 0 0
T24 0 429 0 0
T25 0 6936 0 0
T28 2232 71 0 0
T39 126012 44061 0 0
T43 2450 0 0 0
T47 0 864 0 0
T61 1287 0 0 0

BufferDepRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 763076802 761494308 0 0
T1 154532 154398 0 0
T2 13730 13564 0 0
T3 253220 253048 0 0
T4 423516 423320 0 0
T5 225320 225188 0 0
T6 337142 336790 0 0
T7 247988 247966 0 0
T20 2782 2628 0 0
T21 437502 437484 0 0
T22 159898 159724 0 0

BufferIncrOverFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 763076802 6863074 0 0
T3 126610 512 0 0
T4 211758 0 0 0
T5 112660 512 0 0
T6 337142 43583 0 0
T7 247988 43927 0 0
T8 49444 19377 0 0
T12 3338 0 0 0
T14 0 83 0 0
T20 1391 0 0 0
T21 218751 0 0 0
T22 159898 449 0 0
T23 17846 48 0 0
T24 0 429 0 0
T25 0 6937 0 0
T28 2232 71 0 0
T39 126012 44061 0 0
T43 2450 0 0 0
T47 0 864 0 0
T61 1287 0 0 0

DepBufferRspOrder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 763076803 16670427 0 0
T1 77266 32 0 0
T2 6865 32 0 0
T3 126610 544 0 0
T4 211758 32 0 0
T5 112660 544 0 0
T6 337142 43647 0 0
T7 247988 43961 0 0
T8 49444 9771 0 0
T12 3338 0 0 0
T14 0 131155 0 0
T20 1391 32 0 0
T21 218751 32 0 0
T22 159898 481 0 0
T23 8923 4 0 0
T24 0 429 0 0
T25 0 6936 0 0
T28 2232 6 0 0
T39 126012 19395 0 0
T43 1225 0 0 0
T61 1287 0 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS4877100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
ALWAYS7666100.00
ALWAYS9033100.00
CONT_ASSIGN9711100.00
ALWAYS11600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE
54 1 1
55 1 1
MISSING_ELSE
61 1 1
62 1 1
65 1 1
66 1 1
71 1 1
72 1 1
76 1 1
77 1 1
79 1 1
80 1 1
MISSING_ELSE
82 1 1
83 1 1
MISSING_ELSE
90 1 1
91 1 1
92 1 1
97 1 1
116 unreachable
117 unreachable
118 unreachable


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
TotalCoveredPercent
Conditions221986.36
Logical221986.36
Non-Logical00
Event00

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110Not Covered
111CoveredT3,T5,T6

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT3,T5,T6
110Not Covered
111CoveredT3,T5,T6

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------
-1-StatusTests
0CoveredT3,T5,T6
1CoveredT1,T2,T3

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T23,T24
11CoveredT3,T5,T6

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------
-1-StatusTests
0CoveredT3,T5,T6
1CoveredT1,T2,T3

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---
-1--2-StatusTests
01CoveredT7,T23,T24
10CoveredT1,T2,T3
11CoveredT3,T5,T6

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 71 2 2 100.00
TERNARY 72 2 2 100.00
IF 51 2 2 100.00
IF 54 2 2 100.00
IF 76 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 ((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T5,T6


LineNo. Expression -1-: 72 ((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T5,T6


LineNo. Expression -1-: 51 if (wr_buf_i[i])

Branches:
-1-StatusTests
1 Covered T3,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 54 if (rd_buf_i[i])

Branches:
-1-StatusTests
1 Covered T3,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 76 if ((!rst_ni)) -2-: 79 if (fin_cnt_incr) -3-: 82 if (fin_cnt_decr)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T3,T5,T6
0 0 - Covered T1,T2,T3
0 - 1 Covered T3,T5,T6
0 - 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferDecrUnderRun_A 381538401 4028978 0 0
BufferDepRsp_A 381538401 380747154 0 0
BufferIncrOverFlow_A 381538401 4028982 0 0
DepBufferRspOrder_A 381538401 9308523 0 0


BufferDecrUnderRun_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 381538401 4028978 0 0
T3 126610 512 0 0
T4 211758 0 0 0
T5 112660 512 0 0
T6 168571 22938 0 0
T7 123994 23664 0 0
T8 0 9606 0 0
T20 1391 0 0 0
T21 218751 0 0 0
T22 79949 232 0 0
T23 8923 44 0 0
T28 0 65 0 0
T39 0 24666 0 0
T43 1225 0 0 0
T47 0 864 0 0

BufferDepRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 381538401 380747154 0 0
T1 77266 77199 0 0
T2 6865 6782 0 0
T3 126610 126524 0 0
T4 211758 211660 0 0
T5 112660 112594 0 0
T6 168571 168395 0 0
T7 123994 123983 0 0
T20 1391 1314 0 0
T21 218751 218742 0 0
T22 79949 79862 0 0

BufferIncrOverFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 381538401 4028982 0 0
T3 126610 512 0 0
T4 211758 0 0 0
T5 112660 512 0 0
T6 168571 22938 0 0
T7 123994 23664 0 0
T8 0 9606 0 0
T20 1391 0 0 0
T21 218751 0 0 0
T22 79949 232 0 0
T23 8923 44 0 0
T28 0 65 0 0
T39 0 24666 0 0
T43 1225 0 0 0
T47 0 864 0 0

DepBufferRspOrder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 381538401 9308523 0 0
T1 77266 32 0 0
T2 6865 32 0 0
T3 126610 544 0 0
T4 211758 32 0 0
T5 112660 544 0 0
T6 168571 23002 0 0
T7 123994 23698 0 0
T20 1391 32 0 0
T21 218751 32 0 0
T22 79949 264 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS4877100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6511100.00
CONT_ASSIGN6611100.00
CONT_ASSIGN7111100.00
CONT_ASSIGN7211100.00
ALWAYS7666100.00
ALWAYS9033100.00
CONT_ASSIGN9711100.00
ALWAYS11600
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE
54 1 1
55 1 1
MISSING_ELSE
61 1 1
62 1 1
65 1 1
66 1 1
71 1 1
72 1 1
76 1 1
77 1 1
79 1 1
80 1 1
MISSING_ELSE
82 1 1
83 1 1
MISSING_ELSE
90 1 1
91 1 1
92 1 1
97 1 1
116 unreachable
117 unreachable
118 unreachable


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
TotalCoveredPercent
Conditions221986.36
Logical221986.36
Non-Logical00
Event00

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT14,T16,T72
101CoveredT1,T2,T3
110Not Covered
111CoveredT6,T7,T22

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT6,T7,T22
110Not Covered
111CoveredT6,T7,T22

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------
-1-StatusTests
0CoveredT6,T7,T22
1CoveredT1,T2,T3

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT24,T45,T156
11CoveredT6,T7,T22

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------
-1-StatusTests
0CoveredT6,T7,T22
1CoveredT1,T2,T3

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---
-1--2-StatusTests
01CoveredT24,T45,T156
10CoveredT1,T2,T3
11CoveredT6,T7,T22

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 71 2 2 100.00
TERNARY 72 2 2 100.00
IF 51 2 2 100.00
IF 54 2 2 100.00
IF 76 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 ((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T6,T7,T22


LineNo. Expression -1-: 72 ((incr_buf_sel == decr_buf_sel)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T6,T7,T22


LineNo. Expression -1-: 51 if (wr_buf_i[i])

Branches:
-1-StatusTests
1 Covered T6,T7,T22
0 Covered T1,T2,T3


LineNo. Expression -1-: 54 if (rd_buf_i[i])

Branches:
-1-StatusTests
1 Covered T6,T7,T22
0 Covered T1,T2,T3


LineNo. Expression -1-: 76 if ((!rst_ni)) -2-: 79 if (fin_cnt_incr) -3-: 82 if (fin_cnt_decr)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T6,T7,T22
0 0 - Covered T1,T2,T3
0 - 1 Covered T6,T7,T22
0 - 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferDecrUnderRun_A 381538401 2834084 0 0
BufferDepRsp_A 381538401 380747154 0 0
BufferIncrOverFlow_A 381538401 2834092 0 0
DepBufferRspOrder_A 381538402 7361904 0 0


BufferDecrUnderRun_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 381538401 2834084 0 0
T6 168571 20645 0 0
T7 123994 20263 0 0
T8 49444 9771 0 0
T12 3338 0 0 0
T14 0 83 0 0
T22 79949 217 0 0
T23 8923 4 0 0
T24 0 429 0 0
T25 0 6936 0 0
T28 2232 6 0 0
T39 126012 19395 0 0
T43 1225 0 0 0
T61 1287 0 0 0

BufferDepRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 381538401 380747154 0 0
T1 77266 77199 0 0
T2 6865 6782 0 0
T3 126610 126524 0 0
T4 211758 211660 0 0
T5 112660 112594 0 0
T6 168571 168395 0 0
T7 123994 123983 0 0
T20 1391 1314 0 0
T21 218751 218742 0 0
T22 79949 79862 0 0

BufferIncrOverFlow_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 381538401 2834092 0 0
T6 168571 20645 0 0
T7 123994 20263 0 0
T8 49444 9771 0 0
T12 3338 0 0 0
T14 0 83 0 0
T22 79949 217 0 0
T23 8923 4 0 0
T24 0 429 0 0
T25 0 6937 0 0
T28 2232 6 0 0
T39 126012 19395 0 0
T43 1225 0 0 0
T61 1287 0 0 0

DepBufferRspOrder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 381538402 7361904 0 0
T6 168571 20645 0 0
T7 123994 20263 0 0
T8 49444 9771 0 0
T12 3338 0 0 0
T14 0 131155 0 0
T22 79949 217 0 0
T23 8923 4 0 0
T24 0 429 0 0
T25 0 6936 0 0
T28 2232 6 0 0
T39 126012 19395 0 0
T43 1225 0 0 0
T61 1287 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%