Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T23

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T6,T7,T23
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T6,T7,T23
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T7,T23

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T23
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T7,T23

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T7,T23

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1526153604	1522988616	0	0
CheckNGreaterZero_A	4160	4160	0	0
GntImpliesReady_A	1526153604	410703584	0	0
GntImpliesValid_A	1526153604	410703584	0	0
GrantKnown_A	1526153604	1522988616	0	0
IdxKnown_A	1526153604	1522988616	0	0
IndexIsCorrect_A	1526153604	410703584	0	0
NoReadyValidNoGrant_A	1526153604	179509320	0	0
Priority_A	1526153604	434647674	0	0
ReadyAndValidImplyGrant_A	1526153604	410703584	0	0
ReqAndReadyImplyGrant_A	1526153604	410703584	0	0
ReqImpliesValid_A	1526153604	434647674	0	0
ValidKnown_A	1526153604	1522988616	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1526153604	1522988616	0	0
T1	309064	308796	0	0
T2	27460	27128	0	0
T3	506440	506096	0	0
T4	847032	846640	0	0
T5	450640	450376	0	0
T6	674284	673580	0	0
T7	495976	495932	0	0
T20	5564	5256	0	0
T21	875004	874968	0	0
T22	319796	319448	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4160	4160	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T20	4	4	0	0
T21	4	4	0	0
T22	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1526153604	410703584	0	0
T1	309064	30694	0	0
T2	27460	64	0	0
T3	506440	1608	0	0
T4	847032	376466	0	0
T5	450640	29140	0	0
T6	674284	87294	0	0
T7	495976	87922	0	0
T8	0	19542	0	0
T20	5564	64	0	0
T21	875004	1956792	0	0
T22	319796	153136	0	0
T23	0	2004	0	0
T28	0	12	0	0
T39	0	38790	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1526153604	410703584	0	0
T1	309064	30694	0	0
T2	27460	64	0	0
T3	506440	1608	0	0
T4	847032	376466	0	0
T5	450640	29140	0	0
T6	674284	87294	0	0
T7	495976	87922	0	0
T8	0	19542	0	0
T20	5564	64	0	0
T21	875004	1956792	0	0
T22	319796	153136	0	0
T23	0	2004	0	0
T28	0	12	0	0
T39	0	38790	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1526153604	1522988616	0	0
T1	309064	308796	0	0
T2	27460	27128	0	0
T3	506440	506096	0	0
T4	847032	846640	0	0
T5	450640	450376	0	0
T6	674284	673580	0	0
T7	495976	495932	0	0
T20	5564	5256	0	0
T21	875004	874968	0	0
T22	319796	319448	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1526153604	1522988616	0	0
T1	309064	308796	0	0
T2	27460	27128	0	0
T3	506440	506096	0	0
T4	847032	846640	0	0
T5	450640	450376	0	0
T6	674284	673580	0	0
T7	495976	495932	0	0
T20	5564	5256	0	0
T21	875004	874968	0	0
T22	319796	319448	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1526153604	410703584	0	0
T1	309064	30694	0	0
T2	27460	64	0	0
T3	506440	1608	0	0
T4	847032	376466	0	0
T5	450640	29140	0	0
T6	674284	87294	0	0
T7	495976	87922	0	0
T8	0	19542	0	0
T20	5564	64	0	0
T21	875004	1956792	0	0
T22	319796	153136	0	0
T23	0	2004	0	0
T28	0	12	0	0
T39	0	38790	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1526153604	179509320	0	0
T1	154532	256	0	0
T2	13730	256	0	0
T3	253220	2816	0	0
T4	423516	256	0	0
T5	225320	2688	0	0
T6	674284	238466	0	0
T7	495976	2604252	0	0
T8	98888	25180	0	0
T12	6676	0	0	0
T14	0	1048830	0	0
T20	2782	256	0	0
T21	437502	3392	0	0
T22	319796	1654	0	0
T23	17846	14	0	0
T24	0	1294	0	0
T25	0	41666	0	0
T28	4464	22	0	0
T39	252024	1187478	0	0
T43	2450	0	0	0
T61	2574	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1526153604	434647674	0	0
T1	309064	30694	0	0
T2	27460	64	0	0
T3	506440	1608	0	0
T4	847032	376466	0	0
T5	450640	29140	0	0
T6	674284	91046	0	0
T7	495976	631196	0	0
T8	0	25468	0	0
T20	5564	64	0	0
T21	875004	1956792	0	0
T22	319796	153136	0	0
T23	0	2004	0	0
T28	0	12	0	0
T39	0	296098	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1526153604	410703584	0	0
T1	309064	30694	0	0
T2	27460	64	0	0
T3	506440	1608	0	0
T4	847032	376466	0	0
T5	450640	29140	0	0
T6	674284	87294	0	0
T7	495976	87922	0	0
T8	0	19542	0	0
T20	5564	64	0	0
T21	875004	1956792	0	0
T22	319796	153136	0	0
T23	0	2004	0	0
T28	0	12	0	0
T39	0	38790	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1526153604	410703584	0	0
T1	309064	30694	0	0
T2	27460	64	0	0
T3	506440	1608	0	0
T4	847032	376466	0	0
T5	450640	29140	0	0
T6	674284	87294	0	0
T7	495976	87922	0	0
T8	0	19542	0	0
T20	5564	64	0	0
T21	875004	1956792	0	0
T22	319796	153136	0	0
T23	0	2004	0	0
T28	0	12	0	0
T39	0	38790	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1526153604	434647674	0	0
T1	309064	30694	0	0
T2	27460	64	0	0
T3	506440	1608	0	0
T4	847032	376466	0	0
T5	450640	29140	0	0
T6	674284	91046	0	0
T7	495976	631196	0	0
T8	0	25468	0	0
T20	5564	64	0	0
T21	875004	1956792	0	0
T22	319796	153136	0	0
T23	0	2004	0	0
T28	0	12	0	0
T39	0	296098	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1526153604	1522988616	0	0
T1	309064	308796	0	0
T2	27460	27128	0	0
T3	506440	506096	0	0
T4	847032	846640	0	0
T5	450640	450376	0	0
T6	674284	673580	0	0
T7	495976	495932	0	0
T20	5564	5256	0	0
T21	875004	874968	0	0
T22	319796	319448	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T23

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T6,T7,T23
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T6,T7,T23
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T7,T23

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T23
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T7,T23

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T7,T23

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	381538401	380747154	0	0
CheckNGreaterZero_A	1040	1040	0	0
GntImpliesReady_A	381538401	114198213	0	0
GntImpliesValid_A	381538401	114198213	0	0
GrantKnown_A	381538401	380747154	0	0
IdxKnown_A	381538401	380747154	0	0
IndexIsCorrect_A	381538401	114198213	0	0
NoReadyValidNoGrant_A	381538401	47188996	0	0
Priority_A	381538401	120228634	0	0
ReadyAndValidImplyGrant_A	381538401	114198213	0	0
ReqAndReadyImplyGrant_A	381538401	114198213	0	0
ReqImpliesValid_A	381538401	120228634	0	0
ValidKnown_A	381538401	380747154	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	380747154	0	0
T1	77266	77199	0	0
T2	6865	6782	0	0
T3	126610	126524	0	0
T4	211758	211660	0	0
T5	112660	112594	0	0
T6	168571	168395	0	0
T7	123994	123983	0	0
T20	1391	1314	0	0
T21	218751	218742	0	0
T22	79949	79862	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1040	1040	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	114198213	0	0
T1	77266	9363	0	0
T2	6865	32	0	0
T3	126610	804	0	0
T4	211758	108553	0	0
T5	112660	14570	0	0
T6	168571	23002	0	0
T7	123994	23698	0	0
T20	1391	32	0	0
T21	218751	131095	0	0
T22	79949	4284	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	114198213	0	0
T1	77266	9363	0	0
T2	6865	32	0	0
T3	126610	804	0	0
T4	211758	108553	0	0
T5	112660	14570	0	0
T6	168571	23002	0	0
T7	123994	23698	0	0
T20	1391	32	0	0
T21	218751	131095	0	0
T22	79949	4284	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	380747154	0	0
T1	77266	77199	0	0
T2	6865	6782	0	0
T3	126610	126524	0	0
T4	211758	211660	0	0
T5	112660	112594	0	0
T6	168571	168395	0	0
T7	123994	123983	0	0
T20	1391	1314	0	0
T21	218751	218742	0	0
T22	79949	79862	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	380747154	0	0
T1	77266	77199	0	0
T2	6865	6782	0	0
T3	126610	126524	0	0
T4	211758	211660	0	0
T5	112660	112594	0	0
T6	168571	168395	0	0
T7	123994	123983	0	0
T20	1391	1314	0	0
T21	218751	218742	0	0
T22	79949	79862	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	114198213	0	0
T1	77266	9363	0	0
T2	6865	32	0	0
T3	126610	804	0	0
T4	211758	108553	0	0
T5	112660	14570	0	0
T6	168571	23002	0	0
T7	123994	23698	0	0
T20	1391	32	0	0
T21	218751	131095	0	0
T22	79949	4284	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	47188996	0	0
T1	77266	128	0	0
T2	6865	128	0	0
T3	126610	1408	0	0
T4	211758	128	0	0
T5	112660	1344	0	0
T6	168571	62804	0	0
T7	123994	690632	0	0
T20	1391	128	0	0
T21	218751	1696	0	0
T22	79949	489	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	120228634	0	0
T1	77266	9363	0	0
T2	6865	32	0	0
T3	126610	804	0	0
T4	211758	108553	0	0
T5	112660	14570	0	0
T6	168571	23741	0	0
T7	123994	160997	0	0
T20	1391	32	0	0
T21	218751	131095	0	0
T22	79949	4284	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	114198213	0	0
T1	77266	9363	0	0
T2	6865	32	0	0
T3	126610	804	0	0
T4	211758	108553	0	0
T5	112660	14570	0	0
T6	168571	23002	0	0
T7	123994	23698	0	0
T20	1391	32	0	0
T21	218751	131095	0	0
T22	79949	4284	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	114198213	0	0
T1	77266	9363	0	0
T2	6865	32	0	0
T3	126610	804	0	0
T4	211758	108553	0	0
T5	112660	14570	0	0
T6	168571	23002	0	0
T7	123994	23698	0	0
T20	1391	32	0	0
T21	218751	131095	0	0
T22	79949	4284	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	120228634	0	0
T1	77266	9363	0	0
T2	6865	32	0	0
T3	126610	804	0	0
T4	211758	108553	0	0
T5	112660	14570	0	0
T6	168571	23741	0	0
T7	123994	160997	0	0
T20	1391	32	0	0
T21	218751	131095	0	0
T22	79949	4284	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	380747154	0	0
T1	77266	77199	0	0
T2	6865	6782	0	0
T3	126610	126524	0	0
T4	211758	211660	0	0
T5	112660	112594	0	0
T6	168571	168395	0	0
T7	123994	123983	0	0
T20	1391	1314	0	0
T21	218751	218742	0	0
T22	79949	79862	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T23

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T6,T7,T23
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T6,T7,T23
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T7,T23

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T23
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T7,T23

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T7,T23

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	381538401	380747154	0	0
CheckNGreaterZero_A	1040	1040	0	0
GntImpliesReady_A	381538401	114198129	0	0
GntImpliesValid_A	381538401	114198129	0	0
GrantKnown_A	381538401	380747154	0	0
IdxKnown_A	381538401	380747154	0	0
IndexIsCorrect_A	381538401	114198129	0	0
NoReadyValidNoGrant_A	381538401	47188996	0	0
Priority_A	381538401	120228550	0	0
ReadyAndValidImplyGrant_A	381538401	114198129	0	0
ReqAndReadyImplyGrant_A	381538401	114198129	0	0
ReqImpliesValid_A	381538401	120228550	0	0
ValidKnown_A	381538401	380747154	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	380747154	0	0
T1	77266	77199	0	0
T2	6865	6782	0	0
T3	126610	126524	0	0
T4	211758	211660	0	0
T5	112660	112594	0	0
T6	168571	168395	0	0
T7	123994	123983	0	0
T20	1391	1314	0	0
T21	218751	218742	0	0
T22	79949	79862	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1040	1040	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	114198129	0	0
T1	77266	9363	0	0
T2	6865	32	0	0
T3	126610	804	0	0
T4	211758	108553	0	0
T5	112660	14570	0	0
T6	168571	23002	0	0
T7	123994	23698	0	0
T20	1391	32	0	0
T21	218751	131095	0	0
T22	79949	4284	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	114198129	0	0
T1	77266	9363	0	0
T2	6865	32	0	0
T3	126610	804	0	0
T4	211758	108553	0	0
T5	112660	14570	0	0
T6	168571	23002	0	0
T7	123994	23698	0	0
T20	1391	32	0	0
T21	218751	131095	0	0
T22	79949	4284	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	380747154	0	0
T1	77266	77199	0	0
T2	6865	6782	0	0
T3	126610	126524	0	0
T4	211758	211660	0	0
T5	112660	112594	0	0
T6	168571	168395	0	0
T7	123994	123983	0	0
T20	1391	1314	0	0
T21	218751	218742	0	0
T22	79949	79862	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	380747154	0	0
T1	77266	77199	0	0
T2	6865	6782	0	0
T3	126610	126524	0	0
T4	211758	211660	0	0
T5	112660	112594	0	0
T6	168571	168395	0	0
T7	123994	123983	0	0
T20	1391	1314	0	0
T21	218751	218742	0	0
T22	79949	79862	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	114198129	0	0
T1	77266	9363	0	0
T2	6865	32	0	0
T3	126610	804	0	0
T4	211758	108553	0	0
T5	112660	14570	0	0
T6	168571	23002	0	0
T7	123994	23698	0	0
T20	1391	32	0	0
T21	218751	131095	0	0
T22	79949	4284	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	47188996	0	0
T1	77266	128	0	0
T2	6865	128	0	0
T3	126610	1408	0	0
T4	211758	128	0	0
T5	112660	1344	0	0
T6	168571	62804	0	0
T7	123994	690632	0	0
T20	1391	128	0	0
T21	218751	1696	0	0
T22	79949	489	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	120228550	0	0
T1	77266	9363	0	0
T2	6865	32	0	0
T3	126610	804	0	0
T4	211758	108553	0	0
T5	112660	14570	0	0
T6	168571	23741	0	0
T7	123994	160997	0	0
T20	1391	32	0	0
T21	218751	131095	0	0
T22	79949	4284	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	114198129	0	0
T1	77266	9363	0	0
T2	6865	32	0	0
T3	126610	804	0	0
T4	211758	108553	0	0
T5	112660	14570	0	0
T6	168571	23002	0	0
T7	123994	23698	0	0
T20	1391	32	0	0
T21	218751	131095	0	0
T22	79949	4284	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	114198129	0	0
T1	77266	9363	0	0
T2	6865	32	0	0
T3	126610	804	0	0
T4	211758	108553	0	0
T5	112660	14570	0	0
T6	168571	23002	0	0
T7	123994	23698	0	0
T20	1391	32	0	0
T21	218751	131095	0	0
T22	79949	4284	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	120228550	0	0
T1	77266	9363	0	0
T2	6865	32	0	0
T3	126610	804	0	0
T4	211758	108553	0	0
T5	112660	14570	0	0
T6	168571	23741	0	0
T7	123994	160997	0	0
T20	1391	32	0	0
T21	218751	131095	0	0
T22	79949	4284	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	380747154	0	0
T1	77266	77199	0	0
T2	6865	6782	0	0
T3	126610	126524	0	0
T4	211758	211660	0	0
T5	112660	112594	0	0
T6	168571	168395	0	0
T7	123994	123983	0	0
T20	1391	1314	0	0
T21	218751	218742	0	0
T22	79949	79862	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T21
1	0	Covered	T6,T7,T28

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T6,T7,T28
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T6,T7,T28
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T4,T21
1	1	Covered	T6,T7,T28

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T28
1	1	Covered	T1,T4,T21

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T1,T4,T21

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T7,T28

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T7,T28

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	381538401	380747154	0	0
CheckNGreaterZero_A	1040	1040	0	0
GntImpliesReady_A	381538401	91153621	0	0
GntImpliesValid_A	381538401	91153621	0	0
GrantKnown_A	381538401	380747154	0	0
IdxKnown_A	381538401	380747154	0	0
IndexIsCorrect_A	381538401	91153621	0	0
NoReadyValidNoGrant_A	381538401	42565664	0	0
Priority_A	381538401	97095245	0	0
ReadyAndValidImplyGrant_A	381538401	91153621	0	0
ReqAndReadyImplyGrant_A	381538401	91153621	0	0
ReqImpliesValid_A	381538401	97095245	0	0
ValidKnown_A	381538401	380747154	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	380747154	0	0
T1	77266	77199	0	0
T2	6865	6782	0	0
T3	126610	126524	0	0
T4	211758	211660	0	0
T5	112660	112594	0	0
T6	168571	168395	0	0
T7	123994	123983	0	0
T20	1391	1314	0	0
T21	218751	218742	0	0
T22	79949	79862	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1040	1040	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	91153621	0	0
T1	77266	5984	0	0
T2	6865	0	0	0
T3	126610	0	0	0
T4	211758	79680	0	0
T5	112660	0	0	0
T6	168571	20645	0	0
T7	123994	20263	0	0
T8	0	9771	0	0
T20	1391	0	0	0
T21	218751	847301	0	0
T22	79949	72284	0	0
T23	0	1002	0	0
T28	0	6	0	0
T39	0	19395	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	91153621	0	0
T1	77266	5984	0	0
T2	6865	0	0	0
T3	126610	0	0	0
T4	211758	79680	0	0
T5	112660	0	0	0
T6	168571	20645	0	0
T7	123994	20263	0	0
T8	0	9771	0	0
T20	1391	0	0	0
T21	218751	847301	0	0
T22	79949	72284	0	0
T23	0	1002	0	0
T28	0	6	0	0
T39	0	19395	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	380747154	0	0
T1	77266	77199	0	0
T2	6865	6782	0	0
T3	126610	126524	0	0
T4	211758	211660	0	0
T5	112660	112594	0	0
T6	168571	168395	0	0
T7	123994	123983	0	0
T20	1391	1314	0	0
T21	218751	218742	0	0
T22	79949	79862	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	380747154	0	0
T1	77266	77199	0	0
T2	6865	6782	0	0
T3	126610	126524	0	0
T4	211758	211660	0	0
T5	112660	112594	0	0
T6	168571	168395	0	0
T7	123994	123983	0	0
T20	1391	1314	0	0
T21	218751	218742	0	0
T22	79949	79862	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	91153621	0	0
T1	77266	5984	0	0
T2	6865	0	0	0
T3	126610	0	0	0
T4	211758	79680	0	0
T5	112660	0	0	0
T6	168571	20645	0	0
T7	123994	20263	0	0
T8	0	9771	0	0
T20	1391	0	0	0
T21	218751	847301	0	0
T22	79949	72284	0	0
T23	0	1002	0	0
T28	0	6	0	0
T39	0	19395	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	42565664	0	0
T6	168571	56429	0	0
T7	123994	611494	0	0
T8	49444	12590	0	0
T12	3338	0	0	0
T14	0	524415	0	0
T22	79949	338	0	0
T23	8923	7	0	0
T24	0	647	0	0
T25	0	20833	0	0
T28	2232	11	0	0
T39	126012	593739	0	0
T43	1225	0	0	0
T61	1287	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	97095245	0	0
T1	77266	5984	0	0
T2	6865	0	0	0
T3	126610	0	0	0
T4	211758	79680	0	0
T5	112660	0	0	0
T6	168571	21782	0	0
T7	123994	154601	0	0
T8	0	12734	0	0
T20	1391	0	0	0
T21	218751	847301	0	0
T22	79949	72284	0	0
T23	0	1002	0	0
T28	0	6	0	0
T39	0	148049	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	91153621	0	0
T1	77266	5984	0	0
T2	6865	0	0	0
T3	126610	0	0	0
T4	211758	79680	0	0
T5	112660	0	0	0
T6	168571	20645	0	0
T7	123994	20263	0	0
T8	0	9771	0	0
T20	1391	0	0	0
T21	218751	847301	0	0
T22	79949	72284	0	0
T23	0	1002	0	0
T28	0	6	0	0
T39	0	19395	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	91153621	0	0
T1	77266	5984	0	0
T2	6865	0	0	0
T3	126610	0	0	0
T4	211758	79680	0	0
T5	112660	0	0	0
T6	168571	20645	0	0
T7	123994	20263	0	0
T8	0	9771	0	0
T20	1391	0	0	0
T21	218751	847301	0	0
T22	79949	72284	0	0
T23	0	1002	0	0
T28	0	6	0	0
T39	0	19395	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	97095245	0	0
T1	77266	5984	0	0
T2	6865	0	0	0
T3	126610	0	0	0
T4	211758	79680	0	0
T5	112660	0	0	0
T6	168571	21782	0	0
T7	123994	154601	0	0
T8	0	12734	0	0
T20	1391	0	0	0
T21	218751	847301	0	0
T22	79949	72284	0	0
T23	0	1002	0	0
T28	0	6	0	0
T39	0	148049	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	380747154	0	0
T1	77266	77199	0	0
T2	6865	6782	0	0
T3	126610	126524	0	0
T4	211758	211660	0	0
T5	112660	112594	0	0
T6	168571	168395	0	0
T7	123994	123983	0	0
T20	1391	1314	0	0
T21	218751	218742	0	0
T22	79949	79862	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T21
1	0	Covered	T6,T7,T28

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T6,T7,T28
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T6,T7,T28
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T8
1	0	Covered	T1,T4,T21
1	1	Covered	T6,T7,T28

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T28
1	1	Covered	T1,T4,T21

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T1,T4,T21

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T7,T28

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T7,T28

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	381538401	380747154	0	0
CheckNGreaterZero_A	1040	1040	0	0
GntImpliesReady_A	381538401	91153621	0	0
GntImpliesValid_A	381538401	91153621	0	0
GrantKnown_A	381538401	380747154	0	0
IdxKnown_A	381538401	380747154	0	0
IndexIsCorrect_A	381538401	91153621	0	0
NoReadyValidNoGrant_A	381538401	42565664	0	0
Priority_A	381538401	97095245	0	0
ReadyAndValidImplyGrant_A	381538401	91153621	0	0
ReqAndReadyImplyGrant_A	381538401	91153621	0	0
ReqImpliesValid_A	381538401	97095245	0	0
ValidKnown_A	381538401	380747154	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	380747154	0	0
T1	77266	77199	0	0
T2	6865	6782	0	0
T3	126610	126524	0	0
T4	211758	211660	0	0
T5	112660	112594	0	0
T6	168571	168395	0	0
T7	123994	123983	0	0
T20	1391	1314	0	0
T21	218751	218742	0	0
T22	79949	79862	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1040	1040	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	91153621	0	0
T1	77266	5984	0	0
T2	6865	0	0	0
T3	126610	0	0	0
T4	211758	79680	0	0
T5	112660	0	0	0
T6	168571	20645	0	0
T7	123994	20263	0	0
T8	0	9771	0	0
T20	1391	0	0	0
T21	218751	847301	0	0
T22	79949	72284	0	0
T23	0	1002	0	0
T28	0	6	0	0
T39	0	19395	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	91153621	0	0
T1	77266	5984	0	0
T2	6865	0	0	0
T3	126610	0	0	0
T4	211758	79680	0	0
T5	112660	0	0	0
T6	168571	20645	0	0
T7	123994	20263	0	0
T8	0	9771	0	0
T20	1391	0	0	0
T21	218751	847301	0	0
T22	79949	72284	0	0
T23	0	1002	0	0
T28	0	6	0	0
T39	0	19395	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	380747154	0	0
T1	77266	77199	0	0
T2	6865	6782	0	0
T3	126610	126524	0	0
T4	211758	211660	0	0
T5	112660	112594	0	0
T6	168571	168395	0	0
T7	123994	123983	0	0
T20	1391	1314	0	0
T21	218751	218742	0	0
T22	79949	79862	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	380747154	0	0
T1	77266	77199	0	0
T2	6865	6782	0	0
T3	126610	126524	0	0
T4	211758	211660	0	0
T5	112660	112594	0	0
T6	168571	168395	0	0
T7	123994	123983	0	0
T20	1391	1314	0	0
T21	218751	218742	0	0
T22	79949	79862	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	91153621	0	0
T1	77266	5984	0	0
T2	6865	0	0	0
T3	126610	0	0	0
T4	211758	79680	0	0
T5	112660	0	0	0
T6	168571	20645	0	0
T7	123994	20263	0	0
T8	0	9771	0	0
T20	1391	0	0	0
T21	218751	847301	0	0
T22	79949	72284	0	0
T23	0	1002	0	0
T28	0	6	0	0
T39	0	19395	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	42565664	0	0
T6	168571	56429	0	0
T7	123994	611494	0	0
T8	49444	12590	0	0
T12	3338	0	0	0
T14	0	524415	0	0
T22	79949	338	0	0
T23	8923	7	0	0
T24	0	647	0	0
T25	0	20833	0	0
T28	2232	11	0	0
T39	126012	593739	0	0
T43	1225	0	0	0
T61	1287	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	97095245	0	0
T1	77266	5984	0	0
T2	6865	0	0	0
T3	126610	0	0	0
T4	211758	79680	0	0
T5	112660	0	0	0
T6	168571	21782	0	0
T7	123994	154601	0	0
T8	0	12734	0	0
T20	1391	0	0	0
T21	218751	847301	0	0
T22	79949	72284	0	0
T23	0	1002	0	0
T28	0	6	0	0
T39	0	148049	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	91153621	0	0
T1	77266	5984	0	0
T2	6865	0	0	0
T3	126610	0	0	0
T4	211758	79680	0	0
T5	112660	0	0	0
T6	168571	20645	0	0
T7	123994	20263	0	0
T8	0	9771	0	0
T20	1391	0	0	0
T21	218751	847301	0	0
T22	79949	72284	0	0
T23	0	1002	0	0
T28	0	6	0	0
T39	0	19395	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	91153621	0	0
T1	77266	5984	0	0
T2	6865	0	0	0
T3	126610	0	0	0
T4	211758	79680	0	0
T5	112660	0	0	0
T6	168571	20645	0	0
T7	123994	20263	0	0
T8	0	9771	0	0
T20	1391	0	0	0
T21	218751	847301	0	0
T22	79949	72284	0	0
T23	0	1002	0	0
T28	0	6	0	0
T39	0	19395	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	97095245	0	0
T1	77266	5984	0	0
T2	6865	0	0	0
T3	126610	0	0	0
T4	211758	79680	0	0
T5	112660	0	0	0
T6	168571	21782	0	0
T7	123994	154601	0	0
T8	0	12734	0	0
T20	1391	0	0	0
T21	218751	847301	0	0
T22	79949	72284	0	0
T23	0	1002	0	0
T28	0	6	0	0
T39	0	148049	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381538401	380747154	0	0
T1	77266	77199	0	0
T2	6865	6782	0	0
T3	126610	126524	0	0
T4	211758	211660	0	0
T5	112660	112594	0	0
T6	168571	168395	0	0
T7	123994	123983	0	0
T20	1391	1314	0	0
T21	218751	218742	0	0
T22	79949	79862	0	0