Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	27841697	1		T1	602		T2	338		T3	21839
full_word	7871152	1		T1	488		T2	123		T3	11997

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	35712529	1		T1	1090		T2	461		T3	33836
auto[TlIntgErrCmd]	122	1		T65	13		T101	8		T218	4
auto[TlIntgErrData]	101	1		T65	6		T101	6		T218	3
auto[TlIntgErrBoth]	97	1		T65	1		T101	6		T218	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31222347	1		T1	637		T2	369		T3	24915
auto[1]	4490502	1		T1	453		T2	92		T3	8921

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	27147962	1		T1	569		T2	320		T3	20703
auto[TlIntgErrNone]	partial	auto[1]	693447	1		T1	33		T2	18		T3	1136
auto[TlIntgErrNone]	full_word	auto[0]	4074244	1		T1	68		T2	49		T3	4212
auto[TlIntgErrNone]	full_word	auto[1]	3796876	1		T1	420		T2	74		T3	7785
auto[TlIntgErrCmd]	partial	auto[0]	34	1		T101	2		T218	2		T227	2
auto[TlIntgErrCmd]	partial	auto[1]	77	1		T65	11		T101	6		T218	2
auto[TlIntgErrCmd]	full_word	auto[0]	10	1		T65	2		T361	2		T363	1
auto[TlIntgErrCmd]	full_word	auto[1]	1	1		T358	1		-	-		-	-
auto[TlIntgErrData]	partial	auto[0]	49	1		T65	1		T101	2		T218	2
auto[TlIntgErrData]	partial	auto[1]	44	1		T65	5		T101	4		T227	1
auto[TlIntgErrData]	full_word	auto[0]	4	1		T363	1		T364	1		T365	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T218	1		T230	1		T358	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1		T101	2		T218	1		T227	2
auto[TlIntgErrBoth]	partial	auto[1]	45	1		T65	1		T101	2		T218	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T101	1		T266	2		T365	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1		T101	1		T218	1		T234	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	20699	1		T65	16		T100	174		T101	19
full_word	3775315	1		T1	121		T2	6		T4	20

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3795719	1		T1	121		T2	6		T4	20
auto[TlIntgErrCmd]	104	1		T65	3		T101	9		T218	5
auto[TlIntgErrData]	102	1		T65	5		T101	3		T218	3
auto[TlIntgErrBoth]	89	1		T65	11		T101	8		T218	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3769478	1		T1	121		T2	6		T4	20
auto[1]	26536	1		T65	11		T100	209		T101	13

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1318	1		T100	16		T216	5		T217	4
auto[TlIntgErrNone]	partial	auto[1]	19116	1		T100	158		T216	65		T217	59
auto[TlIntgErrNone]	full_word	auto[0]	3768039	1		T1	121		T2	6		T4	20
auto[TlIntgErrNone]	full_word	auto[1]	7246	1		T100	51		T216	33		T217	33
auto[TlIntgErrCmd]	partial	auto[0]	28	1		T65	1		T101	3		T218	1
auto[TlIntgErrCmd]	partial	auto[1]	66	1		T65	2		T101	6		T218	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T266	1		T366	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	8	1		T227	1		T234	1		T361	1
auto[TlIntgErrData]	partial	auto[0]	55	1		T65	2		T101	3		T218	1
auto[TlIntgErrData]	partial	auto[1]	36	1		T65	3		T218	1		T230	2
auto[TlIntgErrData]	full_word	auto[0]	4	1		T218	1		T234	2		T362	1
auto[TlIntgErrData]	full_word	auto[1]	7	1		T358	1		T361	2		T363	1
auto[TlIntgErrBoth]	partial	auto[0]	28	1		T65	3		T101	1		T227	1
auto[TlIntgErrBoth]	partial	auto[1]	52	1		T65	5		T101	6		T218	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T65	2		T358	1		T266	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T65	1		T101	1		T364	1