Line Coverage for Module :
flash_phy_scramble
| Line No. | Total | Covered | Percent |
TOTAL | | 38 | 38 | 100.00 |
CONT_ASSIGN | 43 | 1 | 1 | 100.00 |
CONT_ASSIGN | 43 | 1 | 1 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 46 | 1 | 1 | 100.00 |
CONT_ASSIGN | 46 | 1 | 1 | 100.00 |
CONT_ASSIGN | 47 | 1 | 1 | 100.00 |
CONT_ASSIGN | 47 | 1 | 1 | 100.00 |
CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
CONT_ASSIGN | 52 | 1 | 1 | 100.00 |
CONT_ASSIGN | 52 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
CONT_ASSIGN | 57 | 1 | 1 | 100.00 |
CONT_ASSIGN | 57 | 1 | 1 | 100.00 |
CONT_ASSIGN | 58 | 1 | 1 | 100.00 |
CONT_ASSIGN | 58 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 102 | 1 | 1 | 100.00 |
ALWAYS | 118 | 4 | 4 | 100.00 |
CONT_ASSIGN | 125 | 1 | 1 | 100.00 |
CONT_ASSIGN | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 166 | 1 | 1 | 100.00 |
ALWAYS | 173 | 4 | 4 | 100.00 |
ALWAYS | 189 | 3 | 3 | 100.00 |
CONT_ASSIGN | 196 | 1 | 1 | 100.00 |
CONT_ASSIGN | 197 | 1 | 1 | 100.00 |
CONT_ASSIGN | 232 | 1 | 1 | 100.00 |
CONT_ASSIGN | 235 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
43 |
2 |
2 |
44 |
2 |
2 |
46 |
2 |
2 |
47 |
2 |
2 |
51 |
2 |
2 |
52 |
2 |
2 |
56 |
2 |
2 |
57 |
2 |
2 |
58 |
2 |
2 |
100 |
1 |
1 |
102 |
1 |
1 |
118 |
1 |
1 |
119 |
1 |
1 |
120 |
1 |
1 |
121 |
1 |
1 |
|
|
|
MISSING_ELSE |
125 |
1 |
1 |
128 |
1 |
1 |
166 |
1 |
1 |
173 |
1 |
1 |
174 |
1 |
1 |
175 |
1 |
1 |
176 |
1 |
1 |
|
|
|
MISSING_ELSE |
189 |
1 |
1 |
190 |
1 |
1 |
192 |
1 |
1 |
196 |
1 |
1 |
197 |
1 |
1 |
232 |
1 |
1 |
235 |
1 |
1 |
Cond Coverage for Module :
flash_phy_scramble
| Total | Covered | Percent |
Conditions | 29 | 25 | 86.21 |
Logical | 29 | 25 | 86.21 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 120
EXPRESSION (((!calc_req)) || (calc_req && calc_ack))
------1------ -----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 120
SUB-EXPRESSION (calc_req && calc_ack)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Unreachable | T1,T2,T3 |
LINE 125
EXPRESSION (addr_key_sel ? rand_addr_key_i : addr_key_i)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T10,T11,T12 |
LINE 166
EXPRESSION (op_type == DeScrambleOp)
------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 175
EXPRESSION (((!op_req)) || (op_req && op_ack))
-----1----- ---------2--------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 175
SUB-EXPRESSION (op_req && op_ack)
---1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 196
EXPRESSION (op_ack ? '0 : (op_req & ((!cipher_valid_out))))
---1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 196
SUB-EXPRESSION (op_req & ((!cipher_valid_out)))
---1-- ----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 197
EXPRESSION (cipher_valid_in_q & cipher_valid_out)
--------1-------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
LINE 209
EXPRESSION (dec ? scrambled_data_in : plain_data_in)
-1-
-1- | Status | Tests |
0 | Covered | T2,T3,T17 |
1 | Covered | T1,T2,T3 |
LINE 209
EXPRESSION (data_key_sel ? rand_data_key_i : data_key_i)
------1-----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T10,T11,T12 |
LINE 232
EXPRESSION (dec ? data : scrambled_data_in)
-1-
-1- | Status | Tests |
0 | Covered | T2,T3,T17 |
1 | Covered | T1,T2,T3 |
LINE 235
EXPRESSION (dec ? plain_data_in : data)
-1-
-1- | Status | Tests |
0 | Covered | T2,T3,T17 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
flash_phy_scramble
| Line No. | Total | Covered | Percent |
Branches |
|
20 |
20 |
100.00 |
TERNARY |
125 |
2 |
2 |
100.00 |
TERNARY |
196 |
2 |
2 |
100.00 |
TERNARY |
232 |
2 |
2 |
100.00 |
TERNARY |
235 |
2 |
2 |
100.00 |
TERNARY |
209 |
2 |
2 |
100.00 |
TERNARY |
209 |
2 |
2 |
100.00 |
IF |
118 |
3 |
3 |
100.00 |
IF |
173 |
3 |
3 |
100.00 |
IF |
189 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_scramble.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_scramble.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 125 (addr_key_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T10,T11,T12 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 196 (op_ack) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 232 (dec) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T17 |
LineNo. Expression
-1-: 235 (dec) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T17 |
LineNo. Expression
-1-: 209 (dec) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T2,T3,T17 |
LineNo. Expression
-1-: 209 (data_key_sel) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T10,T11,T12 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 118 if ((!rst_ni))
-2-: 120 if (((!calc_req) || (calc_req && calc_ack)))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 173 if ((!rst_ni))
-2-: 175 if (((!op_req) || (op_req && op_ack)))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 189 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |