Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1584566912	1581119928	0	0
CheckNGreaterZero_A	4172	4172	0	0
GntImpliesReady_A	1584566912	416015972	0	0
GntImpliesValid_A	1584566912	416015972	0	0
GrantKnown_A	1584566912	1581119928	0	0
IdxKnown_A	1584566912	1581119928	0	0
IndexIsCorrect_A	1584566912	416015972	0	0
NoReadyValidNoGrant_A	1584566912	184192451	0	0
Priority_A	1584566912	440165933	0	0
ReadyAndValidImplyGrant_A	1584566912	416015972	0	0
ReqAndReadyImplyGrant_A	1584566912	416015972	0	0
ReqImpliesValid_A	1584566912	440165933	0	0
ValidKnown_A	1584566912	1581119928	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584566912	1581119928	0	0
T1	15768	15516	0	0
T2	6692	6080	0	0
T3	1028072	983236	0	0
T4	20044	18876	0	0
T5	602280	601896	0	0
T10	1579556	1579492	0	0
T17	5616	5068	0	0
T18	5400	5008	0	0
T19	6964	6592	0	0
T20	5052	4844	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4172	4172	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T10	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584566912	416015972	0	0
T1	15768	3034	0	0
T2	6692	354	0	0
T3	1028072	222614	0	0
T4	20044	760	0	0
T5	602280	189596	0	0
T6	0	18	0	0
T10	1579556	544522	0	0
T17	5616	176	0	0
T18	5400	64	0	0
T19	6964	398	0	0
T20	5052	64	0	0
T24	0	2686	0	0
T44	0	420	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584566912	416015972	0	0
T1	15768	3034	0	0
T2	6692	354	0	0
T3	1028072	222614	0	0
T4	20044	760	0	0
T5	602280	189596	0	0
T6	0	18	0	0
T10	1579556	544522	0	0
T17	5616	176	0	0
T18	5400	64	0	0
T19	6964	398	0	0
T20	5052	64	0	0
T24	0	2686	0	0
T44	0	420	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584566912	1581119928	0	0
T1	15768	15516	0	0
T2	6692	6080	0	0
T3	1028072	983236	0	0
T4	20044	18876	0	0
T5	602280	601896	0	0
T10	1579556	1579492	0	0
T17	5616	5068	0	0
T18	5400	5008	0	0
T19	6964	6592	0	0
T20	5052	4844	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584566912	1581119928	0	0
T1	15768	15516	0	0
T2	6692	6080	0	0
T3	1028072	983236	0	0
T4	20044	18876	0	0
T5	602280	601896	0	0
T10	1579556	1579492	0	0
T17	5616	5068	0	0
T18	5400	5008	0	0
T19	6964	6592	0	0
T20	5052	4844	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584566912	416015972	0	0
T1	15768	3034	0	0
T2	6692	354	0	0
T3	1028072	222614	0	0
T4	20044	760	0	0
T5	602280	189596	0	0
T6	0	18	0	0
T10	1579556	544522	0	0
T17	5616	176	0	0
T18	5400	64	0	0
T19	6964	398	0	0
T20	5052	64	0	0
T24	0	2686	0	0
T44	0	420	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584566912	184192451	0	0
T1	15768	762	0	0
T2	6692	762	0	0
T3	1028072	57600	0	0
T4	20044	1158	0	0
T5	602280	114512	0	0
T6	0	20	0	0
T10	1579556	2125312	0	0
T17	5616	512	0	0
T18	5400	256	0	0
T19	6964	290	0	0
T20	5052	256	0	0
T22	0	63920	0	0
T24	0	236	0	0
T38	0	1714	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584566912	440165933	0	0
T1	15768	3038	0	0
T2	6692	354	0	0
T3	1028072	222614	0	0
T4	20044	760	0	0
T5	602280	221982	0	0
T6	0	24	0	0
T10	1579556	544522	0	0
T17	5616	176	0	0
T18	5400	64	0	0
T19	6964	398	0	0
T20	5052	64	0	0
T24	0	2686	0	0
T44	0	420	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584566912	416015972	0	0
T1	15768	3034	0	0
T2	6692	354	0	0
T3	1028072	222614	0	0
T4	20044	760	0	0
T5	602280	189596	0	0
T6	0	18	0	0
T10	1579556	544522	0	0
T17	5616	176	0	0
T18	5400	64	0	0
T19	6964	398	0	0
T20	5052	64	0	0
T24	0	2686	0	0
T44	0	420	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584566912	416015972	0	0
T1	15768	3034	0	0
T2	6692	354	0	0
T3	1028072	222614	0	0
T4	20044	760	0	0
T5	602280	189596	0	0
T6	0	18	0	0
T10	1579556	544522	0	0
T17	5616	176	0	0
T18	5400	64	0	0
T19	6964	398	0	0
T20	5052	64	0	0
T24	0	2686	0	0
T44	0	420	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584566912	440165933	0	0
T1	15768	3038	0	0
T2	6692	354	0	0
T3	1028072	222614	0	0
T4	20044	760	0	0
T5	602280	221982	0	0
T6	0	24	0	0
T10	1579556	544522	0	0
T17	5616	176	0	0
T18	5400	64	0	0
T19	6964	398	0	0
T20	5052	64	0	0
T24	0	2686	0	0
T44	0	420	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1584566912	1581119928	0	0
T1	15768	15516	0	0
T2	6692	6080	0	0
T3	1028072	983236	0	0
T4	20044	18876	0	0
T5	602280	601896	0	0
T10	1579556	1579492	0	0
T17	5616	5068	0	0
T18	5400	5008	0	0
T19	6964	6592	0	0
T20	5052	4844	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396141728	395279982	0	0
CheckNGreaterZero_A	1043	1043	0	0
GntImpliesReady_A	396141728	110175129	0	0
GntImpliesValid_A	396141728	110175129	0	0
GrantKnown_A	396141728	395279982	0	0
IdxKnown_A	396141728	395279982	0	0
IndexIsCorrect_A	396141728	110175129	0	0
NoReadyValidNoGrant_A	396141728	48211591	0	0
Priority_A	396141728	116194177	0	0
ReadyAndValidImplyGrant_A	396141728	110175129	0	0
ReqAndReadyImplyGrant_A	396141728	110175129	0	0
ReqImpliesValid_A	396141728	116194177	0	0
ValidKnown_A	396141728	395279982	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	395279982	0	0
T1	3942	3879	0	0
T2	1673	1520	0	0
T3	257018	245809	0	0
T4	5011	4719	0	0
T5	150570	150474	0	0
T10	394889	394873	0	0
T17	1404	1267	0	0
T18	1350	1252	0	0
T19	1741	1648	0	0
T20	1263	1211	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1043	1043	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	110175129	0	0
T1	3942	1178	0	0
T2	1673	98	0	0
T3	257018	111307	0	0
T4	5011	367	0	0
T5	150570	48538	0	0
T10	394889	137455	0	0
T17	1404	64	0	0
T18	1350	32	0	0
T19	1741	188	0	0
T20	1263	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	110175129	0	0
T1	3942	1178	0	0
T2	1673	98	0	0
T3	257018	111307	0	0
T4	5011	367	0	0
T5	150570	48538	0	0
T10	394889	137455	0	0
T17	1404	64	0	0
T18	1350	32	0	0
T19	1741	188	0	0
T20	1263	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	395279982	0	0
T1	3942	3879	0	0
T2	1673	1520	0	0
T3	257018	245809	0	0
T4	5011	4719	0	0
T5	150570	150474	0	0
T10	394889	394873	0	0
T17	1404	1267	0	0
T18	1350	1252	0	0
T19	1741	1648	0	0
T20	1263	1211	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	395279982	0	0
T1	3942	3879	0	0
T2	1673	1520	0	0
T3	257018	245809	0	0
T4	5011	4719	0	0
T5	150570	150474	0	0
T10	394889	394873	0	0
T17	1404	1267	0	0
T18	1350	1252	0	0
T19	1741	1648	0	0
T20	1263	1211	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	110175129	0	0
T1	3942	1178	0	0
T2	1673	98	0	0
T3	257018	111307	0	0
T4	5011	367	0	0
T5	150570	48538	0	0
T10	394889	137455	0	0
T17	1404	64	0	0
T18	1350	32	0	0
T19	1741	188	0	0
T20	1263	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	48211591	0	0
T1	3942	257	0	0
T2	1673	341	0	0
T3	257018	28800	0	0
T4	5011	559	0	0
T5	150570	31893	0	0
T10	394889	536832	0	0
T17	1404	256	0	0
T18	1350	128	0	0
T19	1741	128	0	0
T20	1263	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	116194177	0	0
T1	3942	1180	0	0
T2	1673	98	0	0
T3	257018	111307	0	0
T4	5011	367	0	0
T5	150570	59011	0	0
T10	394889	137455	0	0
T17	1404	64	0	0
T18	1350	32	0	0
T19	1741	188	0	0
T20	1263	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	110175129	0	0
T1	3942	1178	0	0
T2	1673	98	0	0
T3	257018	111307	0	0
T4	5011	367	0	0
T5	150570	48538	0	0
T10	394889	137455	0	0
T17	1404	64	0	0
T18	1350	32	0	0
T19	1741	188	0	0
T20	1263	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	110175129	0	0
T1	3942	1178	0	0
T2	1673	98	0	0
T3	257018	111307	0	0
T4	5011	367	0	0
T5	150570	48538	0	0
T10	394889	137455	0	0
T17	1404	64	0	0
T18	1350	32	0	0
T19	1741	188	0	0
T20	1263	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	116194177	0	0
T1	3942	1180	0	0
T2	1673	98	0	0
T3	257018	111307	0	0
T4	5011	367	0	0
T5	150570	59011	0	0
T10	394889	137455	0	0
T17	1404	64	0	0
T18	1350	32	0	0
T19	1741	188	0	0
T20	1263	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	395279982	0	0
T1	3942	3879	0	0
T2	1673	1520	0	0
T3	257018	245809	0	0
T4	5011	4719	0	0
T5	150570	150474	0	0
T10	394889	394873	0	0
T17	1404	1267	0	0
T18	1350	1252	0	0
T19	1741	1648	0	0
T20	1263	1211	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396141728	395279982	0	0
CheckNGreaterZero_A	1043	1043	0	0
GntImpliesReady_A	396141728	110175129	0	0
GntImpliesValid_A	396141728	110175129	0	0
GrantKnown_A	396141728	395279982	0	0
IdxKnown_A	396141728	395279982	0	0
IndexIsCorrect_A	396141728	110175129	0	0
NoReadyValidNoGrant_A	396141728	48211591	0	0
Priority_A	396141728	116194177	0	0
ReadyAndValidImplyGrant_A	396141728	110175129	0	0
ReqAndReadyImplyGrant_A	396141728	110175129	0	0
ReqImpliesValid_A	396141728	116194177	0	0
ValidKnown_A	396141728	395279982	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	395279982	0	0
T1	3942	3879	0	0
T2	1673	1520	0	0
T3	257018	245809	0	0
T4	5011	4719	0	0
T5	150570	150474	0	0
T10	394889	394873	0	0
T17	1404	1267	0	0
T18	1350	1252	0	0
T19	1741	1648	0	0
T20	1263	1211	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1043	1043	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	110175129	0	0
T1	3942	1178	0	0
T2	1673	98	0	0
T3	257018	111307	0	0
T4	5011	367	0	0
T5	150570	48538	0	0
T10	394889	137455	0	0
T17	1404	64	0	0
T18	1350	32	0	0
T19	1741	188	0	0
T20	1263	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	110175129	0	0
T1	3942	1178	0	0
T2	1673	98	0	0
T3	257018	111307	0	0
T4	5011	367	0	0
T5	150570	48538	0	0
T10	394889	137455	0	0
T17	1404	64	0	0
T18	1350	32	0	0
T19	1741	188	0	0
T20	1263	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	395279982	0	0
T1	3942	3879	0	0
T2	1673	1520	0	0
T3	257018	245809	0	0
T4	5011	4719	0	0
T5	150570	150474	0	0
T10	394889	394873	0	0
T17	1404	1267	0	0
T18	1350	1252	0	0
T19	1741	1648	0	0
T20	1263	1211	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	395279982	0	0
T1	3942	3879	0	0
T2	1673	1520	0	0
T3	257018	245809	0	0
T4	5011	4719	0	0
T5	150570	150474	0	0
T10	394889	394873	0	0
T17	1404	1267	0	0
T18	1350	1252	0	0
T19	1741	1648	0	0
T20	1263	1211	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	110175129	0	0
T1	3942	1178	0	0
T2	1673	98	0	0
T3	257018	111307	0	0
T4	5011	367	0	0
T5	150570	48538	0	0
T10	394889	137455	0	0
T17	1404	64	0	0
T18	1350	32	0	0
T19	1741	188	0	0
T20	1263	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	48211591	0	0
T1	3942	257	0	0
T2	1673	341	0	0
T3	257018	28800	0	0
T4	5011	559	0	0
T5	150570	31893	0	0
T10	394889	536832	0	0
T17	1404	256	0	0
T18	1350	128	0	0
T19	1741	128	0	0
T20	1263	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	116194177	0	0
T1	3942	1180	0	0
T2	1673	98	0	0
T3	257018	111307	0	0
T4	5011	367	0	0
T5	150570	59011	0	0
T10	394889	137455	0	0
T17	1404	64	0	0
T18	1350	32	0	0
T19	1741	188	0	0
T20	1263	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	110175129	0	0
T1	3942	1178	0	0
T2	1673	98	0	0
T3	257018	111307	0	0
T4	5011	367	0	0
T5	150570	48538	0	0
T10	394889	137455	0	0
T17	1404	64	0	0
T18	1350	32	0	0
T19	1741	188	0	0
T20	1263	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	110175129	0	0
T1	3942	1178	0	0
T2	1673	98	0	0
T3	257018	111307	0	0
T4	5011	367	0	0
T5	150570	48538	0	0
T10	394889	137455	0	0
T17	1404	64	0	0
T18	1350	32	0	0
T19	1741	188	0	0
T20	1263	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	116194177	0	0
T1	3942	1180	0	0
T2	1673	98	0	0
T3	257018	111307	0	0
T4	5011	367	0	0
T5	150570	59011	0	0
T10	394889	137455	0	0
T17	1404	64	0	0
T18	1350	32	0	0
T19	1741	188	0	0
T20	1263	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	395279982	0	0
T1	3942	3879	0	0
T2	1673	1520	0	0
T3	257018	245809	0	0
T4	5011	4719	0	0
T5	150570	150474	0	0
T10	394889	394873	0	0
T17	1404	1267	0	0
T18	1350	1252	0	0
T19	1741	1648	0	0
T20	1263	1211	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T17
1	0	Covered	T1,T2,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T24
1	0	Covered	T1,T2,T17
1	1	Covered	T1,T2,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T17

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T24
1	1	Covered	T1,T2,T17

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396141728	395279982	0	0
CheckNGreaterZero_A	1043	1043	0	0
GntImpliesReady_A	396141728	97832841	0	0
GntImpliesValid_A	396141728	97832841	0	0
GrantKnown_A	396141728	395279982	0	0
IdxKnown_A	396141728	395279982	0	0
IndexIsCorrect_A	396141728	97832841	0	0
NoReadyValidNoGrant_A	396141728	43884668	0	0
Priority_A	396141728	103888740	0	0
ReadyAndValidImplyGrant_A	396141728	97832841	0	0
ReqAndReadyImplyGrant_A	396141728	97832841	0	0
ReqImpliesValid_A	396141728	103888740	0	0
ValidKnown_A	396141728	395279982	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	395279982	0	0
T1	3942	3879	0	0
T2	1673	1520	0	0
T3	257018	245809	0	0
T4	5011	4719	0	0
T5	150570	150474	0	0
T10	394889	394873	0	0
T17	1404	1267	0	0
T18	1350	1252	0	0
T19	1741	1648	0	0
T20	1263	1211	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1043	1043	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	97832841	0	0
T1	3942	339	0	0
T2	1673	79	0	0
T3	257018	0	0	0
T4	5011	13	0	0
T5	150570	46260	0	0
T6	0	9	0	0
T10	394889	134806	0	0
T17	1404	24	0	0
T18	1350	0	0	0
T19	1741	11	0	0
T20	1263	0	0	0
T24	0	1343	0	0
T44	0	210	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	97832841	0	0
T1	3942	339	0	0
T2	1673	79	0	0
T3	257018	0	0	0
T4	5011	13	0	0
T5	150570	46260	0	0
T6	0	9	0	0
T10	394889	134806	0	0
T17	1404	24	0	0
T18	1350	0	0	0
T19	1741	11	0	0
T20	1263	0	0	0
T24	0	1343	0	0
T44	0	210	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	395279982	0	0
T1	3942	3879	0	0
T2	1673	1520	0	0
T3	257018	245809	0	0
T4	5011	4719	0	0
T5	150570	150474	0	0
T10	394889	394873	0	0
T17	1404	1267	0	0
T18	1350	1252	0	0
T19	1741	1648	0	0
T20	1263	1211	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	395279982	0	0
T1	3942	3879	0	0
T2	1673	1520	0	0
T3	257018	245809	0	0
T4	5011	4719	0	0
T5	150570	150474	0	0
T10	394889	394873	0	0
T17	1404	1267	0	0
T18	1350	1252	0	0
T19	1741	1648	0	0
T20	1263	1211	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	97832841	0	0
T1	3942	339	0	0
T2	1673	79	0	0
T3	257018	0	0	0
T4	5011	13	0	0
T5	150570	46260	0	0
T6	0	9	0	0
T10	394889	134806	0	0
T17	1404	24	0	0
T18	1350	0	0	0
T19	1741	11	0	0
T20	1263	0	0	0
T24	0	1343	0	0
T44	0	210	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	43884668	0	0
T1	3942	124	0	0
T2	1673	40	0	0
T3	257018	0	0	0
T4	5011	20	0	0
T5	150570	25363	0	0
T6	0	10	0	0
T10	394889	525824	0	0
T17	1404	0	0	0
T18	1350	0	0	0
T19	1741	17	0	0
T20	1263	0	0	0
T22	0	31960	0	0
T24	0	118	0	0
T38	0	857	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	103888740	0	0
T1	3942	339	0	0
T2	1673	79	0	0
T3	257018	0	0	0
T4	5011	13	0	0
T5	150570	51980	0	0
T6	0	12	0	0
T10	394889	134806	0	0
T17	1404	24	0	0
T18	1350	0	0	0
T19	1741	11	0	0
T20	1263	0	0	0
T24	0	1343	0	0
T44	0	210	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	97832841	0	0
T1	3942	339	0	0
T2	1673	79	0	0
T3	257018	0	0	0
T4	5011	13	0	0
T5	150570	46260	0	0
T6	0	9	0	0
T10	394889	134806	0	0
T17	1404	24	0	0
T18	1350	0	0	0
T19	1741	11	0	0
T20	1263	0	0	0
T24	0	1343	0	0
T44	0	210	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	97832841	0	0
T1	3942	339	0	0
T2	1673	79	0	0
T3	257018	0	0	0
T4	5011	13	0	0
T5	150570	46260	0	0
T6	0	9	0	0
T10	394889	134806	0	0
T17	1404	24	0	0
T18	1350	0	0	0
T19	1741	11	0	0
T20	1263	0	0	0
T24	0	1343	0	0
T44	0	210	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	103888740	0	0
T1	3942	339	0	0
T2	1673	79	0	0
T3	257018	0	0	0
T4	5011	13	0	0
T5	150570	51980	0	0
T6	0	12	0	0
T10	394889	134806	0	0
T17	1404	24	0	0
T18	1350	0	0	0
T19	1741	11	0	0
T20	1263	0	0	0
T24	0	1343	0	0
T44	0	210	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	395279982	0	0
T1	3942	3879	0	0
T2	1673	1520	0	0
T3	257018	245809	0	0
T4	5011	4719	0	0
T5	150570	150474	0	0
T10	394889	394873	0	0
T17	1404	1267	0	0
T18	1350	1252	0	0
T19	1741	1648	0	0
T20	1263	1211	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T17
1	0	Covered	T1,T2,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T5,T24
1	0	Covered	T1,T2,T17
1	1	Covered	T1,T2,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T17

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T5,T24
1	1	Covered	T1,T2,T17

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	396141728	395279982	0	0
CheckNGreaterZero_A	1043	1043	0	0
GntImpliesReady_A	396141728	97832873	0	0
GntImpliesValid_A	396141728	97832873	0	0
GrantKnown_A	396141728	395279982	0	0
IdxKnown_A	396141728	395279982	0	0
IndexIsCorrect_A	396141728	97832873	0	0
NoReadyValidNoGrant_A	396141728	43884601	0	0
Priority_A	396141728	103888839	0	0
ReadyAndValidImplyGrant_A	396141728	97832873	0	0
ReqAndReadyImplyGrant_A	396141728	97832873	0	0
ReqImpliesValid_A	396141728	103888839	0	0
ValidKnown_A	396141728	395279982	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	395279982	0	0
T1	3942	3879	0	0
T2	1673	1520	0	0
T3	257018	245809	0	0
T4	5011	4719	0	0
T5	150570	150474	0	0
T10	394889	394873	0	0
T17	1404	1267	0	0
T18	1350	1252	0	0
T19	1741	1648	0	0
T20	1263	1211	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1043	1043	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	97832873	0	0
T1	3942	339	0	0
T2	1673	79	0	0
T3	257018	0	0	0
T4	5011	13	0	0
T5	150570	46260	0	0
T6	0	9	0	0
T10	394889	134806	0	0
T17	1404	24	0	0
T18	1350	0	0	0
T19	1741	11	0	0
T20	1263	0	0	0
T24	0	1343	0	0
T44	0	210	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	97832873	0	0
T1	3942	339	0	0
T2	1673	79	0	0
T3	257018	0	0	0
T4	5011	13	0	0
T5	150570	46260	0	0
T6	0	9	0	0
T10	394889	134806	0	0
T17	1404	24	0	0
T18	1350	0	0	0
T19	1741	11	0	0
T20	1263	0	0	0
T24	0	1343	0	0
T44	0	210	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	395279982	0	0
T1	3942	3879	0	0
T2	1673	1520	0	0
T3	257018	245809	0	0
T4	5011	4719	0	0
T5	150570	150474	0	0
T10	394889	394873	0	0
T17	1404	1267	0	0
T18	1350	1252	0	0
T19	1741	1648	0	0
T20	1263	1211	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	395279982	0	0
T1	3942	3879	0	0
T2	1673	1520	0	0
T3	257018	245809	0	0
T4	5011	4719	0	0
T5	150570	150474	0	0
T10	394889	394873	0	0
T17	1404	1267	0	0
T18	1350	1252	0	0
T19	1741	1648	0	0
T20	1263	1211	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	97832873	0	0
T1	3942	339	0	0
T2	1673	79	0	0
T3	257018	0	0	0
T4	5011	13	0	0
T5	150570	46260	0	0
T6	0	9	0	0
T10	394889	134806	0	0
T17	1404	24	0	0
T18	1350	0	0	0
T19	1741	11	0	0
T20	1263	0	0	0
T24	0	1343	0	0
T44	0	210	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	43884601	0	0
T1	3942	124	0	0
T2	1673	40	0	0
T3	257018	0	0	0
T4	5011	20	0	0
T5	150570	25363	0	0
T6	0	10	0	0
T10	394889	525824	0	0
T17	1404	0	0	0
T18	1350	0	0	0
T19	1741	17	0	0
T20	1263	0	0	0
T22	0	31960	0	0
T24	0	118	0	0
T38	0	857	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	103888839	0	0
T1	3942	339	0	0
T2	1673	79	0	0
T3	257018	0	0	0
T4	5011	13	0	0
T5	150570	51980	0	0
T6	0	12	0	0
T10	394889	134806	0	0
T17	1404	24	0	0
T18	1350	0	0	0
T19	1741	11	0	0
T20	1263	0	0	0
T24	0	1343	0	0
T44	0	210	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	97832873	0	0
T1	3942	339	0	0
T2	1673	79	0	0
T3	257018	0	0	0
T4	5011	13	0	0
T5	150570	46260	0	0
T6	0	9	0	0
T10	394889	134806	0	0
T17	1404	24	0	0
T18	1350	0	0	0
T19	1741	11	0	0
T20	1263	0	0	0
T24	0	1343	0	0
T44	0	210	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	97832873	0	0
T1	3942	339	0	0
T2	1673	79	0	0
T3	257018	0	0	0
T4	5011	13	0	0
T5	150570	46260	0	0
T6	0	9	0	0
T10	394889	134806	0	0
T17	1404	24	0	0
T18	1350	0	0	0
T19	1741	11	0	0
T20	1263	0	0	0
T24	0	1343	0	0
T44	0	210	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	103888839	0	0
T1	3942	339	0	0
T2	1673	79	0	0
T3	257018	0	0	0
T4	5011	13	0	0
T5	150570	51980	0	0
T6	0	12	0	0
T10	394889	134806	0	0
T17	1404	24	0	0
T18	1350	0	0	0
T19	1741	11	0	0
T20	1263	0	0	0
T24	0	1343	0	0
T44	0	210	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	396141728	395279982	0	0
T1	3942	3879	0	0
T2	1673	1520	0	0
T3	257018	245809	0	0
T4	5011	4719	0	0
T5	150570	150474	0	0
T10	394889	394873	0	0
T17	1404	1267	0	0
T18	1350	1252	0	0
T19	1741	1648	0	0
T20	1263	1211	0	0