Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	24833280	1		T1	120		T2	20		T3	81236
full_word	7832449	1		T1	42		T3	15937		T12	3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	32665429	1		T1	162		T2	20		T3	97173
auto[TlIntgErrCmd]	115	1		T69	8		T102	5		T203	6
auto[TlIntgErrData]	93	1		T69	5		T102	3		T203	7
auto[TlIntgErrBoth]	92	1		T69	7		T102	2		T203	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	28144364	1		T1	115		T2	19		T3	87182
auto[1]	4521365	1		T1	47		T2	1		T3	9991

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	24126158	1		T1	115		T2	19		T3	79912
auto[TlIntgErrNone]	partial	auto[1]	706850	1		T1	5		T2	1		T3	1324
auto[TlIntgErrNone]	full_word	auto[0]	4018078	1		T3	7270		T12	1		T4	1
auto[TlIntgErrNone]	full_word	auto[1]	3814343	1		T1	42		T3	8667		T12	2
auto[TlIntgErrCmd]	partial	auto[0]	39	1		T69	4		T102	2		T203	1
auto[TlIntgErrCmd]	partial	auto[1]	67	1		T69	4		T102	2		T203	5
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T102	1		T350	1		T352	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T217	3		T355	1		T356	1
auto[TlIntgErrData]	partial	auto[0]	41	1		T69	2		T102	1		T203	2
auto[TlIntgErrData]	partial	auto[1]	41	1		T69	2		T102	1		T203	5
auto[TlIntgErrData]	full_word	auto[0]	2	1		T357	2		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	9	1		T69	1		T102	1		T352	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1		T69	1		T102	1		T203	3
auto[TlIntgErrBoth]	partial	auto[1]	46	1		T69	4		T102	1		T203	4
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T350	1		T355	1		T253	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T69	2		T253	1		-	-

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	21293	1		T101	581		T68	31		T69	18
full_word	3773854	1		T3	11470		T7	16613		T8	16594

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3794864	1		T3	11470		T7	16613		T8	16594
auto[TlIntgErrCmd]	93	1		T69	3		T102	1		T203	6
auto[TlIntgErrData]	94	1		T69	8		T102	3		T203	5
auto[TlIntgErrBoth]	96	1		T69	7		T102	5		T203	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3767488	1		T3	11470		T7	16613		T8	16594
auto[1]	27659	1		T101	706		T68	41		T69	13

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1327	1		T101	53		T68	3		T202	20
auto[TlIntgErrNone]	partial	auto[1]	19702	1		T101	528		T68	28		T202	406
auto[TlIntgErrNone]	full_word	auto[0]	3766045	1		T3	11470		T7	16613		T8	16594
auto[TlIntgErrNone]	full_word	auto[1]	7790	1		T101	178		T68	13		T202	59
auto[TlIntgErrCmd]	partial	auto[0]	30	1		T203	2		T217	3		T350	2
auto[TlIntgErrCmd]	partial	auto[1]	57	1		T69	3		T102	1		T203	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T352	1		T356	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T350	1		T353	1		T251	1
auto[TlIntgErrData]	partial	auto[0]	52	1		T69	4		T102	2		T203	3
auto[TlIntgErrData]	partial	auto[1]	35	1		T69	4		T102	1		T203	2
auto[TlIntgErrData]	full_word	auto[0]	3	1		T349	1		T248	1		T252	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T253	1		T251	1		T252	2
auto[TlIntgErrBoth]	partial	auto[0]	26	1		T69	1		T102	2		T203	2
auto[TlIntgErrBoth]	partial	auto[1]	64	1		T69	6		T102	3		T203	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T355	1		T358	1		T352	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T203	1		T355	1		T252	1