Unified Coverage Report :: Module :: flash_ctrl_erase

Module : flash_ctrl_erase

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_erase.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_ctrl_erase	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_flash_ctrl_erase

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.69	97.12	93.60	98.44		100.00	84.29	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : flash_ctrl_erase

	Line No.	Total	Covered	Percent
TOTAL		9	9	100.00
CONT_ASSIGN	43	0	0
CONT_ASSIGN	46	1	1	100.00
ALWAYS	49	3	3	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	57	1	1	100.00
CONT_ASSIGN	58	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	66	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_erase.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_erase.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
43		unreachable
46	1	1
49	1	1
50	1	1
51	1	1
56	1	1
57	1	1
58	1	1
62	1	1
66	1	1

---

Cond Coverage for Module : flash_ctrl_erase

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       43
 EXPRESSION (op_start_i & op_addr_oob_i)
             -----1----   ------2------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T4,T5
1	1	Unreachable

 LINE       46
 EXPRESSION (flash_req_o & (flash_done_i | oob_err))
             -----1-----   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T13
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       46
 SUB-EXPRESSION (flash_done_i | oob_err)
                 ------1-----   ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T3,T4

 LINE       50
 EXPRESSION (op_done_o & oob_err)
             ----1----   ---2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T4,T5
1	1	Unreachable

 LINE       51
 EXPRESSION (op_done_o & flash_mp_err_i)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T13
1	0	Covered	T1,T4,T5
1	1	Covered	T5,T30,T24

 LINE       56
 EXPRESSION (op_start_i & ((~op_addr_oob_i)))
             -----1----   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T4,T5

 LINE       58
 EXPRESSION ((op_type_i == FlashErasePage) ? ((op_addr_i & PageAddrMask)) : ((op_addr_i & BankAddrMask)))
             --------------1--------------

-1-	Status	Tests
0	Covered	T3,T16,T7
1	Covered	T1,T2,T3

 LINE       58
 SUB-EXPRESSION (op_type_i == FlashErasePage)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : flash_ctrl_erase

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	58	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_erase.sv' or '../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_erase.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	58	((op_type_i == FlashErasePage)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T16,T7