Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T7,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T7,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T7,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T7,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T7,T8

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1632531328	1629097896	0	0
CheckNGreaterZero_A	4164	4164	0	0
GntImpliesReady_A	1632531328	410842516	0	0
GntImpliesValid_A	1632531328	410842516	0	0
GrantKnown_A	1632531328	1629097896	0	0
IdxKnown_A	1632531328	1629097896	0	0
IndexIsCorrect_A	1632531328	410842516	0	0
NoReadyValidNoGrant_A	1632531328	175499825	0	0
Priority_A	1632531328	434694585	0	0
ReadyAndValidImplyGrant_A	1632531328	410842516	0	0
ReqAndReadyImplyGrant_A	1632531328	410842516	0	0
ReqImpliesValid_A	1632531328	434694585	0	0
ValidKnown_A	1632531328	1629097896	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1632531328	1629097896	0	0
T1	1003492	1002784	0	0
T2	6072	5812	0	0
T3	785920	785524	0	0
T4	5064	4732	0	0
T5	688108	687744	0	0
T6	1676452	1599776	0	0
T7	521564	521504	0	0
T12	13640	11048	0	0
T13	4396	3388	0	0
T16	7052	6852	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4164	4164	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T12	4	4	0	0
T13	4	4	0	0
T16	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1632531328	410842516	0	0
T1	501746	143672	0	0
T2	3036	64	0	0
T3	785920	283510	0	0
T4	5064	584	0	0
T5	688108	27094	0	0
T6	1676452	361612	0	0
T7	521564	92376	0	0
T8	0	38582	0	0
T12	13640	344	0	0
T13	4396	134	0	0
T16	7052	618	0	0
T22	0	207118	0	0
T30	938714	156116	0	0
T38	0	8	0	0
T40	0	18426	0	0
T44	0	61234	0	0
T54	288932	96690	0	0
T61	0	222628	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1632531328	410842516	0	0
T1	501746	143672	0	0
T2	3036	64	0	0
T3	785920	283510	0	0
T4	5064	584	0	0
T5	688108	27094	0	0
T6	1676452	361612	0	0
T7	521564	92376	0	0
T8	0	38582	0	0
T12	13640	344	0	0
T13	4396	134	0	0
T16	7052	618	0	0
T22	0	207118	0	0
T30	938714	156116	0	0
T38	0	8	0	0
T40	0	18426	0	0
T44	0	61234	0	0
T54	288932	96690	0	0
T61	0	222628	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1632531328	1629097896	0	0
T1	1003492	1002784	0	0
T2	6072	5812	0	0
T3	785920	785524	0	0
T4	5064	4732	0	0
T5	688108	687744	0	0
T6	1676452	1599776	0	0
T7	521564	521504	0	0
T12	13640	11048	0	0
T13	4396	3388	0	0
T16	7052	6852	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1632531328	1629097896	0	0
T1	1003492	1002784	0	0
T2	6072	5812	0	0
T3	785920	785524	0	0
T4	5064	4732	0	0
T5	688108	687744	0	0
T6	1676452	1599776	0	0
T7	521564	521504	0	0
T12	13640	11048	0	0
T13	4396	3388	0	0
T16	7052	6852	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1632531328	410842516	0	0
T1	501746	143672	0	0
T2	3036	64	0	0
T3	785920	283510	0	0
T4	5064	584	0	0
T5	688108	27094	0	0
T6	1676452	361612	0	0
T7	521564	92376	0	0
T8	0	38582	0	0
T12	13640	344	0	0
T13	4396	134	0	0
T16	7052	618	0	0
T22	0	207118	0	0
T30	938714	156116	0	0
T38	0	8	0	0
T40	0	18426	0	0
T44	0	61234	0	0
T54	288932	96690	0	0
T61	0	222628	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1632531328	175499825	0	0
T1	501746	190226	0	0
T2	3036	256	0	0
T3	785920	76000	0	0
T4	5064	256	0	0
T5	688108	128	0	0
T6	1676452	93416	0	0
T7	521564	2783214	0	0
T8	0	1214374	0	0
T12	13640	1376	0	0
T13	4396	536	0	0
T16	7052	256	0	0
T19	0	592	0	0
T20	0	1392	0	0
T24	0	134	0	0
T30	938714	3318	0	0
T38	0	14	0	0
T40	0	53610	0	0
T44	0	3648	0	0
T54	288932	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1632531328	434694585	0	0
T1	501746	143672	0	0
T2	3036	64	0	0
T3	785920	313742	0	0
T4	5064	584	0	0
T5	688108	27094	0	0
T6	1676452	361612	0	0
T7	521564	603436	0	0
T8	0	260630	0	0
T12	13640	344	0	0
T13	4396	134	0	0
T16	7052	618	0	0
T22	0	207118	0	0
T30	938714	156116	0	0
T38	0	8	0	0
T40	0	20084	0	0
T44	0	61234	0	0
T54	288932	96690	0	0
T61	0	222628	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1632531328	410842516	0	0
T1	501746	143672	0	0
T2	3036	64	0	0
T3	785920	283510	0	0
T4	5064	584	0	0
T5	688108	27094	0	0
T6	1676452	361612	0	0
T7	521564	92376	0	0
T8	0	38582	0	0
T12	13640	344	0	0
T13	4396	134	0	0
T16	7052	618	0	0
T22	0	207118	0	0
T30	938714	156116	0	0
T38	0	8	0	0
T40	0	18426	0	0
T44	0	61234	0	0
T54	288932	96690	0	0
T61	0	222628	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1632531328	410842516	0	0
T1	501746	143672	0	0
T2	3036	64	0	0
T3	785920	283510	0	0
T4	5064	584	0	0
T5	688108	27094	0	0
T6	1676452	361612	0	0
T7	521564	92376	0	0
T8	0	38582	0	0
T12	13640	344	0	0
T13	4396	134	0	0
T16	7052	618	0	0
T22	0	207118	0	0
T30	938714	156116	0	0
T38	0	8	0	0
T40	0	18426	0	0
T44	0	61234	0	0
T54	288932	96690	0	0
T61	0	222628	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1632531328	434694585	0	0
T1	501746	143672	0	0
T2	3036	64	0	0
T3	785920	313742	0	0
T4	5064	584	0	0
T5	688108	27094	0	0
T6	1676452	361612	0	0
T7	521564	603436	0	0
T8	0	260630	0	0
T12	13640	344	0	0
T13	4396	134	0	0
T16	7052	618	0	0
T22	0	207118	0	0
T30	938714	156116	0	0
T38	0	8	0	0
T40	0	20084	0	0
T44	0	61234	0	0
T54	288932	96690	0	0
T61	0	222628	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1632531328	1629097896	0	0
T1	1003492	1002784	0	0
T2	6072	5812	0	0
T3	785920	785524	0	0
T4	5064	4732	0	0
T5	688108	687744	0	0
T6	1676452	1599776	0	0
T7	521564	521504	0	0
T12	13640	11048	0	0
T13	4396	3388	0	0
T16	7052	6852	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T7,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T7,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T7,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T7,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T7,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408132832	407274474	0	0
CheckNGreaterZero_A	1041	1041	0	0
GntImpliesReady_A	408132832	111151133	0	0
GntImpliesValid_A	408132832	111151133	0	0
GrantKnown_A	408132832	407274474	0	0
IdxKnown_A	408132832	407274474	0	0
IndexIsCorrect_A	408132832	111151133	0	0
NoReadyValidNoGrant_A	408132832	46134960	0	0
Priority_A	408132832	117068455	0	0
ReadyAndValidImplyGrant_A	408132832	111151133	0	0
ReqAndReadyImplyGrant_A	408132832	111151133	0	0
ReqImpliesValid_A	408132832	117068455	0	0
ValidKnown_A	408132832	407274474	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	407274474	0	0
T1	250873	250696	0	0
T2	1518	1453	0	0
T3	196480	196381	0	0
T4	1266	1183	0	0
T5	172027	171936	0	0
T6	419113	399944	0	0
T7	130391	130376	0	0
T12	3410	2762	0	0
T13	1099	847	0	0
T16	1763	1713	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1041	1041	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	111151133	0	0
T1	250873	71836	0	0
T2	1518	32	0	0
T3	196480	71207	0	0
T4	1266	292	0	0
T5	172027	13547	0	0
T6	419113	180806	0	0
T7	130391	20937	0	0
T12	3410	172	0	0
T13	1099	67	0	0
T16	1763	309	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	111151133	0	0
T1	250873	71836	0	0
T2	1518	32	0	0
T3	196480	71207	0	0
T4	1266	292	0	0
T5	172027	13547	0	0
T6	419113	180806	0	0
T7	130391	20937	0	0
T12	3410	172	0	0
T13	1099	67	0	0
T16	1763	309	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	407274474	0	0
T1	250873	250696	0	0
T2	1518	1453	0	0
T3	196480	196381	0	0
T4	1266	1183	0	0
T5	172027	171936	0	0
T6	419113	399944	0	0
T7	130391	130376	0	0
T12	3410	2762	0	0
T13	1099	847	0	0
T16	1763	1713	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	407274474	0	0
T1	250873	250696	0	0
T2	1518	1453	0	0
T3	196480	196381	0	0
T4	1266	1183	0	0
T5	172027	171936	0	0
T6	419113	399944	0	0
T7	130391	130376	0	0
T12	3410	2762	0	0
T13	1099	847	0	0
T16	1763	1713	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	111151133	0	0
T1	250873	71836	0	0
T2	1518	32	0	0
T3	196480	71207	0	0
T4	1266	292	0	0
T5	172027	13547	0	0
T6	419113	180806	0	0
T7	130391	20937	0	0
T12	3410	172	0	0
T13	1099	67	0	0
T16	1763	309	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	46134960	0	0
T1	250873	95113	0	0
T2	1518	128	0	0
T3	196480	24429	0	0
T4	1266	128	0	0
T5	172027	64	0	0
T6	419113	46708	0	0
T7	130391	640072	0	0
T12	3410	688	0	0
T13	1099	268	0	0
T16	1763	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	117068455	0	0
T1	250873	71836	0	0
T2	1518	32	0	0
T3	196480	81840	0	0
T4	1266	292	0	0
T5	172027	13547	0	0
T6	419113	180806	0	0
T7	130391	150691	0	0
T12	3410	172	0	0
T13	1099	67	0	0
T16	1763	309	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	111151133	0	0
T1	250873	71836	0	0
T2	1518	32	0	0
T3	196480	71207	0	0
T4	1266	292	0	0
T5	172027	13547	0	0
T6	419113	180806	0	0
T7	130391	20937	0	0
T12	3410	172	0	0
T13	1099	67	0	0
T16	1763	309	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	111151133	0	0
T1	250873	71836	0	0
T2	1518	32	0	0
T3	196480	71207	0	0
T4	1266	292	0	0
T5	172027	13547	0	0
T6	419113	180806	0	0
T7	130391	20937	0	0
T12	3410	172	0	0
T13	1099	67	0	0
T16	1763	309	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	117068455	0	0
T1	250873	71836	0	0
T2	1518	32	0	0
T3	196480	81840	0	0
T4	1266	292	0	0
T5	172027	13547	0	0
T6	419113	180806	0	0
T7	130391	150691	0	0
T12	3410	172	0	0
T13	1099	67	0	0
T16	1763	309	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	407274474	0	0
T1	250873	250696	0	0
T2	1518	1453	0	0
T3	196480	196381	0	0
T4	1266	1183	0	0
T5	172027	171936	0	0
T6	419113	399944	0	0
T7	130391	130376	0	0
T12	3410	2762	0	0
T13	1099	847	0	0
T16	1763	1713	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T7,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T7,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T7,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T7,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T7,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408132832	407274474	0	0
CheckNGreaterZero_A	1041	1041	0	0
GntImpliesReady_A	408132832	111151128	0	0
GntImpliesValid_A	408132832	111151128	0	0
GrantKnown_A	408132832	407274474	0	0
IdxKnown_A	408132832	407274474	0	0
IndexIsCorrect_A	408132832	111151128	0	0
NoReadyValidNoGrant_A	408132832	46134951	0	0
Priority_A	408132832	117068459	0	0
ReadyAndValidImplyGrant_A	408132832	111151128	0	0
ReqAndReadyImplyGrant_A	408132832	111151128	0	0
ReqImpliesValid_A	408132832	117068459	0	0
ValidKnown_A	408132832	407274474	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	407274474	0	0
T1	250873	250696	0	0
T2	1518	1453	0	0
T3	196480	196381	0	0
T4	1266	1183	0	0
T5	172027	171936	0	0
T6	419113	399944	0	0
T7	130391	130376	0	0
T12	3410	2762	0	0
T13	1099	847	0	0
T16	1763	1713	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1041	1041	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	111151128	0	0
T1	250873	71836	0	0
T2	1518	32	0	0
T3	196480	71207	0	0
T4	1266	292	0	0
T5	172027	13547	0	0
T6	419113	180806	0	0
T7	130391	20937	0	0
T12	3410	172	0	0
T13	1099	67	0	0
T16	1763	309	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	111151128	0	0
T1	250873	71836	0	0
T2	1518	32	0	0
T3	196480	71207	0	0
T4	1266	292	0	0
T5	172027	13547	0	0
T6	419113	180806	0	0
T7	130391	20937	0	0
T12	3410	172	0	0
T13	1099	67	0	0
T16	1763	309	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	407274474	0	0
T1	250873	250696	0	0
T2	1518	1453	0	0
T3	196480	196381	0	0
T4	1266	1183	0	0
T5	172027	171936	0	0
T6	419113	399944	0	0
T7	130391	130376	0	0
T12	3410	2762	0	0
T13	1099	847	0	0
T16	1763	1713	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	407274474	0	0
T1	250873	250696	0	0
T2	1518	1453	0	0
T3	196480	196381	0	0
T4	1266	1183	0	0
T5	172027	171936	0	0
T6	419113	399944	0	0
T7	130391	130376	0	0
T12	3410	2762	0	0
T13	1099	847	0	0
T16	1763	1713	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	111151128	0	0
T1	250873	71836	0	0
T2	1518	32	0	0
T3	196480	71207	0	0
T4	1266	292	0	0
T5	172027	13547	0	0
T6	419113	180806	0	0
T7	130391	20937	0	0
T12	3410	172	0	0
T13	1099	67	0	0
T16	1763	309	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	46134951	0	0
T1	250873	95113	0	0
T2	1518	128	0	0
T3	196480	24429	0	0
T4	1266	128	0	0
T5	172027	64	0	0
T6	419113	46708	0	0
T7	130391	640072	0	0
T12	3410	688	0	0
T13	1099	268	0	0
T16	1763	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	117068459	0	0
T1	250873	71836	0	0
T2	1518	32	0	0
T3	196480	81840	0	0
T4	1266	292	0	0
T5	172027	13547	0	0
T6	419113	180806	0	0
T7	130391	150691	0	0
T12	3410	172	0	0
T13	1099	67	0	0
T16	1763	309	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	111151128	0	0
T1	250873	71836	0	0
T2	1518	32	0	0
T3	196480	71207	0	0
T4	1266	292	0	0
T5	172027	13547	0	0
T6	419113	180806	0	0
T7	130391	20937	0	0
T12	3410	172	0	0
T13	1099	67	0	0
T16	1763	309	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	111151128	0	0
T1	250873	71836	0	0
T2	1518	32	0	0
T3	196480	71207	0	0
T4	1266	292	0	0
T5	172027	13547	0	0
T6	419113	180806	0	0
T7	130391	20937	0	0
T12	3410	172	0	0
T13	1099	67	0	0
T16	1763	309	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	117068459	0	0
T1	250873	71836	0	0
T2	1518	32	0	0
T3	196480	81840	0	0
T4	1266	292	0	0
T5	172027	13547	0	0
T6	419113	180806	0	0
T7	130391	150691	0	0
T12	3410	172	0	0
T13	1099	67	0	0
T16	1763	309	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	407274474	0	0
T1	250873	250696	0	0
T2	1518	1453	0	0
T3	196480	196381	0	0
T4	1266	1183	0	0
T5	172027	171936	0	0
T6	419113	399944	0	0
T7	130391	130376	0	0
T12	3410	2762	0	0
T13	1099	847	0	0
T16	1763	1713	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T30
1	0	Covered	T3,T7,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T7,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T7,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T3,T7,T30
1	1	Covered	T3,T7,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T3,T7,T30

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T3,T7,T30

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T7,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T7,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408132832	407274474	0	0
CheckNGreaterZero_A	1041	1041	0	0
GntImpliesReady_A	408132832	94270103	0	0
GntImpliesValid_A	408132832	94270103	0	0
GrantKnown_A	408132832	407274474	0	0
IdxKnown_A	408132832	407274474	0	0
IndexIsCorrect_A	408132832	94270103	0	0
NoReadyValidNoGrant_A	408132832	41614974	0	0
Priority_A	408132832	100278794	0	0
ReadyAndValidImplyGrant_A	408132832	94270103	0	0
ReqAndReadyImplyGrant_A	408132832	94270103	0	0
ReqImpliesValid_A	408132832	100278794	0	0
ValidKnown_A	408132832	407274474	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	407274474	0	0
T1	250873	250696	0	0
T2	1518	1453	0	0
T3	196480	196381	0	0
T4	1266	1183	0	0
T5	172027	171936	0	0
T6	419113	399944	0	0
T7	130391	130376	0	0
T12	3410	2762	0	0
T13	1099	847	0	0
T16	1763	1713	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1041	1041	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	94270103	0	0
T3	196480	70548	0	0
T4	1266	0	0	0
T5	172027	0	0	0
T6	419113	0	0	0
T7	130391	25251	0	0
T8	0	19291	0	0
T12	3410	0	0	0
T13	1099	0	0	0
T16	1763	0	0	0
T22	0	103559	0	0
T30	469357	78058	0	0
T38	0	4	0	0
T40	0	9213	0	0
T44	0	30617	0	0
T54	144466	48345	0	0
T61	0	111314	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	94270103	0	0
T3	196480	70548	0	0
T4	1266	0	0	0
T5	172027	0	0	0
T6	419113	0	0	0
T7	130391	25251	0	0
T8	0	19291	0	0
T12	3410	0	0	0
T13	1099	0	0	0
T16	1763	0	0	0
T22	0	103559	0	0
T30	469357	78058	0	0
T38	0	4	0	0
T40	0	9213	0	0
T44	0	30617	0	0
T54	144466	48345	0	0
T61	0	111314	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	407274474	0	0
T1	250873	250696	0	0
T2	1518	1453	0	0
T3	196480	196381	0	0
T4	1266	1183	0	0
T5	172027	171936	0	0
T6	419113	399944	0	0
T7	130391	130376	0	0
T12	3410	2762	0	0
T13	1099	847	0	0
T16	1763	1713	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	407274474	0	0
T1	250873	250696	0	0
T2	1518	1453	0	0
T3	196480	196381	0	0
T4	1266	1183	0	0
T5	172027	171936	0	0
T6	419113	399944	0	0
T7	130391	130376	0	0
T12	3410	2762	0	0
T13	1099	847	0	0
T16	1763	1713	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	94270103	0	0
T3	196480	70548	0	0
T4	1266	0	0	0
T5	172027	0	0	0
T6	419113	0	0	0
T7	130391	25251	0	0
T8	0	19291	0	0
T12	3410	0	0	0
T13	1099	0	0	0
T16	1763	0	0	0
T22	0	103559	0	0
T30	469357	78058	0	0
T38	0	4	0	0
T40	0	9213	0	0
T44	0	30617	0	0
T54	144466	48345	0	0
T61	0	111314	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	41614974	0	0
T3	196480	13571	0	0
T4	1266	0	0	0
T5	172027	0	0	0
T6	419113	0	0	0
T7	130391	751535	0	0
T8	0	607187	0	0
T12	3410	0	0	0
T13	1099	0	0	0
T16	1763	0	0	0
T19	0	296	0	0
T20	0	696	0	0
T24	0	67	0	0
T30	469357	1659	0	0
T38	0	7	0	0
T40	0	26805	0	0
T44	0	1824	0	0
T54	144466	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	100278794	0	0
T3	196480	75031	0	0
T4	1266	0	0	0
T5	172027	0	0	0
T6	419113	0	0	0
T7	130391	151027	0	0
T8	0	130315	0	0
T12	3410	0	0	0
T13	1099	0	0	0
T16	1763	0	0	0
T22	0	103559	0	0
T30	469357	78058	0	0
T38	0	4	0	0
T40	0	10042	0	0
T44	0	30617	0	0
T54	144466	48345	0	0
T61	0	111314	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	94270103	0	0
T3	196480	70548	0	0
T4	1266	0	0	0
T5	172027	0	0	0
T6	419113	0	0	0
T7	130391	25251	0	0
T8	0	19291	0	0
T12	3410	0	0	0
T13	1099	0	0	0
T16	1763	0	0	0
T22	0	103559	0	0
T30	469357	78058	0	0
T38	0	4	0	0
T40	0	9213	0	0
T44	0	30617	0	0
T54	144466	48345	0	0
T61	0	111314	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	94270103	0	0
T3	196480	70548	0	0
T4	1266	0	0	0
T5	172027	0	0	0
T6	419113	0	0	0
T7	130391	25251	0	0
T8	0	19291	0	0
T12	3410	0	0	0
T13	1099	0	0	0
T16	1763	0	0	0
T22	0	103559	0	0
T30	469357	78058	0	0
T38	0	4	0	0
T40	0	9213	0	0
T44	0	30617	0	0
T54	144466	48345	0	0
T61	0	111314	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	100278794	0	0
T3	196480	75031	0	0
T4	1266	0	0	0
T5	172027	0	0	0
T6	419113	0	0	0
T7	130391	151027	0	0
T8	0	130315	0	0
T12	3410	0	0	0
T13	1099	0	0	0
T16	1763	0	0	0
T22	0	103559	0	0
T30	469357	78058	0	0
T38	0	4	0	0
T40	0	10042	0	0
T44	0	30617	0	0
T54	144466	48345	0	0
T61	0	111314	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	407274474	0	0
T1	250873	250696	0	0
T2	1518	1453	0	0
T3	196480	196381	0	0
T4	1266	1183	0	0
T5	172027	171936	0	0
T6	419113	399944	0	0
T7	130391	130376	0	0
T12	3410	2762	0	0
T13	1099	847	0	0
T16	1763	1713	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T30
1	0	Covered	T3,T7,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T7,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T7,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T3,T7,T30
1	1	Covered	T3,T7,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T3,T7,T30

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T7,T8
1	1	Covered	T3,T7,T30

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T7,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T7,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	408132832	407274474	0	0
CheckNGreaterZero_A	1041	1041	0	0
GntImpliesReady_A	408132832	94270152	0	0
GntImpliesValid_A	408132832	94270152	0	0
GrantKnown_A	408132832	407274474	0	0
IdxKnown_A	408132832	407274474	0	0
IndexIsCorrect_A	408132832	94270152	0	0
NoReadyValidNoGrant_A	408132832	41614940	0	0
Priority_A	408132832	100278877	0	0
ReadyAndValidImplyGrant_A	408132832	94270152	0	0
ReqAndReadyImplyGrant_A	408132832	94270152	0	0
ReqImpliesValid_A	408132832	100278877	0	0
ValidKnown_A	408132832	407274474	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	407274474	0	0
T1	250873	250696	0	0
T2	1518	1453	0	0
T3	196480	196381	0	0
T4	1266	1183	0	0
T5	172027	171936	0	0
T6	419113	399944	0	0
T7	130391	130376	0	0
T12	3410	2762	0	0
T13	1099	847	0	0
T16	1763	1713	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1041	1041	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	94270152	0	0
T3	196480	70548	0	0
T4	1266	0	0	0
T5	172027	0	0	0
T6	419113	0	0	0
T7	130391	25251	0	0
T8	0	19291	0	0
T12	3410	0	0	0
T13	1099	0	0	0
T16	1763	0	0	0
T22	0	103559	0	0
T30	469357	78058	0	0
T38	0	4	0	0
T40	0	9213	0	0
T44	0	30617	0	0
T54	144466	48345	0	0
T61	0	111314	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	94270152	0	0
T3	196480	70548	0	0
T4	1266	0	0	0
T5	172027	0	0	0
T6	419113	0	0	0
T7	130391	25251	0	0
T8	0	19291	0	0
T12	3410	0	0	0
T13	1099	0	0	0
T16	1763	0	0	0
T22	0	103559	0	0
T30	469357	78058	0	0
T38	0	4	0	0
T40	0	9213	0	0
T44	0	30617	0	0
T54	144466	48345	0	0
T61	0	111314	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	407274474	0	0
T1	250873	250696	0	0
T2	1518	1453	0	0
T3	196480	196381	0	0
T4	1266	1183	0	0
T5	172027	171936	0	0
T6	419113	399944	0	0
T7	130391	130376	0	0
T12	3410	2762	0	0
T13	1099	847	0	0
T16	1763	1713	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	407274474	0	0
T1	250873	250696	0	0
T2	1518	1453	0	0
T3	196480	196381	0	0
T4	1266	1183	0	0
T5	172027	171936	0	0
T6	419113	399944	0	0
T7	130391	130376	0	0
T12	3410	2762	0	0
T13	1099	847	0	0
T16	1763	1713	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	94270152	0	0
T3	196480	70548	0	0
T4	1266	0	0	0
T5	172027	0	0	0
T6	419113	0	0	0
T7	130391	25251	0	0
T8	0	19291	0	0
T12	3410	0	0	0
T13	1099	0	0	0
T16	1763	0	0	0
T22	0	103559	0	0
T30	469357	78058	0	0
T38	0	4	0	0
T40	0	9213	0	0
T44	0	30617	0	0
T54	144466	48345	0	0
T61	0	111314	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	41614940	0	0
T3	196480	13571	0	0
T4	1266	0	0	0
T5	172027	0	0	0
T6	419113	0	0	0
T7	130391	751535	0	0
T8	0	607187	0	0
T12	3410	0	0	0
T13	1099	0	0	0
T16	1763	0	0	0
T19	0	296	0	0
T20	0	696	0	0
T24	0	67	0	0
T30	469357	1659	0	0
T38	0	7	0	0
T40	0	26805	0	0
T44	0	1824	0	0
T54	144466	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	100278877	0	0
T3	196480	75031	0	0
T4	1266	0	0	0
T5	172027	0	0	0
T6	419113	0	0	0
T7	130391	151027	0	0
T8	0	130315	0	0
T12	3410	0	0	0
T13	1099	0	0	0
T16	1763	0	0	0
T22	0	103559	0	0
T30	469357	78058	0	0
T38	0	4	0	0
T40	0	10042	0	0
T44	0	30617	0	0
T54	144466	48345	0	0
T61	0	111314	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	94270152	0	0
T3	196480	70548	0	0
T4	1266	0	0	0
T5	172027	0	0	0
T6	419113	0	0	0
T7	130391	25251	0	0
T8	0	19291	0	0
T12	3410	0	0	0
T13	1099	0	0	0
T16	1763	0	0	0
T22	0	103559	0	0
T30	469357	78058	0	0
T38	0	4	0	0
T40	0	9213	0	0
T44	0	30617	0	0
T54	144466	48345	0	0
T61	0	111314	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	94270152	0	0
T3	196480	70548	0	0
T4	1266	0	0	0
T5	172027	0	0	0
T6	419113	0	0	0
T7	130391	25251	0	0
T8	0	19291	0	0
T12	3410	0	0	0
T13	1099	0	0	0
T16	1763	0	0	0
T22	0	103559	0	0
T30	469357	78058	0	0
T38	0	4	0	0
T40	0	9213	0	0
T44	0	30617	0	0
T54	144466	48345	0	0
T61	0	111314	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	100278877	0	0
T3	196480	75031	0	0
T4	1266	0	0	0
T5	172027	0	0	0
T6	419113	0	0	0
T7	130391	151027	0	0
T8	0	130315	0	0
T12	3410	0	0	0
T13	1099	0	0	0
T16	1763	0	0	0
T22	0	103559	0	0
T30	469357	78058	0	0
T38	0	4	0	0
T40	0	10042	0	0
T44	0	30617	0	0
T54	144466	48345	0	0
T61	0	111314	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408132832	407274474	0	0
T1	250873	250696	0	0
T2	1518	1453	0	0
T3	196480	196381	0	0
T4	1266	1183	0	0
T5	172027	171936	0	0
T6	419113	399944	0	0
T7	130391	130376	0	0
T12	3410	2762	0	0
T13	1099	847	0	0
T16	1763	1713	0	0