Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	91.67	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.67	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	2	14	87.50

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	2	14	87.50	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	20287	1		T104	395		T105	20		T106	491
full_word	3773933	1		T3	514		T4	6		T7	16477

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3793949	1		T3	514		T4	6		T7	16477
auto[TlIntgErrCmd]	82	1		T204	6		T205	2		T243	2
auto[TlIntgErrData]	97	1		T204	7		T205	1		T243	1
auto[TlIntgErrBoth]	92	1		T204	6		T205	6		T243	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3768356	1		T3	514		T4	6		T7	16477
auto[1]	25864	1		T104	489		T105	31		T106	732

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	2	14	87.50	2

Automatically Generated Cross Bins for cr_all

Element holes

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrCmd]]	[full_word]	*	--	--	2

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1106	1		T104	19		T105	1		T106	38
auto[TlIntgErrNone]	partial	auto[1]	18920	1		T104	376		T105	19		T106	453
auto[TlIntgErrNone]	full_word	auto[0]	3767143	1		T3	514		T4	6		T7	16477
auto[TlIntgErrNone]	full_word	auto[1]	6780	1		T104	113		T105	12		T106	279
auto[TlIntgErrCmd]	partial	auto[0]	26	1		T204	2		T257	2		T280	2
auto[TlIntgErrCmd]	partial	auto[1]	56	1		T204	4		T205	2		T243	2
auto[TlIntgErrData]	partial	auto[0]	41	1		T204	3		T205	1		T243	1
auto[TlIntgErrData]	partial	auto[1]	51	1		T204	3		T257	3		T280	3
auto[TlIntgErrData]	full_word	auto[0]	2	1		T281	1		T383	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1		T204	1		T257	1		T259	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1		T204	2		T205	2		T243	3
auto[TlIntgErrBoth]	partial	auto[1]	52	1		T204	4		T205	4		T243	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T257	1		T384	1		T385	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T382	1		T386	1		-	-

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	24341152	1		T1	6575		T2	34922		T3	1278
full_word	7598762	1		T1	9317		T2	555		T3	3476

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	31939624	1		T1	15892		T2	35477		T3	4754
auto[TlIntgErrCmd]	108	1		T204	4		T205	2		T243	3
auto[TlIntgErrData]	101	1		T204	11		T205	4		T243	4
auto[TlIntgErrBoth]	81	1		T204	5		T205	4		T243	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	27563686	1		T1	12165		T2	35069		T3	1812
auto[1]	4376228	1		T1	3727		T2	408		T3	2942

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	23681010	1		T1	6415		T2	34873		T3	1024
auto[TlIntgErrNone]	partial	auto[1]	659877	1		T1	160		T2	49		T3	254
auto[TlIntgErrNone]	full_word	auto[0]	3882552	1		T1	5750		T2	196		T3	788
auto[TlIntgErrNone]	full_word	auto[1]	3716185	1		T1	3567		T2	359		T3	2688
auto[TlIntgErrCmd]	partial	auto[0]	42	1		T204	1		T205	1		T243	3
auto[TlIntgErrCmd]	partial	auto[1]	59	1		T204	3		T205	1		T257	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T280	1		T281	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T281	1		T258	2		T259	1
auto[TlIntgErrData]	partial	auto[0]	43	1		T204	2		T205	2		T243	2
auto[TlIntgErrData]	partial	auto[1]	44	1		T204	7		T205	2		T243	2
auto[TlIntgErrData]	full_word	auto[0]	5	1		T204	1		T257	1		T280	1
auto[TlIntgErrData]	full_word	auto[1]	9	1		T204	1		T381	1		T382	2
auto[TlIntgErrBoth]	partial	auto[0]	29	1		T204	2		T205	1		T243	1
auto[TlIntgErrBoth]	partial	auto[1]	48	1		T204	3		T205	3		T243	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T243	1		T281	1		T387	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1		T258	1		-	-		-	-