Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1510993544	1507789448	0	0
CheckNGreaterZero_A	4124	4124	0	0
GntImpliesReady_A	1510993544	400462129	0	0
GntImpliesValid_A	1510993544	400462129	0	0
GrantKnown_A	1510993544	1507789448	0	0
IdxKnown_A	1510993544	1507789448	0	0
IndexIsCorrect_A	1510993544	400462129	0	0
NoReadyValidNoGrant_A	1510993544	175709350	0	0
Priority_A	1510993544	424343371	0	0
ReadyAndValidImplyGrant_A	1510993544	400462129	0	0
ReqAndReadyImplyGrant_A	1510993544	400462129	0	0
ReqImpliesValid_A	1510993544	424343371	0	0
ValidKnown_A	1510993544	1507789448	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1510993544	1507789448	0	0
T1	133524	133244	0	0
T2	291780	291540	0	0
T3	59780	59560	0	0
T4	6960	6184	0	0
T5	1920	1580	0	0
T6	443776	443184	0	0
T7	480144	480076	0	0
T18	4180	3916	0	0
T19	846504	846220	0	0
T20	6204	5960	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4124	4124	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1510993544	400462129	0	0
T1	66762	1624	0	0
T2	291780	141386	0	0
T3	59780	2386	0	0
T4	6960	418	0	0
T5	1920	64	0	0
T6	443776	64804	0	0
T7	480144	84836	0	0
T18	4180	64	0	0
T19	846504	286392	0	0
T20	6204	64	0	0
T21	0	236	0	0
T22	0	265848	0	0
T39	4104	0	0	0
T51	0	80918	0	0
T54	0	290	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1510993544	400462129	0	0
T1	66762	1624	0	0
T2	291780	141386	0	0
T3	59780	2386	0	0
T4	6960	418	0	0
T5	1920	64	0	0
T6	443776	64804	0	0
T7	480144	84836	0	0
T18	4180	64	0	0
T19	846504	286392	0	0
T20	6204	64	0	0
T21	0	236	0	0
T22	0	265848	0	0
T39	4104	0	0	0
T51	0	80918	0	0
T54	0	290	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1510993544	1507789448	0	0
T1	133524	133244	0	0
T2	291780	291540	0	0
T3	59780	59560	0	0
T4	6960	6184	0	0
T5	1920	1580	0	0
T6	443776	443184	0	0
T7	480144	480076	0	0
T18	4180	3916	0	0
T19	846504	846220	0	0
T20	6204	5960	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1510993544	1507789448	0	0
T1	133524	133244	0	0
T2	291780	291540	0	0
T3	59780	59560	0	0
T4	6960	6184	0	0
T5	1920	1580	0	0
T6	443776	443184	0	0
T7	480144	480076	0	0
T18	4180	3916	0	0
T19	846504	846220	0	0
T20	6204	5960	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1510993544	400462129	0	0
T1	66762	1624	0	0
T2	291780	141386	0	0
T3	59780	2386	0	0
T4	6960	418	0	0
T5	1920	64	0	0
T6	443776	64804	0	0
T7	480144	84836	0	0
T18	4180	64	0	0
T19	846504	286392	0	0
T20	6204	64	0	0
T21	0	236	0	0
T22	0	265848	0	0
T39	4104	0	0	0
T51	0	80918	0	0
T54	0	290	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1510993544	175709350	0	0
T1	66762	256	0	0
T2	291780	804	0	0
T3	59780	3708	0	0
T4	6960	920	0	0
T5	1920	256	0	0
T6	443776	178378	0	0
T7	480144	2589986	0	0
T15	0	1648	0	0
T18	4180	256	0	0
T19	846504	127900	0	0
T20	6204	256	0	0
T21	0	18	0	0
T22	0	548	0	0
T39	4104	0	0	0
T51	0	64826	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1510993544	424343371	0	0
T1	66762	1624	0	0
T2	291780	141386	0	0
T3	59780	2388	0	0
T4	6960	418	0	0
T5	1920	64	0	0
T6	443776	69000	0	0
T7	480144	588408	0	0
T18	4180	64	0	0
T19	846504	322670	0	0
T20	6204	64	0	0
T21	0	236	0	0
T22	0	265848	0	0
T39	4104	0	0	0
T51	0	93346	0	0
T54	0	300	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1510993544	400462129	0	0
T1	66762	1624	0	0
T2	291780	141386	0	0
T3	59780	2386	0	0
T4	6960	418	0	0
T5	1920	64	0	0
T6	443776	64804	0	0
T7	480144	84836	0	0
T18	4180	64	0	0
T19	846504	286392	0	0
T20	6204	64	0	0
T21	0	236	0	0
T22	0	265848	0	0
T39	4104	0	0	0
T51	0	80918	0	0
T54	0	290	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1510993544	400462129	0	0
T1	66762	1624	0	0
T2	291780	141386	0	0
T3	59780	2386	0	0
T4	6960	418	0	0
T5	1920	64	0	0
T6	443776	64804	0	0
T7	480144	84836	0	0
T18	4180	64	0	0
T19	846504	286392	0	0
T20	6204	64	0	0
T21	0	236	0	0
T22	0	265848	0	0
T39	4104	0	0	0
T51	0	80918	0	0
T54	0	290	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1510993544	424343371	0	0
T1	66762	1624	0	0
T2	291780	141386	0	0
T3	59780	2388	0	0
T4	6960	418	0	0
T5	1920	64	0	0
T6	443776	69000	0	0
T7	480144	588408	0	0
T18	4180	64	0	0
T19	846504	322670	0	0
T20	6204	64	0	0
T21	0	236	0	0
T22	0	265848	0	0
T39	4104	0	0	0
T51	0	93346	0	0
T54	0	300	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1510993544	1507789448	0	0
T1	133524	133244	0	0
T2	291780	291540	0	0
T3	59780	59560	0	0
T4	6960	6184	0	0
T5	1920	1580	0	0
T6	443776	443184	0	0
T7	480144	480076	0	0
T18	4180	3916	0	0
T19	846504	846220	0	0
T20	6204	5960	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	377748386	376947362	0	0
CheckNGreaterZero_A	1031	1031	0	0
GntImpliesReady_A	377748386	102000992	0	0
GntImpliesValid_A	377748386	102000992	0	0
GrantKnown_A	377748386	376947362	0	0
IdxKnown_A	377748386	376947362	0	0
IndexIsCorrect_A	377748386	102000992	0	0
NoReadyValidNoGrant_A	377748386	45450379	0	0
Priority_A	377748386	107999142	0	0
ReadyAndValidImplyGrant_A	377748386	102000992	0	0
ReqAndReadyImplyGrant_A	377748386	102000992	0	0
ReqImpliesValid_A	377748386	107999142	0	0
ValidKnown_A	377748386	376947362	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	376947362	0	0
T1	33381	33311	0	0
T2	72945	72885	0	0
T3	14945	14890	0	0
T4	1740	1546	0	0
T5	480	395	0	0
T6	110944	110796	0	0
T7	120036	120019	0	0
T18	1045	979	0	0
T19	211626	211555	0	0
T20	1551	1490	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1031	1031	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	102000992	0	0
T1	33381	812	0	0
T2	72945	68300	0	0
T3	14945	574	0	0
T4	1740	186	0	0
T5	480	32	0	0
T6	110944	16824	0	0
T7	120036	23277	0	0
T18	1045	32	0	0
T19	211626	81680	0	0
T20	1551	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	102000992	0	0
T1	33381	812	0	0
T2	72945	68300	0	0
T3	14945	574	0	0
T4	1740	186	0	0
T5	480	32	0	0
T6	110944	16824	0	0
T7	120036	23277	0	0
T18	1045	32	0	0
T19	211626	81680	0	0
T20	1551	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	376947362	0	0
T1	33381	33311	0	0
T2	72945	72885	0	0
T3	14945	14890	0	0
T4	1740	1546	0	0
T5	480	395	0	0
T6	110944	110796	0	0
T7	120036	120019	0	0
T18	1045	979	0	0
T19	211626	211555	0	0
T20	1551	1490	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	376947362	0	0
T1	33381	33311	0	0
T2	72945	72885	0	0
T3	14945	14890	0	0
T4	1740	1546	0	0
T5	480	395	0	0
T6	110944	110796	0	0
T7	120036	120019	0	0
T18	1045	979	0	0
T19	211626	211555	0	0
T20	1551	1490	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	102000992	0	0
T1	33381	812	0	0
T2	72945	68300	0	0
T3	14945	574	0	0
T4	1740	186	0	0
T5	480	32	0	0
T6	110944	16824	0	0
T7	120036	23277	0	0
T18	1045	32	0	0
T19	211626	81680	0	0
T20	1551	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	45450379	0	0
T1	33381	128	0	0
T2	72945	261	0	0
T3	14945	928	0	0
T4	1740	401	0	0
T5	480	128	0	0
T6	110944	46316	0	0
T7	120036	696643	0	0
T18	1045	128	0	0
T19	211626	31681	0	0
T20	1551	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	107999142	0	0
T1	33381	812	0	0
T2	72945	68300	0	0
T3	14945	575	0	0
T4	1740	186	0	0
T5	480	32	0	0
T6	110944	17843	0	0
T7	120036	179580	0	0
T18	1045	32	0	0
T19	211626	91412	0	0
T20	1551	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	102000992	0	0
T1	33381	812	0	0
T2	72945	68300	0	0
T3	14945	574	0	0
T4	1740	186	0	0
T5	480	32	0	0
T6	110944	16824	0	0
T7	120036	23277	0	0
T18	1045	32	0	0
T19	211626	81680	0	0
T20	1551	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	102000992	0	0
T1	33381	812	0	0
T2	72945	68300	0	0
T3	14945	574	0	0
T4	1740	186	0	0
T5	480	32	0	0
T6	110944	16824	0	0
T7	120036	23277	0	0
T18	1045	32	0	0
T19	211626	81680	0	0
T20	1551	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	107999142	0	0
T1	33381	812	0	0
T2	72945	68300	0	0
T3	14945	575	0	0
T4	1740	186	0	0
T5	480	32	0	0
T6	110944	17843	0	0
T7	120036	179580	0	0
T18	1045	32	0	0
T19	211626	91412	0	0
T20	1551	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	376947362	0	0
T1	33381	33311	0	0
T2	72945	72885	0	0
T3	14945	14890	0	0
T4	1740	1546	0	0
T5	480	395	0	0
T6	110944	110796	0	0
T7	120036	120019	0	0
T18	1045	979	0	0
T19	211626	211555	0	0
T20	1551	1490	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	377748386	376947362	0	0
CheckNGreaterZero_A	1031	1031	0	0
GntImpliesReady_A	377748386	102001004	0	0
GntImpliesValid_A	377748386	102001004	0	0
GrantKnown_A	377748386	376947362	0	0
IdxKnown_A	377748386	376947362	0	0
IndexIsCorrect_A	377748386	102001004	0	0
NoReadyValidNoGrant_A	377748386	45450261	0	0
Priority_A	377748386	107999272	0	0
ReadyAndValidImplyGrant_A	377748386	102001004	0	0
ReqAndReadyImplyGrant_A	377748386	102001004	0	0
ReqImpliesValid_A	377748386	107999272	0	0
ValidKnown_A	377748386	376947362	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	376947362	0	0
T1	33381	33311	0	0
T2	72945	72885	0	0
T3	14945	14890	0	0
T4	1740	1546	0	0
T5	480	395	0	0
T6	110944	110796	0	0
T7	120036	120019	0	0
T18	1045	979	0	0
T19	211626	211555	0	0
T20	1551	1490	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1031	1031	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	102001004	0	0
T1	33381	812	0	0
T2	72945	68300	0	0
T3	14945	574	0	0
T4	1740	186	0	0
T5	480	32	0	0
T6	110944	16824	0	0
T7	120036	23277	0	0
T18	1045	32	0	0
T19	211626	81680	0	0
T20	1551	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	102001004	0	0
T1	33381	812	0	0
T2	72945	68300	0	0
T3	14945	574	0	0
T4	1740	186	0	0
T5	480	32	0	0
T6	110944	16824	0	0
T7	120036	23277	0	0
T18	1045	32	0	0
T19	211626	81680	0	0
T20	1551	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	376947362	0	0
T1	33381	33311	0	0
T2	72945	72885	0	0
T3	14945	14890	0	0
T4	1740	1546	0	0
T5	480	395	0	0
T6	110944	110796	0	0
T7	120036	120019	0	0
T18	1045	979	0	0
T19	211626	211555	0	0
T20	1551	1490	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	376947362	0	0
T1	33381	33311	0	0
T2	72945	72885	0	0
T3	14945	14890	0	0
T4	1740	1546	0	0
T5	480	395	0	0
T6	110944	110796	0	0
T7	120036	120019	0	0
T18	1045	979	0	0
T19	211626	211555	0	0
T20	1551	1490	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	102001004	0	0
T1	33381	812	0	0
T2	72945	68300	0	0
T3	14945	574	0	0
T4	1740	186	0	0
T5	480	32	0	0
T6	110944	16824	0	0
T7	120036	23277	0	0
T18	1045	32	0	0
T19	211626	81680	0	0
T20	1551	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	45450261	0	0
T1	33381	128	0	0
T2	72945	261	0	0
T3	14945	928	0	0
T4	1740	401	0	0
T5	480	128	0	0
T6	110944	46316	0	0
T7	120036	696643	0	0
T18	1045	128	0	0
T19	211626	31681	0	0
T20	1551	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	107999272	0	0
T1	33381	812	0	0
T2	72945	68300	0	0
T3	14945	575	0	0
T4	1740	186	0	0
T5	480	32	0	0
T6	110944	17843	0	0
T7	120036	179580	0	0
T18	1045	32	0	0
T19	211626	91412	0	0
T20	1551	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	102001004	0	0
T1	33381	812	0	0
T2	72945	68300	0	0
T3	14945	574	0	0
T4	1740	186	0	0
T5	480	32	0	0
T6	110944	16824	0	0
T7	120036	23277	0	0
T18	1045	32	0	0
T19	211626	81680	0	0
T20	1551	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	102001004	0	0
T1	33381	812	0	0
T2	72945	68300	0	0
T3	14945	574	0	0
T4	1740	186	0	0
T5	480	32	0	0
T6	110944	16824	0	0
T7	120036	23277	0	0
T18	1045	32	0	0
T19	211626	81680	0	0
T20	1551	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	107999272	0	0
T1	33381	812	0	0
T2	72945	68300	0	0
T3	14945	575	0	0
T4	1740	186	0	0
T5	480	32	0	0
T6	110944	17843	0	0
T7	120036	179580	0	0
T18	1045	32	0	0
T19	211626	91412	0	0
T20	1551	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	376947362	0	0
T1	33381	33311	0	0
T2	72945	72885	0	0
T3	14945	14890	0	0
T4	1740	1546	0	0
T5	480	395	0	0
T6	110944	110796	0	0
T7	120036	120019	0	0
T18	1045	979	0	0
T19	211626	211555	0	0
T20	1551	1490	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T3,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T2,T3,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T7
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	377748386	376947362	0	0
CheckNGreaterZero_A	1031	1031	0	0
GntImpliesReady_A	377748386	98230076	0	0
GntImpliesValid_A	377748386	98230076	0	0
GrantKnown_A	377748386	376947362	0	0
IdxKnown_A	377748386	376947362	0	0
IndexIsCorrect_A	377748386	98230076	0	0
NoReadyValidNoGrant_A	377748386	42404359	0	0
Priority_A	377748386	104172484	0	0
ReadyAndValidImplyGrant_A	377748386	98230076	0	0
ReqAndReadyImplyGrant_A	377748386	98230076	0	0
ReqImpliesValid_A	377748386	104172484	0	0
ValidKnown_A	377748386	376947362	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	376947362	0	0
T1	33381	33311	0	0
T2	72945	72885	0	0
T3	14945	14890	0	0
T4	1740	1546	0	0
T5	480	395	0	0
T6	110944	110796	0	0
T7	120036	120019	0	0
T18	1045	979	0	0
T19	211626	211555	0	0
T20	1551	1490	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1031	1031	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	98230076	0	0
T2	72945	2393	0	0
T3	14945	619	0	0
T4	1740	23	0	0
T5	480	0	0	0
T6	110944	15578	0	0
T7	120036	19141	0	0
T18	1045	0	0	0
T19	211626	61516	0	0
T20	1551	0	0	0
T21	0	118	0	0
T22	0	132924	0	0
T39	2052	0	0	0
T51	0	40459	0	0
T54	0	145	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	98230076	0	0
T2	72945	2393	0	0
T3	14945	619	0	0
T4	1740	23	0	0
T5	480	0	0	0
T6	110944	15578	0	0
T7	120036	19141	0	0
T18	1045	0	0	0
T19	211626	61516	0	0
T20	1551	0	0	0
T21	0	118	0	0
T22	0	132924	0	0
T39	2052	0	0	0
T51	0	40459	0	0
T54	0	145	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	376947362	0	0
T1	33381	33311	0	0
T2	72945	72885	0	0
T3	14945	14890	0	0
T4	1740	1546	0	0
T5	480	395	0	0
T6	110944	110796	0	0
T7	120036	120019	0	0
T18	1045	979	0	0
T19	211626	211555	0	0
T20	1551	1490	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	376947362	0	0
T1	33381	33311	0	0
T2	72945	72885	0	0
T3	14945	14890	0	0
T4	1740	1546	0	0
T5	480	395	0	0
T6	110944	110796	0	0
T7	120036	120019	0	0
T18	1045	979	0	0
T19	211626	211555	0	0
T20	1551	1490	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	98230076	0	0
T2	72945	2393	0	0
T3	14945	619	0	0
T4	1740	23	0	0
T5	480	0	0	0
T6	110944	15578	0	0
T7	120036	19141	0	0
T18	1045	0	0	0
T19	211626	61516	0	0
T20	1551	0	0	0
T21	0	118	0	0
T22	0	132924	0	0
T39	2052	0	0	0
T51	0	40459	0	0
T54	0	145	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	42404359	0	0
T2	72945	141	0	0
T3	14945	926	0	0
T4	1740	59	0	0
T5	480	0	0	0
T6	110944	42873	0	0
T7	120036	598350	0	0
T15	0	824	0	0
T18	1045	0	0	0
T19	211626	32269	0	0
T20	1551	0	0	0
T21	0	9	0	0
T22	0	274	0	0
T39	2052	0	0	0
T51	0	32413	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	104172484	0	0
T2	72945	2393	0	0
T3	14945	619	0	0
T4	1740	23	0	0
T5	480	0	0	0
T6	110944	16657	0	0
T7	120036	114624	0	0
T18	1045	0	0	0
T19	211626	69923	0	0
T20	1551	0	0	0
T21	0	118	0	0
T22	0	132924	0	0
T39	2052	0	0	0
T51	0	46673	0	0
T54	0	150	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	98230076	0	0
T2	72945	2393	0	0
T3	14945	619	0	0
T4	1740	23	0	0
T5	480	0	0	0
T6	110944	15578	0	0
T7	120036	19141	0	0
T18	1045	0	0	0
T19	211626	61516	0	0
T20	1551	0	0	0
T21	0	118	0	0
T22	0	132924	0	0
T39	2052	0	0	0
T51	0	40459	0	0
T54	0	145	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	98230076	0	0
T2	72945	2393	0	0
T3	14945	619	0	0
T4	1740	23	0	0
T5	480	0	0	0
T6	110944	15578	0	0
T7	120036	19141	0	0
T18	1045	0	0	0
T19	211626	61516	0	0
T20	1551	0	0	0
T21	0	118	0	0
T22	0	132924	0	0
T39	2052	0	0	0
T51	0	40459	0	0
T54	0	145	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	104172484	0	0
T2	72945	2393	0	0
T3	14945	619	0	0
T4	1740	23	0	0
T5	480	0	0	0
T6	110944	16657	0	0
T7	120036	114624	0	0
T18	1045	0	0	0
T19	211626	69923	0	0
T20	1551	0	0	0
T21	0	118	0	0
T22	0	132924	0	0
T39	2052	0	0	0
T51	0	46673	0	0
T54	0	150	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	376947362	0	0
T1	33381	33311	0	0
T2	72945	72885	0	0
T3	14945	14890	0	0
T4	1740	1546	0	0
T5	480	395	0	0
T6	110944	110796	0	0
T7	120036	120019	0	0
T18	1045	979	0	0
T19	211626	211555	0	0
T20	1551	1490	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T3,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T2,T3,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T7
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	377748386	376947362	0	0
CheckNGreaterZero_A	1031	1031	0	0
GntImpliesReady_A	377748386	98230057	0	0
GntImpliesValid_A	377748386	98230057	0	0
GrantKnown_A	377748386	376947362	0	0
IdxKnown_A	377748386	376947362	0	0
IndexIsCorrect_A	377748386	98230057	0	0
NoReadyValidNoGrant_A	377748386	42404351	0	0
Priority_A	377748386	104172473	0	0
ReadyAndValidImplyGrant_A	377748386	98230057	0	0
ReqAndReadyImplyGrant_A	377748386	98230057	0	0
ReqImpliesValid_A	377748386	104172473	0	0
ValidKnown_A	377748386	376947362	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	376947362	0	0
T1	33381	33311	0	0
T2	72945	72885	0	0
T3	14945	14890	0	0
T4	1740	1546	0	0
T5	480	395	0	0
T6	110944	110796	0	0
T7	120036	120019	0	0
T18	1045	979	0	0
T19	211626	211555	0	0
T20	1551	1490	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1031	1031	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	98230057	0	0
T2	72945	2393	0	0
T3	14945	619	0	0
T4	1740	23	0	0
T5	480	0	0	0
T6	110944	15578	0	0
T7	120036	19141	0	0
T18	1045	0	0	0
T19	211626	61516	0	0
T20	1551	0	0	0
T21	0	118	0	0
T22	0	132924	0	0
T39	2052	0	0	0
T51	0	40459	0	0
T54	0	145	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	98230057	0	0
T2	72945	2393	0	0
T3	14945	619	0	0
T4	1740	23	0	0
T5	480	0	0	0
T6	110944	15578	0	0
T7	120036	19141	0	0
T18	1045	0	0	0
T19	211626	61516	0	0
T20	1551	0	0	0
T21	0	118	0	0
T22	0	132924	0	0
T39	2052	0	0	0
T51	0	40459	0	0
T54	0	145	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	376947362	0	0
T1	33381	33311	0	0
T2	72945	72885	0	0
T3	14945	14890	0	0
T4	1740	1546	0	0
T5	480	395	0	0
T6	110944	110796	0	0
T7	120036	120019	0	0
T18	1045	979	0	0
T19	211626	211555	0	0
T20	1551	1490	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	376947362	0	0
T1	33381	33311	0	0
T2	72945	72885	0	0
T3	14945	14890	0	0
T4	1740	1546	0	0
T5	480	395	0	0
T6	110944	110796	0	0
T7	120036	120019	0	0
T18	1045	979	0	0
T19	211626	211555	0	0
T20	1551	1490	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	98230057	0	0
T2	72945	2393	0	0
T3	14945	619	0	0
T4	1740	23	0	0
T5	480	0	0	0
T6	110944	15578	0	0
T7	120036	19141	0	0
T18	1045	0	0	0
T19	211626	61516	0	0
T20	1551	0	0	0
T21	0	118	0	0
T22	0	132924	0	0
T39	2052	0	0	0
T51	0	40459	0	0
T54	0	145	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	42404351	0	0
T2	72945	141	0	0
T3	14945	926	0	0
T4	1740	59	0	0
T5	480	0	0	0
T6	110944	42873	0	0
T7	120036	598350	0	0
T15	0	824	0	0
T18	1045	0	0	0
T19	211626	32269	0	0
T20	1551	0	0	0
T21	0	9	0	0
T22	0	274	0	0
T39	2052	0	0	0
T51	0	32413	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	104172473	0	0
T2	72945	2393	0	0
T3	14945	619	0	0
T4	1740	23	0	0
T5	480	0	0	0
T6	110944	16657	0	0
T7	120036	114624	0	0
T18	1045	0	0	0
T19	211626	69923	0	0
T20	1551	0	0	0
T21	0	118	0	0
T22	0	132924	0	0
T39	2052	0	0	0
T51	0	46673	0	0
T54	0	150	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	98230057	0	0
T2	72945	2393	0	0
T3	14945	619	0	0
T4	1740	23	0	0
T5	480	0	0	0
T6	110944	15578	0	0
T7	120036	19141	0	0
T18	1045	0	0	0
T19	211626	61516	0	0
T20	1551	0	0	0
T21	0	118	0	0
T22	0	132924	0	0
T39	2052	0	0	0
T51	0	40459	0	0
T54	0	145	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	98230057	0	0
T2	72945	2393	0	0
T3	14945	619	0	0
T4	1740	23	0	0
T5	480	0	0	0
T6	110944	15578	0	0
T7	120036	19141	0	0
T18	1045	0	0	0
T19	211626	61516	0	0
T20	1551	0	0	0
T21	0	118	0	0
T22	0	132924	0	0
T39	2052	0	0	0
T51	0	40459	0	0
T54	0	145	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	104172473	0	0
T2	72945	2393	0	0
T3	14945	619	0	0
T4	1740	23	0	0
T5	480	0	0	0
T6	110944	16657	0	0
T7	120036	114624	0	0
T18	1045	0	0	0
T19	211626	69923	0	0
T20	1551	0	0	0
T21	0	118	0	0
T22	0	132924	0	0
T39	2052	0	0	0
T51	0	46673	0	0
T54	0	150	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377748386	376947362	0	0
T1	33381	33311	0	0
T2	72945	72885	0	0
T3	14945	14890	0	0
T4	1740	1546	0	0
T5	480	395	0	0
T6	110944	110796	0	0
T7	120036	120019	0	0
T18	1045	979	0	0
T19	211626	211555	0	0
T20	1551	1490	0	0