Unified Coverage Report :: Module :: flash_ctrl_core_csr_assert_fpv

Module : flash_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_flash_ctrl_csr_assert_0/flash_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.flash_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.flash_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.69	97.12	93.60	98.44		100.00	84.29	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : flash_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	87	87	100.00	87	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	87	87	100.00	87	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	380020284	4428	0	0
addr_rd_A	380020284	1518	0	0
bank0_info0_page_cfg_0_rd_A	380020284	2818	0	0
bank0_info0_page_cfg_1_rd_A	380020284	2625	0	0
bank0_info0_page_cfg_2_rd_A	380020284	2848	0	0
bank0_info0_page_cfg_3_rd_A	380020284	3132	0	0
bank0_info0_page_cfg_4_rd_A	380020284	3376	0	0
bank0_info0_page_cfg_5_rd_A	380020284	2976	0	0
bank0_info0_page_cfg_6_rd_A	380020284	2468	0	0
bank0_info0_page_cfg_7_rd_A	380020284	2837	0	0
bank0_info0_page_cfg_8_rd_A	380020284	3062	0	0
bank0_info0_page_cfg_9_rd_A	380020284	2257	0	0
bank0_info0_regwen_0_rd_A	380020284	925	0	0
bank0_info0_regwen_1_rd_A	380020284	1330	0	0
bank0_info0_regwen_2_rd_A	380020284	1473	0	0
bank0_info0_regwen_3_rd_A	380020284	1458	0	0
bank0_info0_regwen_4_rd_A	380020284	1206	0	0
bank0_info0_regwen_5_rd_A	380020284	1217	0	0
bank0_info0_regwen_6_rd_A	380020284	1295	0	0
bank0_info0_regwen_7_rd_A	380020284	1476	0	0
bank0_info0_regwen_8_rd_A	380020284	921	0	0
bank0_info0_regwen_9_rd_A	380020284	1161	0	0
bank0_info1_page_cfg_rd_A	380020284	2811	0	0
bank0_info1_regwen_rd_A	380020284	1223	0	0
bank0_info2_page_cfg_0_rd_A	380020284	3120	0	0
bank0_info2_page_cfg_1_rd_A	380020284	2665	0	0
bank0_info2_regwen_0_rd_A	380020284	1216	0	0
bank0_info2_regwen_1_rd_A	380020284	1636	0	0
bank1_info0_page_cfg_0_rd_A	380020284	2970	0	0
bank1_info0_page_cfg_1_rd_A	380020284	2938	0	0
bank1_info0_page_cfg_2_rd_A	380020284	2950	0	0
bank1_info0_page_cfg_3_rd_A	380020284	2891	0	0
bank1_info0_page_cfg_4_rd_A	380020284	2937	0	0
bank1_info0_page_cfg_5_rd_A	380020284	2655	0	0
bank1_info0_page_cfg_6_rd_A	380020284	2723	0	0
bank1_info0_page_cfg_7_rd_A	380020284	2913	0	0
bank1_info0_page_cfg_8_rd_A	380020284	2919	0	0
bank1_info0_page_cfg_9_rd_A	380020284	3071	0	0
bank1_info0_regwen_0_rd_A	380020284	1494	0	0
bank1_info0_regwen_1_rd_A	380020284	1265	0	0
bank1_info0_regwen_2_rd_A	380020284	1541	0	0
bank1_info0_regwen_3_rd_A	380020284	1435	0	0
bank1_info0_regwen_4_rd_A	380020284	1405	0	0
bank1_info0_regwen_5_rd_A	380020284	690	0	0
bank1_info0_regwen_6_rd_A	380020284	1249	0	0
bank1_info0_regwen_7_rd_A	380020284	1446	0	0
bank1_info0_regwen_8_rd_A	380020284	1080	0	0
bank1_info0_regwen_9_rd_A	380020284	900	0	0
bank1_info1_page_cfg_rd_A	380020284	3006	0	0
bank1_info1_regwen_rd_A	380020284	1163	0	0
bank1_info2_page_cfg_0_rd_A	380020284	2579	0	0
bank1_info2_page_cfg_1_rd_A	380020284	2855	0	0
bank1_info2_regwen_0_rd_A	380020284	1261	0	0
bank1_info2_regwen_1_rd_A	380020284	1518	0	0
bank_cfg_regwen_rd_A	380020284	1154	0	0
default_region_rd_A	380020284	2396	0	0
exec_rd_A	380020284	1311	0	0
fifo_lvl_rd_A	380020284	1554	0	0
fifo_rst_rd_A	380020284	1160	0	0
hw_info_cfg_override_rd_A	380020284	1792	0	0
intr_enable_rd_A	380020284	2562	0	0
mp_region_0_rd_A	380020284	1741	0	0
mp_region_1_rd_A	380020284	1342	0	0
mp_region_2_rd_A	380020284	1557	0	0
mp_region_3_rd_A	380020284	1718	0	0
mp_region_4_rd_A	380020284	1878	0	0
mp_region_5_rd_A	380020284	1512	0	0
mp_region_6_rd_A	380020284	1569	0	0
mp_region_7_rd_A	380020284	1620	0	0
mp_region_cfg_0_rd_A	380020284	2815	0	0
mp_region_cfg_1_rd_A	380020284	2941	0	0
mp_region_cfg_2_rd_A	380020284	2433	0	0
mp_region_cfg_3_rd_A	380020284	2636	0	0
mp_region_cfg_4_rd_A	380020284	2810	0	0
mp_region_cfg_5_rd_A	380020284	2517	0	0
mp_region_cfg_6_rd_A	380020284	2849	0	0
mp_region_cfg_7_rd_A	380020284	2770	0	0
phy_alert_cfg_rd_A	380020284	546	0	0
region_cfg_regwen_0_rd_A	380020284	1471	0	0
region_cfg_regwen_1_rd_A	380020284	1534	0	0
region_cfg_regwen_2_rd_A	380020284	1499	0	0
region_cfg_regwen_3_rd_A	380020284	1437	0	0
region_cfg_regwen_4_rd_A	380020284	1478	0	0
region_cfg_regwen_5_rd_A	380020284	1521	0	0
region_cfg_regwen_6_rd_A	380020284	1555	0	0
region_cfg_regwen_7_rd_A	380020284	1330	0	0
scratch_rd_A	380020284	1384	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	4428	0	0
T104	2452	75	0	0
T105	6123	2	0	0
T106	4252	36	0	0
T107	2397	1	0	0
T203	6218	408	0	0
T204	33582	2	0	0
T223	3389	115	0	0
T224	3188	107	0	0
T225	7651	3	0	0
T226	6041	158	0	0

addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1518	0	0
T66	5110	15	0	0
T105	6123	7	0	0
T227	5540	4	0	0
T236	19868	80	0	0
T237	20013	23	0	0
T247	3187	3	0	0
T278	21218	45	0	0
T279	3463	5	0	0
T280	77892	81	0	0
T281	80406	75	0	0

bank0_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	2818	0	0
T105	6123	7	0	0
T227	5540	36	0	0
T236	19868	61	0	0
T237	20013	31	0	0
T240	3465	7	0	0
T247	3187	1	0	0
T278	21218	24	0	0
T279	3463	25	0	0
T282	3305	4	0	0
T283	4018	25	0	0

bank0_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	2625	0	0
T66	5110	12	0	0
T105	6123	5	0	0
T227	5540	13	0	0
T236	19868	18	0	0
T237	20013	52	0	0
T240	3465	1	0	0
T247	3187	4	0	0
T278	21218	78	0	0
T279	3463	34	0	0
T283	4018	2	0	0

bank0_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	2848	0	0
T66	5110	6	0	0
T105	6123	34	0	0
T227	5540	11	0	0
T236	19868	47	0	0
T237	20013	84	0	0
T240	3465	2	0	0
T247	3187	6	0	0
T278	21218	9	0	0
T282	3305	14	0	0
T283	4018	25	0	0

bank0_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	3132	0	0
T66	5110	9	0	0
T105	6123	39	0	0
T227	5540	11	0	0
T236	19868	50	0	0
T237	20013	26	0	0
T240	3465	8	0	0
T247	3187	6	0	0
T278	21218	24	0	0
T282	3305	15	0	0
T283	4018	25	0	0

bank0_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	3376	0	0
T66	5110	9	0	0
T105	6123	49	0	0
T227	5540	9	0	0
T236	19868	89	0	0
T237	20013	96	0	0
T240	3465	19	0	0
T247	3187	6	0	0
T278	21218	50	0	0
T279	3463	8	0	0
T283	4018	34	0	0

bank0_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	2976	0	0
T66	5110	11	0	0
T105	6123	24	0	0
T227	5540	31	0	0
T236	19868	43	0	0
T237	20013	60	0	0
T247	3187	3	0	0
T278	21218	35	0	0
T279	3463	13	0	0
T280	77892	364	0	0
T283	4018	5	0	0

bank0_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	2468	0	0
T66	5110	5	0	0
T105	6123	37	0	0
T227	5540	29	0	0
T236	19868	14	0	0
T237	20013	65	0	0
T247	3187	6	0	0
T278	21218	66	0	0
T279	3463	37	0	0
T282	3305	21	0	0
T283	4018	3	0	0

bank0_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	2837	0	0
T66	5110	18	0	0
T105	6123	11	0	0
T227	5540	31	0	0
T236	19868	42	0	0
T237	20013	79	0	0
T240	3465	21	0	0
T247	3187	2	0	0
T278	21218	56	0	0
T279	3463	32	0	0
T283	4018	6	0	0

bank0_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	3062	0	0
T66	5110	10	0	0
T105	6123	7	0	0
T227	5540	26	0	0
T236	19868	34	0	0
T237	20013	40	0	0
T240	3465	2	0	0
T247	3187	5	0	0
T278	21218	11	0	0
T282	3305	19	0	0
T283	4018	32	0	0

bank0_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	2257	0	0
T66	5110	8	0	0
T105	6123	36	0	0
T227	5540	15	0	0
T236	19868	25	0	0
T237	20013	69	0	0
T240	3465	6	0	0
T247	3187	5	0	0
T278	21218	65	0	0
T282	3305	10	0	0
T283	4018	2	0	0

bank0_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	925	0	0
T66	5110	5	0	0
T105	6123	10	0	0
T227	5540	8	0	0
T236	19868	50	0	0
T237	20013	13	0	0
T247	3187	5	0	0
T278	21218	58	0	0
T279	3463	8	0	0
T280	77892	84	0	0
T283	4018	1	0	0

bank0_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1330	0	0
T66	5110	7	0	0
T105	6123	11	0	0
T227	5540	11	0	0
T236	19868	67	0	0
T237	20013	52	0	0
T240	3465	3	0	0
T247	3187	4	0	0
T278	21218	58	0	0
T279	3463	7	0	0
T283	4018	2	0	0

bank0_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1473	0	0
T66	5110	9	0	0
T105	6123	4	0	0
T227	5540	14	0	0
T236	19868	16	0	0
T237	20013	34	0	0
T247	3187	8	0	0
T278	21218	26	0	0
T279	3463	5	0	0
T280	77892	72	0	0
T283	4018	8	0	0

bank0_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1458	0	0
T66	5110	4	0	0
T105	6123	15	0	0
T227	5540	6	0	0
T236	19868	16	0	0
T237	20013	37	0	0
T240	3465	8	0	0
T247	3187	5	0	0
T278	21218	17	0	0
T282	3305	10	0	0
T283	4018	7	0	0

bank0_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1206	0	0
T66	5110	4	0	0
T105	6123	10	0	0
T227	5540	4	0	0
T236	19868	33	0	0
T237	20013	28	0	0
T240	3465	4	0	0
T247	3187	5	0	0
T278	21218	64	0	0
T279	3463	5	0	0
T283	4018	4	0	0

bank0_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1217	0	0
T66	5110	13	0	0
T105	6123	7	0	0
T227	5540	8	0	0
T236	19868	45	0	0
T237	20013	23	0	0
T240	3465	5	0	0
T247	3187	1	0	0
T278	21218	49	0	0
T279	3463	1	0	0
T283	4018	6	0	0

bank0_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1295	0	0
T66	5110	5	0	0
T105	6123	6	0	0
T227	5540	6	0	0
T236	19868	11	0	0
T237	20013	80	0	0
T247	3187	8	0	0
T278	21218	21	0	0
T279	3463	2	0	0
T280	77892	84	0	0
T281	80406	106	0	0

bank0_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1476	0	0
T66	5110	7	0	0
T105	6123	16	0	0
T227	5540	7	0	0
T236	19868	25	0	0
T237	20013	44	0	0
T247	3187	10	0	0
T278	21218	29	0	0
T280	77892	78	0	0
T281	80406	79	0	0
T283	4018	4	0	0

bank0_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	921	0	0
T66	5110	5	0	0
T105	6123	1	0	0
T227	5540	4	0	0
T236	19868	78	0	0
T237	20013	30	0	0
T247	3187	1	0	0
T278	21218	28	0	0
T279	3463	4	0	0
T280	77892	70	0	0
T283	4018	4	0	0

bank0_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1161	0	0
T66	5110	7	0	0
T105	6123	3	0	0
T227	5540	4	0	0
T236	19868	25	0	0
T237	20013	37	0	0
T247	3187	7	0	0
T278	21218	93	0	0
T279	3463	1	0	0
T280	77892	77	0	0
T283	4018	6	0	0

bank0_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	2811	0	0
T66	5110	12	0	0
T105	6123	40	0	0
T227	5540	8	0	0
T236	19868	26	0	0
T237	20013	4	0	0
T240	3465	11	0	0
T247	3187	6	0	0
T278	21218	73	0	0
T279	3463	27	0	0
T282	3305	38	0	0

bank0_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1223	0	0
T66	5110	16	0	0
T105	6123	8	0	0
T227	5540	4	0	0
T236	19868	41	0	0
T237	20013	12	0	0
T247	3187	8	0	0
T278	21218	77	0	0
T279	3463	7	0	0
T282	3305	5	0	0
T283	4018	7	0	0

bank0_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	3120	0	0
T66	5110	4	0	0
T105	6123	35	0	0
T227	5540	36	0	0
T236	19868	61	0	0
T237	20013	32	0	0
T278	21218	26	0	0
T279	3463	44	0	0
T280	77892	340	0	0
T282	3305	21	0	0
T283	4018	25	0	0

bank0_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	2665	0	0
T66	5110	5	0	0
T105	6123	33	0	0
T227	5540	8	0	0
T236	19868	20	0	0
T237	20013	33	0	0
T240	3465	12	0	0
T278	21218	23	0	0
T279	3463	20	0	0
T282	3305	12	0	0
T283	4018	31	0	0

bank0_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1216	0	0
T66	5110	5	0	0
T105	6123	8	0	0
T227	5540	4	0	0
T236	19868	60	0	0
T237	20013	19	0	0
T240	3465	5	0	0
T278	21218	103	0	0
T279	3463	2	0	0
T280	77892	73	0	0
T283	4018	8	0	0

bank0_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1636	0	0
T66	5110	6	0	0
T105	6123	17	0	0
T227	5540	3	0	0
T236	19868	55	0	0
T237	20013	31	0	0
T278	21218	25	0	0
T280	77892	74	0	0
T281	80406	92	0	0
T282	3305	2	0	0
T283	4018	1	0	0

bank1_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	2970	0	0
T66	5110	8	0	0
T105	6123	1	0	0
T227	5540	13	0	0
T236	19868	68	0	0
T237	20013	39	0	0
T247	3187	4	0	0
T278	21218	51	0	0
T279	3463	37	0	0
T282	3305	25	0	0
T283	4018	25	0	0

bank1_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	2938	0	0
T66	5110	3	0	0
T105	6123	31	0	0
T227	5540	5	0	0
T236	19868	36	0	0
T237	20013	53	0	0
T247	3187	3	0	0
T278	21218	78	0	0
T279	3463	2	0	0
T280	77892	363	0	0
T282	3305	4	0	0

bank1_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	2950	0	0
T66	5110	6	0	0
T105	6123	2	0	0
T227	5540	41	0	0
T236	19868	36	0	0
T237	20013	43	0	0
T240	3465	5	0	0
T278	21218	39	0	0
T280	77892	263	0	0
T282	3305	8	0	0
T283	4018	18	0	0

bank1_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	2891	0	0
T66	5110	11	0	0
T105	6123	15	0	0
T227	5540	17	0	0
T236	19868	52	0	0
T237	20013	82	0	0
T247	3187	10	0	0
T278	21218	22	0	0
T279	3463	6	0	0
T282	3305	8	0	0
T283	4018	16	0	0

bank1_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	2937	0	0
T66	5110	12	0	0
T105	6123	7	0	0
T227	5540	38	0	0
T236	19868	52	0	0
T237	20013	94	0	0
T247	3187	6	0	0
T278	21218	38	0	0
T280	77892	226	0	0
T281	80406	331	0	0
T283	4018	6	0	0

bank1_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	2655	0	0
T66	5110	11	0	0
T105	6123	33	0	0
T227	5540	3	0	0
T236	19868	19	0	0
T237	20013	55	0	0
T240	3465	12	0	0
T247	3187	8	0	0
T278	21218	40	0	0
T279	3463	27	0	0
T283	4018	8	0	0

bank1_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	2723	0	0
T66	5110	16	0	0
T105	6123	14	0	0
T227	5540	31	0	0
T236	19868	66	0	0
T237	20013	31	0	0
T240	3465	3	0	0
T247	3187	9	0	0
T278	21218	19	0	0
T279	3463	23	0	0
T283	4018	26	0	0

bank1_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	2913	0	0
T66	5110	12	0	0
T105	6123	14	0	0
T227	5540	13	0	0
T236	19868	64	0	0
T237	20013	35	0	0
T240	3465	11	0	0
T247	3187	8	0	0
T278	21218	26	0	0
T282	3305	15	0	0
T283	4018	3	0	0

bank1_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	2919	0	0
T66	5110	7	0	0
T105	6123	46	0	0
T227	5540	45	0	0
T236	19868	10	0	0
T237	20013	31	0	0
T240	3465	9	0	0
T247	3187	3	0	0
T278	21218	39	0	0
T279	3463	3	0	0
T283	4018	31	0	0

bank1_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	3071	0	0
T105	6123	6	0	0
T227	5540	7	0	0
T236	19868	25	0	0
T237	20013	58	0	0
T240	3465	12	0	0
T247	3187	7	0	0
T278	21218	83	0	0
T279	3463	24	0	0
T280	77892	331	0	0
T283	4018	7	0	0

bank1_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1494	0	0
T66	5110	6	0	0
T105	6123	7	0	0
T227	5540	6	0	0
T236	19868	44	0	0
T237	20013	20	0	0
T247	3187	4	0	0
T278	21218	89	0	0
T279	3463	6	0	0
T280	77892	89	0	0
T281	80406	80	0	0

bank1_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1265	0	0
T66	5110	13	0	0
T105	6123	6	0	0
T227	5540	10	0	0
T236	19868	46	0	0
T237	20013	31	0	0
T240	3465	6	0	0
T247	3187	2	0	0
T278	21218	38	0	0
T279	3463	6	0	0
T283	4018	4	0	0

bank1_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1541	0	0
T66	5110	10	0	0
T105	6123	6	0	0
T227	5540	9	0	0
T236	19868	32	0	0
T237	20013	48	0	0
T247	3187	8	0	0
T278	21218	57	0	0
T279	3463	4	0	0
T282	3305	4	0	0
T283	4018	7	0	0

bank1_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1435	0	0
T66	5110	9	0	0
T105	6123	6	0	0
T227	5540	11	0	0
T236	19868	28	0	0
T237	20013	59	0	0
T247	3187	1	0	0
T278	21218	41	0	0
T279	3463	7	0	0
T282	3305	6	0	0
T283	4018	8	0	0

bank1_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1405	0	0
T66	5110	6	0	0
T105	6123	11	0	0
T227	5540	9	0	0
T236	19868	66	0	0
T237	20013	19	0	0
T247	3187	8	0	0
T278	21218	35	0	0
T280	77892	73	0	0
T281	80406	75	0	0
T284	43129	41	0	0

bank1_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	690	0	0
T66	5110	2	0	0
T105	6123	7	0	0
T227	5540	7	0	0
T236	19868	46	0	0
T237	20013	36	0	0
T247	3187	3	0	0
T278	21218	28	0	0
T279	3463	7	0	0
T282	3305	5	0	0
T283	4018	5	0	0

bank1_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1249	0	0
T66	5110	6	0	0
T105	6123	11	0	0
T227	5540	12	0	0
T236	19868	12	0	0
T237	20013	45	0	0
T240	3465	3	0	0
T247	3187	2	0	0
T278	21218	62	0	0
T279	3463	8	0	0
T283	4018	6	0	0

bank1_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1446	0	0
T66	5110	8	0	0
T105	6123	3	0	0
T227	5540	9	0	0
T236	19868	59	0	0
T237	20013	13	0	0
T240	3465	2	0	0
T278	21218	31	0	0
T279	3463	4	0	0
T282	3305	8	0	0
T283	4018	7	0	0

bank1_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1080	0	0
T66	5110	17	0	0
T105	6123	13	0	0
T236	19868	47	0	0
T237	20013	25	0	0
T240	3465	1	0	0
T247	3187	3	0	0
T278	21218	85	0	0
T279	3463	6	0	0
T280	77892	88	0	0
T283	4018	7	0	0

bank1_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	900	0	0
T66	5110	15	0	0
T105	6123	9	0	0
T227	5540	10	0	0
T236	19868	10	0	0
T237	20013	9	0	0
T247	3187	1	0	0
T278	21218	27	0	0
T279	3463	6	0	0
T282	3305	4	0	0
T283	4018	5	0	0

bank1_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	3006	0	0
T66	5110	13	0	0
T105	6123	34	0	0
T227	5540	2	0	0
T236	19868	37	0	0
T237	20013	67	0	0
T240	3465	17	0	0
T247	3187	1	0	0
T278	21218	59	0	0
T282	3305	7	0	0
T283	4018	28	0	0

bank1_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1163	0	0
T66	5110	1	0	0
T105	6123	12	0	0
T227	5540	5	0	0
T236	19868	36	0	0
T237	20013	68	0	0
T247	3187	8	0	0
T278	21218	7	0	0
T279	3463	5	0	0
T282	3305	1	0	0
T283	4018	1	0	0

bank1_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	2579	0	0
T66	5110	8	0	0
T105	6123	34	0	0
T227	5540	2	0	0
T236	19868	45	0	0
T237	20013	44	0	0
T240	3465	11	0	0
T247	3187	6	0	0
T278	21218	45	0	0
T282	3305	23	0	0
T283	4018	16	0	0

bank1_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	2855	0	0
T66	5110	7	0	0
T105	6123	8	0	0
T227	5540	44	0	0
T236	19868	41	0	0
T237	20013	30	0	0
T247	3187	3	0	0
T278	21218	64	0	0
T279	3463	23	0	0
T280	77892	204	0	0
T283	4018	2	0	0

bank1_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1261	0	0
T66	5110	3	0	0
T105	6123	13	0	0
T227	5540	10	0	0
T236	19868	20	0	0
T237	20013	53	0	0
T240	3465	2	0	0
T247	3187	4	0	0
T278	21218	32	0	0
T282	3305	3	0	0
T283	4018	4	0	0

bank1_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1518	0	0
T66	5110	8	0	0
T105	6123	9	0	0
T227	5540	3	0	0
T236	19868	50	0	0
T237	20013	65	0	0
T247	3187	7	0	0
T278	21218	29	0	0
T279	3463	6	0	0
T280	77892	104	0	0
T282	3305	3	0	0

bank_cfg_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1154	0	0
T66	5110	11	0	0
T105	6123	1	0	0
T227	5540	11	0	0
T236	19868	60	0	0
T237	20013	50	0	0
T240	3465	1	0	0
T247	3187	7	0	0
T278	21218	38	0	0
T279	3463	3	0	0
T283	4018	1	0	0

default_region_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	2396	0	0
T66	5110	6	0	0
T105	6123	3	0	0
T227	5540	28	0	0
T236	19868	9	0	0
T237	20013	51	0	0
T247	3187	8	0	0
T278	21218	24	0	0
T279	3463	25	0	0
T280	77892	208	0	0
T283	4018	4	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1311	0	0
T66	5110	3	0	0
T105	6123	9	0	0
T227	5540	8	0	0
T236	19868	15	0	0
T237	20013	90	0	0
T240	3465	4	0	0
T247	3187	3	0	0
T278	21218	37	0	0
T279	3463	7	0	0
T280	77892	98	0	0

fifo_lvl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1554	0	0
T66	5110	11	0	0
T105	6123	17	0	0
T227	5540	16	0	0
T236	19868	34	0	0
T237	20013	33	0	0
T240	3465	16	0	0
T247	3187	1	0	0
T278	21218	42	0	0
T282	3305	2	0	0
T283	4018	9	0	0

fifo_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1160	0	0
T66	5110	6	0	0
T105	6123	7	0	0
T227	5540	8	0	0
T236	19868	37	0	0
T237	20013	31	0	0
T247	3187	6	0	0
T278	21218	34	0	0
T279	3463	2	0	0
T282	3305	1	0	0
T283	4018	6	0	0

hw_info_cfg_override_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1792	0	0
T66	5110	8	0	0
T105	6123	12	0	0
T227	5540	20	0	0
T236	19868	75	0	0
T237	20013	21	0	0
T240	3465	9	0	0
T247	3187	1	0	0
T278	21218	60	0	0
T282	3305	6	0	0
T283	4018	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	2562	0	0
T66	5110	6	0	0
T105	6123	2	0	0
T227	5540	19	0	0
T236	19868	59	0	0
T237	20013	35	0	0
T240	3465	5	0	0
T247	3187	7	0	0
T278	21218	48	0	0
T282	3305	3	0	0
T283	4018	22	0	0

mp_region_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1741	0	0
T66	5110	6	0	0
T105	6123	11	0	0
T227	5540	11	0	0
T236	19868	37	0	0
T237	20013	66	0	0
T247	3187	2	0	0
T278	21218	15	0	0
T279	3463	5	0	0
T282	3305	6	0	0
T283	4018	2	0	0

mp_region_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1342	0	0
T66	5110	4	0	0
T105	6123	10	0	0
T227	5540	11	0	0
T236	19868	31	0	0
T237	20013	47	0	0
T278	21218	41	0	0
T280	77892	121	0	0
T281	80406	136	0	0
T282	3305	8	0	0
T283	4018	10	0	0

mp_region_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1557	0	0
T66	5110	6	0	0
T105	6123	5	0	0
T227	5540	8	0	0
T236	19868	56	0	0
T237	20013	52	0	0
T247	3187	6	0	0
T278	21218	30	0	0
T279	3463	6	0	0
T280	77892	136	0	0
T283	4018	10	0	0

mp_region_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1718	0	0
T66	5110	7	0	0
T105	6123	13	0	0
T227	5540	13	0	0
T236	19868	42	0	0
T237	20013	29	0	0
T278	21218	42	0	0
T279	3463	4	0	0
T280	77892	118	0	0
T282	3305	13	0	0
T283	4018	2	0	0

mp_region_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1878	0	0
T66	5110	11	0	0
T105	6123	6	0	0
T227	5540	6	0	0
T236	19868	69	0	0
T237	20013	50	0	0
T247	3187	8	0	0
T278	21218	65	0	0
T279	3463	2	0	0
T280	77892	149	0	0
T283	4018	7	0	0

mp_region_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1512	0	0
T66	5110	10	0	0
T105	6123	6	0	0
T227	5540	11	0	0
T236	19868	56	0	0
T237	20013	53	0	0
T240	3465	4	0	0
T247	3187	3	0	0
T278	21218	28	0	0
T279	3463	10	0	0
T283	4018	1	0	0

mp_region_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1569	0	0
T66	5110	7	0	0
T105	6123	11	0	0
T227	5540	13	0	0
T236	19868	49	0	0
T237	20013	62	0	0
T247	3187	1	0	0
T278	21218	59	0	0
T279	3463	3	0	0
T282	3305	7	0	0
T283	4018	15	0	0

mp_region_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1620	0	0
T66	5110	6	0	0
T105	6123	7	0	0
T227	5540	15	0	0
T236	19868	81	0	0
T237	20013	48	0	0
T240	3465	8	0	0
T247	3187	5	0	0
T278	21218	34	0	0
T282	3305	2	0	0
T283	4018	9	0	0

mp_region_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	2815	0	0
T66	5110	9	0	0
T105	6123	29	0	0
T227	5540	21	0	0
T236	19868	19	0	0
T237	20013	29	0	0
T240	3465	26	0	0
T247	3187	3	0	0
T278	21218	40	0	0
T282	3305	3	0	0
T283	4018	40	0	0

mp_region_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	2941	0	0
T66	5110	6	0	0
T105	6123	24	0	0
T227	5540	20	0	0
T236	19868	23	0	0
T237	20013	16	0	0
T240	3465	7	0	0
T247	3187	5	0	0
T278	21218	23	0	0
T282	3305	10	0	0
T283	4018	4	0	0

mp_region_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	2433	0	0
T66	5110	7	0	0
T105	6123	33	0	0
T227	5540	10	0	0
T236	19868	95	0	0
T237	20013	48	0	0
T240	3465	27	0	0
T247	3187	2	0	0
T278	21218	70	0	0
T279	3463	27	0	0
T282	3305	12	0	0

mp_region_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	2636	0	0
T66	5110	7	0	0
T105	6123	13	0	0
T227	5540	37	0	0
T236	19868	40	0	0
T237	20013	64	0	0
T240	3465	5	0	0
T247	3187	1	0	0
T278	21218	14	0	0
T282	3305	5	0	0
T283	4018	3	0	0

mp_region_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	2810	0	0
T66	5110	11	0	0
T105	6123	9	0	0
T227	5540	29	0	0
T236	19868	23	0	0
T237	20013	42	0	0
T240	3465	14	0	0
T278	21218	34	0	0
T279	3463	3	0	0
T282	3305	3	0	0
T283	4018	26	0	0

mp_region_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	2517	0	0
T66	5110	4	0	0
T105	6123	9	0	0
T227	5540	14	0	0
T236	19868	28	0	0
T237	20013	25	0	0
T247	3187	5	0	0
T278	21218	52	0	0
T279	3463	4	0	0
T282	3305	24	0	0
T283	4018	4	0	0

mp_region_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	2849	0	0
T66	5110	6	0	0
T105	6123	10	0	0
T227	5540	7	0	0
T236	19868	45	0	0
T237	20013	44	0	0
T240	3465	8	0	0
T247	3187	7	0	0
T278	21218	7	0	0
T279	3463	3	0	0
T282	3305	11	0	0

mp_region_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	2770	0	0
T66	5110	10	0	0
T105	6123	51	0	0
T227	5540	11	0	0
T236	19868	42	0	0
T237	20013	28	0	0
T240	3465	16	0	0
T247	3187	9	0	0
T278	21218	32	0	0
T282	3305	17	0	0
T283	4018	30	0	0

phy_alert_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	546	0	0
T66	5110	5	0	0
T227	5540	9	0	0
T236	19868	39	0	0
T237	20013	38	0	0
T247	3187	1	0	0
T278	21218	52	0	0
T285	10460	24	0	0
T286	4897	1	0	0
T287	9748	11	0	0
T288	5315	5	0	0

region_cfg_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1471	0	0
T66	5110	9	0	0
T105	6123	8	0	0
T227	5540	8	0	0
T236	19868	42	0	0
T237	20013	53	0	0
T247	3187	4	0	0
T278	21218	5	0	0
T279	3463	8	0	0
T282	3305	2	0	0
T283	4018	2	0	0

region_cfg_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1534	0	0
T66	5110	6	0	0
T105	6123	2	0	0
T227	5540	8	0	0
T236	19868	69	0	0
T237	20013	49	0	0
T240	3465	7	0	0
T247	3187	1	0	0
T278	21218	47	0	0
T282	3305	3	0	0
T283	4018	3	0	0

region_cfg_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1499	0	0
T66	5110	5	0	0
T105	6123	11	0	0
T227	5540	15	0	0
T236	19868	82	0	0
T237	20013	28	0	0
T247	3187	6	0	0
T278	21218	23	0	0
T280	77892	88	0	0
T282	3305	8	0	0
T283	4018	7	0	0

region_cfg_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1437	0	0
T66	5110	6	0	0
T105	6123	18	0	0
T227	5540	14	0	0
T236	19868	27	0	0
T237	20013	18	0	0
T247	3187	7	0	0
T278	21218	27	0	0
T279	3463	1	0	0
T282	3305	2	0	0
T283	4018	1	0	0

region_cfg_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1478	0	0
T66	5110	9	0	0
T105	6123	10	0	0
T227	5540	9	0	0
T236	19868	39	0	0
T237	20013	45	0	0
T240	3465	7	0	0
T247	3187	9	0	0
T278	21218	19	0	0
T279	3463	5	0	0
T283	4018	3	0	0

region_cfg_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1521	0	0
T66	5110	12	0	0
T105	6123	5	0	0
T227	5540	7	0	0
T236	19868	38	0	0
T237	20013	25	0	0
T247	3187	1	0	0
T278	21218	26	0	0
T279	3463	5	0	0
T282	3305	2	0	0
T283	4018	6	0	0

region_cfg_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1555	0	0
T66	5110	10	0	0
T105	6123	10	0	0
T227	5540	7	0	0
T236	19868	41	0	0
T237	20013	37	0	0
T240	3465	3	0	0
T247	3187	6	0	0
T278	21218	60	0	0
T279	3463	2	0	0
T282	3305	6	0	0

region_cfg_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1330	0	0
T66	5110	7	0	0
T105	6123	2	0	0
T227	5540	4	0	0
T236	19868	35	0	0
T237	20013	47	0	0
T240	3465	2	0	0
T247	3187	7	0	0
T278	21218	74	0	0
T279	3463	9	0	0
T280	77892	99	0	0

scratch_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	380020284	1384	0	0
T66	5110	8	0	0
T105	6123	13	0	0
T227	5540	8	0	0
T236	19868	24	0	0
T237	20013	45	0	0
T247	3187	6	0	0
T278	21218	41	0	0
T279	3463	4	0	0
T280	77892	83	0	0
T281	80406	80	0	0