Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	97.92	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	95.83	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	17945	1		T124	688		T125	623		T129	671
full_word	3765331	1		T1	16		T2	16347		T16	4

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3783006	1		T1	16		T2	16347		T16	4
auto[TlIntgErrCmd]	75	1		T127	3		T238	5		T235	5
auto[TlIntgErrData]	96	1		T127	3		T240	4		T238	2
auto[TlIntgErrBoth]	99	1		T127	3		T240	5		T238	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3759901	1		T1	16		T2	16347		T16	4
auto[1]	23375	1		T124	941		T125	920		T129	836

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1179	1		T124	56		T125	31		T129	54
auto[TlIntgErrNone]	partial	auto[1]	16533	1		T124	632		T125	592		T129	617
auto[TlIntgErrNone]	full_word	auto[0]	3758625	1		T1	16		T2	16347		T16	4
auto[TlIntgErrNone]	full_word	auto[1]	6669	1		T124	309		T125	328		T129	219
auto[TlIntgErrCmd]	partial	auto[0]	23	1		T127	2		T238	3		T235	1
auto[TlIntgErrCmd]	partial	auto[1]	44	1		T127	1		T238	1		T235	4
auto[TlIntgErrCmd]	full_word	auto[1]	8	1		T238	1		T264	2		T334	2
auto[TlIntgErrData]	partial	auto[0]	25	1		T127	1		T240	1		T238	1
auto[TlIntgErrData]	partial	auto[1]	53	1		T127	2		T240	2		T235	3
auto[TlIntgErrData]	full_word	auto[0]	13	1		T238	1		T235	2		T263	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T240	1		T235	1		T335	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1		T240	2		T238	1		T235	1
auto[TlIntgErrBoth]	partial	auto[1]	55	1		T127	3		T240	3		T238	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T235	1		T334	1		T265	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1		T264	1		T334	1		T265	2

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	26599846	1		T1	507		T2	2430		T3	97180
full_word	7740905	1		T1	157		T2	1927		T3	13104

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	34340461	1		T1	664		T2	4357		T3	110284
auto[TlIntgErrCmd]	108	1		T127	2		T240	3		T238	3
auto[TlIntgErrData]	86	1		T127	5		T240	4		T238	2
auto[TlIntgErrBoth]	96	1		T127	3		T240	3		T238	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29767523	1		T1	560		T2	3499		T3	96737
auto[1]	4573228	1		T1	104		T2	858		T3	13547

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	25818630	1		T1	486		T2	1923		T3	95910
auto[TlIntgErrNone]	partial	auto[1]	780945	1		T1	21		T2	507		T3	1270
auto[TlIntgErrNone]	full_word	auto[0]	3948758	1		T1	74		T2	1576		T3	827
auto[TlIntgErrNone]	full_word	auto[1]	3792128	1		T1	83		T2	351		T3	12277
auto[TlIntgErrCmd]	partial	auto[0]	43	1		T127	1		T235	4		T295	1
auto[TlIntgErrCmd]	partial	auto[1]	54	1		T240	3		T238	2		T235	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T235	1		T335	1		T331	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1		T127	1		T238	1		T263	2
auto[TlIntgErrData]	partial	auto[0]	44	1		T127	3		T238	1		T235	2
auto[TlIntgErrData]	partial	auto[1]	40	1		T127	2		T240	4		T238	1
auto[TlIntgErrData]	full_word	auto[0]	1	1		T334	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	1	1		T336	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	42	1		T127	2		T240	2		T238	2
auto[TlIntgErrBoth]	partial	auto[1]	48	1		T127	1		T240	1		T238	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T334	1		T335	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T238	1		T235	1		T337	1