Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T16

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T16
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T16
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T16

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T16
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T16

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T16

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1527291172	1524098748	0	0
CheckNGreaterZero_A	4156	4156	0	0
GntImpliesReady_A	1527291172	413914565	0	0
GntImpliesValid_A	1527291172	413914565	0	0
GrantKnown_A	1527291172	1524098748	0	0
IdxKnown_A	1527291172	1524098748	0	0
IndexIsCorrect_A	1527291172	413914565	0	0
NoReadyValidNoGrant_A	1527291172	174224777	0	0
Priority_A	1527291172	437943196	0	0
ReadyAndValidImplyGrant_A	1527291172	413914565	0	0
ReqAndReadyImplyGrant_A	1527291172	413914565	0	0
ReqImpliesValid_A	1527291172	437943196	0	0
ValidKnown_A	1527291172	1524098748	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1527291172	1524098748	0	0
T1	9988	9332	0	0
T2	2314972	2314324	0	0
T3	888084	887440	0	0
T4	8616	8232	0	0
T6	268188	267704	0	0
T15	17192	14344	0	0
T16	7944	7276	0	0
T17	7060	6464	0	0
T18	2828	2532	0	0
T19	12284	12008	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4156	4156	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T6	4	4	0	0
T15	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1527291172	413914565	0	0
T1	9988	954	0	0
T2	2314972	35242	0	0
T3	888084	381634	0	0
T4	8616	938	0	0
T6	268188	46920	0	0
T7	0	227498	0	0
T15	17192	584	0	0
T16	7944	350	0	0
T17	7060	138	0	0
T18	2828	200	0	0
T19	12284	64	0	0
T22	0	16174	0	0
T28	0	255794	0	0
T34	0	45346	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1527291172	413914565	0	0
T1	9988	954	0	0
T2	2314972	35242	0	0
T3	888084	381634	0	0
T4	8616	938	0	0
T6	268188	46920	0	0
T7	0	227498	0	0
T15	17192	584	0	0
T16	7944	350	0	0
T17	7060	138	0	0
T18	2828	200	0	0
T19	12284	64	0	0
T22	0	16174	0	0
T28	0	255794	0	0
T34	0	45346	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1527291172	1524098748	0	0
T1	9988	9332	0	0
T2	2314972	2314324	0	0
T3	888084	887440	0	0
T4	8616	8232	0	0
T6	268188	267704	0	0
T15	17192	14344	0	0
T16	7944	7276	0	0
T17	7060	6464	0	0
T18	2828	2532	0	0
T19	12284	12008	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1527291172	1524098748	0	0
T1	9988	9332	0	0
T2	2314972	2314324	0	0
T3	888084	887440	0	0
T4	8616	8232	0	0
T6	268188	267704	0	0
T15	17192	14344	0	0
T16	7944	7276	0	0
T17	7060	6464	0	0
T18	2828	2532	0	0
T19	12284	12008	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1527291172	413914565	0	0
T1	9988	954	0	0
T2	2314972	35242	0	0
T3	888084	381634	0	0
T4	8616	938	0	0
T6	268188	46920	0	0
T7	0	227498	0	0
T15	17192	584	0	0
T16	7944	350	0	0
T17	7060	138	0	0
T18	2828	200	0	0
T19	12284	64	0	0
T22	0	16174	0	0
T28	0	255794	0	0
T34	0	45346	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1527291172	174224777	0	0
T1	9988	978	0	0
T2	2314972	1194266	0	0
T3	888084	512	0	0
T4	8616	256	0	0
T6	268188	133608	0	0
T7	0	102512	0	0
T15	17192	2048	0	0
T16	7944	700	0	0
T17	7060	512	0	0
T18	2828	272	0	0
T19	12284	256	0	0
T22	0	49222	0	0
T23	0	1217464	0	0
T28	0	1048576	0	0
T34	0	1336744	0	0
T62	0	25630	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1527291172	437943196	0	0
T1	9988	954	0	0
T2	2314972	578600	0	0
T3	888084	381634	0	0
T4	8616	938	0	0
T6	268188	51170	0	0
T7	0	292176	0	0
T15	17192	584	0	0
T16	7944	350	0	0
T17	7060	138	0	0
T18	2828	200	0	0
T19	12284	64	0	0
T22	0	18470	0	0
T28	0	255794	0	0
T34	0	322294	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1527291172	413914565	0	0
T1	9988	954	0	0
T2	2314972	35242	0	0
T3	888084	381634	0	0
T4	8616	938	0	0
T6	268188	46920	0	0
T7	0	227498	0	0
T15	17192	584	0	0
T16	7944	350	0	0
T17	7060	138	0	0
T18	2828	200	0	0
T19	12284	64	0	0
T22	0	16174	0	0
T28	0	255794	0	0
T34	0	45346	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1527291172	413914565	0	0
T1	9988	954	0	0
T2	2314972	35242	0	0
T3	888084	381634	0	0
T4	8616	938	0	0
T6	268188	46920	0	0
T7	0	227498	0	0
T15	17192	584	0	0
T16	7944	350	0	0
T17	7060	138	0	0
T18	2828	200	0	0
T19	12284	64	0	0
T22	0	16174	0	0
T28	0	255794	0	0
T34	0	45346	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1527291172	437943196	0	0
T1	9988	954	0	0
T2	2314972	578600	0	0
T3	888084	381634	0	0
T4	8616	938	0	0
T6	268188	51170	0	0
T7	0	292176	0	0
T15	17192	584	0	0
T16	7944	350	0	0
T17	7060	138	0	0
T18	2828	200	0	0
T19	12284	64	0	0
T22	0	18470	0	0
T28	0	255794	0	0
T34	0	322294	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1527291172	1524098748	0	0
T1	9988	9332	0	0
T2	2314972	2314324	0	0
T3	888084	887440	0	0
T4	8616	8232	0	0
T6	268188	267704	0	0
T15	17192	14344	0	0
T16	7944	7276	0	0
T17	7060	6464	0	0
T18	2828	2532	0	0
T19	12284	12008	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T16

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T16
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T16
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T16

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T16
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T16

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T16

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	381822793	381024687	0	0
CheckNGreaterZero_A	1039	1039	0	0
GntImpliesReady_A	381822793	110706094	0	0
GntImpliesValid_A	381822793	110706094	0	0
GrantKnown_A	381822793	381024687	0	0
IdxKnown_A	381822793	381024687	0	0
IndexIsCorrect_A	381822793	110706094	0	0
NoReadyValidNoGrant_A	381822793	45458442	0	0
Priority_A	381822793	116858495	0	0
ReadyAndValidImplyGrant_A	381822793	110706094	0	0
ReqAndReadyImplyGrant_A	381822793	110706094	0	0
ReqImpliesValid_A	381822793	116858495	0	0
ValidKnown_A	381822793	381024687	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	381024687	0	0
T1	2497	2333	0	0
T2	578743	578581	0	0
T3	222021	221860	0	0
T4	2154	2058	0	0
T6	67047	66926	0	0
T15	4298	3586	0	0
T16	1986	1819	0	0
T17	1765	1616	0	0
T18	707	633	0	0
T19	3071	3002	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1039	1039	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	110706094	0	0
T1	2497	323	0	0
T2	578743	9568	0	0
T3	222021	132235	0	0
T4	2154	469	0	0
T6	67047	14721	0	0
T15	4298	292	0	0
T16	1986	106	0	0
T17	1765	69	0	0
T18	707	34	0	0
T19	3071	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	110706094	0	0
T1	2497	323	0	0
T2	578743	9568	0	0
T3	222021	132235	0	0
T4	2154	469	0	0
T6	67047	14721	0	0
T15	4298	292	0	0
T16	1986	106	0	0
T17	1765	69	0	0
T18	707	34	0	0
T19	3071	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	381024687	0	0
T1	2497	2333	0	0
T2	578743	578581	0	0
T3	222021	221860	0	0
T4	2154	2058	0	0
T6	67047	66926	0	0
T15	4298	3586	0	0
T16	1986	1819	0	0
T17	1765	1616	0	0
T18	707	633	0	0
T19	3071	3002	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	381024687	0	0
T1	2497	2333	0	0
T2	578743	578581	0	0
T3	222021	221860	0	0
T4	2154	2058	0	0
T6	67047	66926	0	0
T15	4298	3586	0	0
T16	1986	1819	0	0
T17	1765	1616	0	0
T18	707	633	0	0
T19	3071	3002	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	110706094	0	0
T1	2497	323	0	0
T2	578743	9568	0	0
T3	222021	132235	0	0
T4	2154	469	0	0
T6	67047	14721	0	0
T15	4298	292	0	0
T16	1986	106	0	0
T17	1765	69	0	0
T18	707	34	0	0
T19	3071	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	45458442	0	0
T1	2497	419	0	0
T2	578743	319120	0	0
T3	222021	256	0	0
T4	2154	128	0	0
T6	67047	40983	0	0
T15	4298	1024	0	0
T16	1986	342	0	0
T17	1765	256	0	0
T18	707	136	0	0
T19	3071	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	116858495	0	0
T1	2497	323	0	0
T2	578743	152555	0	0
T3	222021	132235	0	0
T4	2154	469	0	0
T6	67047	15257	0	0
T15	4298	292	0	0
T16	1986	106	0	0
T17	1765	69	0	0
T18	707	34	0	0
T19	3071	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	110706094	0	0
T1	2497	323	0	0
T2	578743	9568	0	0
T3	222021	132235	0	0
T4	2154	469	0	0
T6	67047	14721	0	0
T15	4298	292	0	0
T16	1986	106	0	0
T17	1765	69	0	0
T18	707	34	0	0
T19	3071	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	110706094	0	0
T1	2497	323	0	0
T2	578743	9568	0	0
T3	222021	132235	0	0
T4	2154	469	0	0
T6	67047	14721	0	0
T15	4298	292	0	0
T16	1986	106	0	0
T17	1765	69	0	0
T18	707	34	0	0
T19	3071	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	116858495	0	0
T1	2497	323	0	0
T2	578743	152555	0	0
T3	222021	132235	0	0
T4	2154	469	0	0
T6	67047	15257	0	0
T15	4298	292	0	0
T16	1986	106	0	0
T17	1765	69	0	0
T18	707	34	0	0
T19	3071	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	381024687	0	0
T1	2497	2333	0	0
T2	578743	578581	0	0
T3	222021	221860	0	0
T4	2154	2058	0	0
T6	67047	66926	0	0
T15	4298	3586	0	0
T16	1986	1819	0	0
T17	1765	1616	0	0
T18	707	633	0	0
T19	3071	3002	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T16

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T16
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T16
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T16

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T16
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T16

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T16

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	381822793	381024687	0	0
CheckNGreaterZero_A	1039	1039	0	0
GntImpliesReady_A	381822793	110706107	0	0
GntImpliesValid_A	381822793	110706107	0	0
GrantKnown_A	381822793	381024687	0	0
IdxKnown_A	381822793	381024687	0	0
IndexIsCorrect_A	381822793	110706107	0	0
NoReadyValidNoGrant_A	381822793	45458433	0	0
Priority_A	381822793	116858517	0	0
ReadyAndValidImplyGrant_A	381822793	110706107	0	0
ReqAndReadyImplyGrant_A	381822793	110706107	0	0
ReqImpliesValid_A	381822793	116858517	0	0
ValidKnown_A	381822793	381024687	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	381024687	0	0
T1	2497	2333	0	0
T2	578743	578581	0	0
T3	222021	221860	0	0
T4	2154	2058	0	0
T6	67047	66926	0	0
T15	4298	3586	0	0
T16	1986	1819	0	0
T17	1765	1616	0	0
T18	707	633	0	0
T19	3071	3002	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1039	1039	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	110706107	0	0
T1	2497	323	0	0
T2	578743	9568	0	0
T3	222021	132235	0	0
T4	2154	469	0	0
T6	67047	14721	0	0
T15	4298	292	0	0
T16	1986	106	0	0
T17	1765	69	0	0
T18	707	34	0	0
T19	3071	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	110706107	0	0
T1	2497	323	0	0
T2	578743	9568	0	0
T3	222021	132235	0	0
T4	2154	469	0	0
T6	67047	14721	0	0
T15	4298	292	0	0
T16	1986	106	0	0
T17	1765	69	0	0
T18	707	34	0	0
T19	3071	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	381024687	0	0
T1	2497	2333	0	0
T2	578743	578581	0	0
T3	222021	221860	0	0
T4	2154	2058	0	0
T6	67047	66926	0	0
T15	4298	3586	0	0
T16	1986	1819	0	0
T17	1765	1616	0	0
T18	707	633	0	0
T19	3071	3002	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	381024687	0	0
T1	2497	2333	0	0
T2	578743	578581	0	0
T3	222021	221860	0	0
T4	2154	2058	0	0
T6	67047	66926	0	0
T15	4298	3586	0	0
T16	1986	1819	0	0
T17	1765	1616	0	0
T18	707	633	0	0
T19	3071	3002	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	110706107	0	0
T1	2497	323	0	0
T2	578743	9568	0	0
T3	222021	132235	0	0
T4	2154	469	0	0
T6	67047	14721	0	0
T15	4298	292	0	0
T16	1986	106	0	0
T17	1765	69	0	0
T18	707	34	0	0
T19	3071	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	45458433	0	0
T1	2497	419	0	0
T2	578743	319120	0	0
T3	222021	256	0	0
T4	2154	128	0	0
T6	67047	40983	0	0
T15	4298	1024	0	0
T16	1986	342	0	0
T17	1765	256	0	0
T18	707	136	0	0
T19	3071	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	116858517	0	0
T1	2497	323	0	0
T2	578743	152555	0	0
T3	222021	132235	0	0
T4	2154	469	0	0
T6	67047	15257	0	0
T15	4298	292	0	0
T16	1986	106	0	0
T17	1765	69	0	0
T18	707	34	0	0
T19	3071	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	110706107	0	0
T1	2497	323	0	0
T2	578743	9568	0	0
T3	222021	132235	0	0
T4	2154	469	0	0
T6	67047	14721	0	0
T15	4298	292	0	0
T16	1986	106	0	0
T17	1765	69	0	0
T18	707	34	0	0
T19	3071	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	110706107	0	0
T1	2497	323	0	0
T2	578743	9568	0	0
T3	222021	132235	0	0
T4	2154	469	0	0
T6	67047	14721	0	0
T15	4298	292	0	0
T16	1986	106	0	0
T17	1765	69	0	0
T18	707	34	0	0
T19	3071	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	116858517	0	0
T1	2497	323	0	0
T2	578743	152555	0	0
T3	222021	132235	0	0
T4	2154	469	0	0
T6	67047	15257	0	0
T15	4298	292	0	0
T16	1986	106	0	0
T17	1765	69	0	0
T18	707	34	0	0
T19	3071	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	381024687	0	0
T1	2497	2333	0	0
T2	578743	578581	0	0
T3	222021	221860	0	0
T4	2154	2058	0	0
T6	67047	66926	0	0
T15	4298	3586	0	0
T16	1986	1819	0	0
T17	1765	1616	0	0
T18	707	633	0	0
T19	3071	3002	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T16
1	0	Covered	T1,T2,T16

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T16
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T16
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T3,T16
1	1	Covered	T1,T2,T16

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T16
1	1	Covered	T1,T3,T16

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T16

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T16

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	381822793	381024687	0	0
CheckNGreaterZero_A	1039	1039	0	0
GntImpliesReady_A	381822793	96251182	0	0
GntImpliesValid_A	381822793	96251182	0	0
GrantKnown_A	381822793	381024687	0	0
IdxKnown_A	381822793	381024687	0	0
IndexIsCorrect_A	381822793	96251182	0	0
NoReadyValidNoGrant_A	381822793	41653951	0	0
Priority_A	381822793	102113092	0	0
ReadyAndValidImplyGrant_A	381822793	96251182	0	0
ReqAndReadyImplyGrant_A	381822793	96251182	0	0
ReqImpliesValid_A	381822793	102113092	0	0
ValidKnown_A	381822793	381024687	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	381024687	0	0
T1	2497	2333	0	0
T2	578743	578581	0	0
T3	222021	221860	0	0
T4	2154	2058	0	0
T6	67047	66926	0	0
T15	4298	3586	0	0
T16	1986	1819	0	0
T17	1765	1616	0	0
T18	707	633	0	0
T19	3071	3002	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1039	1039	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	96251182	0	0
T1	2497	154	0	0
T2	578743	8053	0	0
T3	222021	58582	0	0
T4	2154	0	0	0
T6	67047	8739	0	0
T7	0	113749	0	0
T15	4298	0	0	0
T16	1986	69	0	0
T17	1765	0	0	0
T18	707	66	0	0
T19	3071	0	0	0
T22	0	8087	0	0
T28	0	127897	0	0
T34	0	22673	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	96251182	0	0
T1	2497	154	0	0
T2	578743	8053	0	0
T3	222021	58582	0	0
T4	2154	0	0	0
T6	67047	8739	0	0
T7	0	113749	0	0
T15	4298	0	0	0
T16	1986	69	0	0
T17	1765	0	0	0
T18	707	66	0	0
T19	3071	0	0	0
T22	0	8087	0	0
T28	0	127897	0	0
T34	0	22673	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	381024687	0	0
T1	2497	2333	0	0
T2	578743	578581	0	0
T3	222021	221860	0	0
T4	2154	2058	0	0
T6	67047	66926	0	0
T15	4298	3586	0	0
T16	1986	1819	0	0
T17	1765	1616	0	0
T18	707	633	0	0
T19	3071	3002	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	381024687	0	0
T1	2497	2333	0	0
T2	578743	578581	0	0
T3	222021	221860	0	0
T4	2154	2058	0	0
T6	67047	66926	0	0
T15	4298	3586	0	0
T16	1986	1819	0	0
T17	1765	1616	0	0
T18	707	633	0	0
T19	3071	3002	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	96251182	0	0
T1	2497	154	0	0
T2	578743	8053	0	0
T3	222021	58582	0	0
T4	2154	0	0	0
T6	67047	8739	0	0
T7	0	113749	0	0
T15	4298	0	0	0
T16	1986	69	0	0
T17	1765	0	0	0
T18	707	66	0	0
T19	3071	0	0	0
T22	0	8087	0	0
T28	0	127897	0	0
T34	0	22673	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	41653951	0	0
T1	2497	70	0	0
T2	578743	278013	0	0
T3	222021	0	0	0
T4	2154	0	0	0
T6	67047	25821	0	0
T7	0	51256	0	0
T15	4298	0	0	0
T16	1986	8	0	0
T17	1765	0	0	0
T18	707	0	0	0
T19	3071	0	0	0
T22	0	24611	0	0
T23	0	608732	0	0
T28	0	524288	0	0
T34	0	668372	0	0
T62	0	12815	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	102113092	0	0
T1	2497	154	0	0
T2	578743	136745	0	0
T3	222021	58582	0	0
T4	2154	0	0	0
T6	67047	10328	0	0
T7	0	146088	0	0
T15	4298	0	0	0
T16	1986	69	0	0
T17	1765	0	0	0
T18	707	66	0	0
T19	3071	0	0	0
T22	0	9235	0	0
T28	0	127897	0	0
T34	0	161147	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	96251182	0	0
T1	2497	154	0	0
T2	578743	8053	0	0
T3	222021	58582	0	0
T4	2154	0	0	0
T6	67047	8739	0	0
T7	0	113749	0	0
T15	4298	0	0	0
T16	1986	69	0	0
T17	1765	0	0	0
T18	707	66	0	0
T19	3071	0	0	0
T22	0	8087	0	0
T28	0	127897	0	0
T34	0	22673	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	96251182	0	0
T1	2497	154	0	0
T2	578743	8053	0	0
T3	222021	58582	0	0
T4	2154	0	0	0
T6	67047	8739	0	0
T7	0	113749	0	0
T15	4298	0	0	0
T16	1986	69	0	0
T17	1765	0	0	0
T18	707	66	0	0
T19	3071	0	0	0
T22	0	8087	0	0
T28	0	127897	0	0
T34	0	22673	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	102113092	0	0
T1	2497	154	0	0
T2	578743	136745	0	0
T3	222021	58582	0	0
T4	2154	0	0	0
T6	67047	10328	0	0
T7	0	146088	0	0
T15	4298	0	0	0
T16	1986	69	0	0
T17	1765	0	0	0
T18	707	66	0	0
T19	3071	0	0	0
T22	0	9235	0	0
T28	0	127897	0	0
T34	0	161147	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	381024687	0	0
T1	2497	2333	0	0
T2	578743	578581	0	0
T3	222021	221860	0	0
T4	2154	2058	0	0
T6	67047	66926	0	0
T15	4298	3586	0	0
T16	1986	1819	0	0
T17	1765	1616	0	0
T18	707	633	0	0
T19	3071	3002	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T16
1	0	Covered	T1,T2,T16

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T16
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T2,T16
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T3,T16
1	1	Covered	T1,T2,T16

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T16
1	1	Covered	T1,T3,T16

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T16

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T16

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	381822793	381024687	0	0
CheckNGreaterZero_A	1039	1039	0	0
GntImpliesReady_A	381822793	96251182	0	0
GntImpliesValid_A	381822793	96251182	0	0
GrantKnown_A	381822793	381024687	0	0
IdxKnown_A	381822793	381024687	0	0
IndexIsCorrect_A	381822793	96251182	0	0
NoReadyValidNoGrant_A	381822793	41653951	0	0
Priority_A	381822793	102113092	0	0
ReadyAndValidImplyGrant_A	381822793	96251182	0	0
ReqAndReadyImplyGrant_A	381822793	96251182	0	0
ReqImpliesValid_A	381822793	102113092	0	0
ValidKnown_A	381822793	381024687	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	381024687	0	0
T1	2497	2333	0	0
T2	578743	578581	0	0
T3	222021	221860	0	0
T4	2154	2058	0	0
T6	67047	66926	0	0
T15	4298	3586	0	0
T16	1986	1819	0	0
T17	1765	1616	0	0
T18	707	633	0	0
T19	3071	3002	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1039	1039	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	96251182	0	0
T1	2497	154	0	0
T2	578743	8053	0	0
T3	222021	58582	0	0
T4	2154	0	0	0
T6	67047	8739	0	0
T7	0	113749	0	0
T15	4298	0	0	0
T16	1986	69	0	0
T17	1765	0	0	0
T18	707	66	0	0
T19	3071	0	0	0
T22	0	8087	0	0
T28	0	127897	0	0
T34	0	22673	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	96251182	0	0
T1	2497	154	0	0
T2	578743	8053	0	0
T3	222021	58582	0	0
T4	2154	0	0	0
T6	67047	8739	0	0
T7	0	113749	0	0
T15	4298	0	0	0
T16	1986	69	0	0
T17	1765	0	0	0
T18	707	66	0	0
T19	3071	0	0	0
T22	0	8087	0	0
T28	0	127897	0	0
T34	0	22673	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	381024687	0	0
T1	2497	2333	0	0
T2	578743	578581	0	0
T3	222021	221860	0	0
T4	2154	2058	0	0
T6	67047	66926	0	0
T15	4298	3586	0	0
T16	1986	1819	0	0
T17	1765	1616	0	0
T18	707	633	0	0
T19	3071	3002	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	381024687	0	0
T1	2497	2333	0	0
T2	578743	578581	0	0
T3	222021	221860	0	0
T4	2154	2058	0	0
T6	67047	66926	0	0
T15	4298	3586	0	0
T16	1986	1819	0	0
T17	1765	1616	0	0
T18	707	633	0	0
T19	3071	3002	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	96251182	0	0
T1	2497	154	0	0
T2	578743	8053	0	0
T3	222021	58582	0	0
T4	2154	0	0	0
T6	67047	8739	0	0
T7	0	113749	0	0
T15	4298	0	0	0
T16	1986	69	0	0
T17	1765	0	0	0
T18	707	66	0	0
T19	3071	0	0	0
T22	0	8087	0	0
T28	0	127897	0	0
T34	0	22673	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	41653951	0	0
T1	2497	70	0	0
T2	578743	278013	0	0
T3	222021	0	0	0
T4	2154	0	0	0
T6	67047	25821	0	0
T7	0	51256	0	0
T15	4298	0	0	0
T16	1986	8	0	0
T17	1765	0	0	0
T18	707	0	0	0
T19	3071	0	0	0
T22	0	24611	0	0
T23	0	608732	0	0
T28	0	524288	0	0
T34	0	668372	0	0
T62	0	12815	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	102113092	0	0
T1	2497	154	0	0
T2	578743	136745	0	0
T3	222021	58582	0	0
T4	2154	0	0	0
T6	67047	10328	0	0
T7	0	146088	0	0
T15	4298	0	0	0
T16	1986	69	0	0
T17	1765	0	0	0
T18	707	66	0	0
T19	3071	0	0	0
T22	0	9235	0	0
T28	0	127897	0	0
T34	0	161147	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	96251182	0	0
T1	2497	154	0	0
T2	578743	8053	0	0
T3	222021	58582	0	0
T4	2154	0	0	0
T6	67047	8739	0	0
T7	0	113749	0	0
T15	4298	0	0	0
T16	1986	69	0	0
T17	1765	0	0	0
T18	707	66	0	0
T19	3071	0	0	0
T22	0	8087	0	0
T28	0	127897	0	0
T34	0	22673	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	96251182	0	0
T1	2497	154	0	0
T2	578743	8053	0	0
T3	222021	58582	0	0
T4	2154	0	0	0
T6	67047	8739	0	0
T7	0	113749	0	0
T15	4298	0	0	0
T16	1986	69	0	0
T17	1765	0	0	0
T18	707	66	0	0
T19	3071	0	0	0
T22	0	8087	0	0
T28	0	127897	0	0
T34	0	22673	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	102113092	0	0
T1	2497	154	0	0
T2	578743	136745	0	0
T3	222021	58582	0	0
T4	2154	0	0	0
T6	67047	10328	0	0
T7	0	146088	0	0
T15	4298	0	0	0
T16	1986	69	0	0
T17	1765	0	0	0
T18	707	66	0	0
T19	3071	0	0	0
T22	0	9235	0	0
T28	0	127897	0	0
T34	0	161147	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	381024687	0	0
T1	2497	2333	0	0
T2	578743	578581	0	0
T3	222021	221860	0	0
T4	2154	2058	0	0
T6	67047	66926	0	0
T15	4298	3586	0	0
T16	1986	1819	0	0
T17	1765	1616	0	0
T18	707	633	0	0
T19	3071	3002	0	0