Unified Coverage Report :: Module :: prim_generic_ram_1p

Module : prim_generic_ram_1p

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic	95.24	85.71				100.00	100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic	95.24	85.71				100.00	100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic	95.24	85.71				100.00	100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic	95.24	85.71				100.00	100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic	95.24	85.71				100.00	100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic	95.24	85.71				100.00	100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic	95.24	85.71				100.00	100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic	95.24	85.71				100.00	100.00

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_info_types[0].u_info_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_info_types[1].u_info_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_info_types[2].u_info_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_info_types[0].u_info_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_info_types[1].u_info_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_info_types[2].u_info_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1p

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	0	0
ALWAYS	63	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	0	1
52		unreachable
63	1	1
64	1	1
65	1	1
66	1	1
67	1	1
			==> MISSING_ELSE
72	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1p

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	63	if (req_i)
-2-:	64	if (write_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T3,T15
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1p

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	8312	8312	0	0
gen_wmask[0].MaskCheck_A	2147483647	182237428	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8312	8312	0	0
T1	8	8	0	0
T2	8	8	0	0
T3	8	8	0	0
T4	8	8	0	0
T6	8	8	0	0
T15	8	8	0	0
T16	8	8	0	0
T17	8	8	0	0
T18	8	8	0	0
T19	8	8	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	182237428	0	0
T1	2497	50	0	0
T2	578743	0	0	0
T3	222021	14200	0	0
T4	2154	0	0	0
T6	67047	0	0	0
T7	325555	7750	0	0
T15	4298	27	0	0
T16	1986	0	0	0
T17	1765	0	0	0
T18	707	0	0	0
T19	3071	0	0	0
T26	147585	655360	0	0
T27	393860	0	0	0
T28	0	4864	0	0
T29	0	552	0	0
T30	0	131072	0	0
T31	0	768	0	0
T32	0	4864	0	0
T33	0	11950	0	0
T35	0	50	0	0
T36	0	12500	0	0
T83	0	65536	0	0
T87	3315	0	0	0
T94	0	655360	0	0
T134	1584	0	0	0
T137	0	786432	0	0
T138	0	606	0	0
T139	0	983040	0	0
T140	0	851968	0	0
T141	0	655360	0	0
T142	0	786432	0	0
T143	1827	0	0	0
T144	1787	0	0	0
T145	1499	0	0	0
T146	203621	0	0	0
T147	1291	0	0	0
T148	401215	0	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	0	0
ALWAYS	63	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	0	1
52		unreachable
63	1	1
64	1	1
65	1	1
66	1	1
67	1	1
			==> MISSING_ELSE
72	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	63	if (req_i)
-2-:	64	if (write_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	1039	1039	0	0
gen_wmask[0].MaskCheck_A	381822793	66584188	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1039	1039	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	66584188	0	0
T1	2497	100	0	0
T2	578743	0	0	0
T3	222021	98900	0	0
T4	2154	400	0	0
T6	67047	0	0	0
T7	0	64050	0	0
T15	4298	0	0	0
T16	1986	0	0	0
T17	1765	0	0	0
T18	707	0	0	0
T19	3071	0	0	0
T28	0	393216	0	0
T31	0	1792	0	0
T32	0	393221	0	0
T33	0	108200	0	0
T35	0	50	0	0
T70	0	7900	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	0	0
ALWAYS	63	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	0	1
52		unreachable
63	1	1
64	1	1
65	1	1
66	1	1
67	1	1
			==> MISSING_ELSE
72	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	63	if (req_i)
-2-:	64	if (write_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T3,T15
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	1039	1039	0	0
gen_wmask[0].MaskCheck_A	381822793	17889535	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1039	1039	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	17889535	0	0
T1	2497	50	0	0
T2	578743	0	0	0
T3	222021	14200	0	0
T4	2154	0	0	0
T6	67047	0	0	0
T7	0	7450	0	0
T15	4298	27	0	0
T16	1986	0	0	0
T17	1765	0	0	0
T18	707	0	0	0
T19	3071	0	0	0
T28	0	4864	0	0
T29	0	552	0	0
T31	0	768	0	0
T32	0	4864	0	0
T33	0	10600	0	0
T35	0	50	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	0	0
ALWAYS	63	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	0	1
52		unreachable
63	1	1
64	1	1
65	1	1
66	1	1
67	1	1
			==> MISSING_ELSE
72	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	63	if (req_i)
-2-:	64	if (write_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T26,T30,T83
1	0	Covered	T2,T7,T69
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	1039	1039	0	0
gen_wmask[0].MaskCheck_A	381822793	7838346	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1039	1039	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	7838346	0	0
T26	147585	327680	0	0
T27	393860	0	0	0
T30	0	131072	0	0
T83	0	65536	0	0
T87	3315	0	0	0
T94	0	655360	0	0
T134	1584	0	0	0
T137	0	786432	0	0
T138	0	606	0	0
T139	0	983040	0	0
T140	0	851968	0	0
T141	0	655360	0	0
T142	0	786432	0	0
T143	1827	0	0	0
T144	1787	0	0	0
T145	1499	0	0	0
T146	203621	0	0	0
T147	1291	0	0	0
T148	401215	0	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	0	0
ALWAYS	63	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	0	1
52		unreachable
63	1	1
64	1	1
65	1	1
66	1	1
67	1	1
			==> MISSING_ELSE
72	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	63	if (req_i)
-2-:	64	if (write_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T7,T33,T36
1	0	Covered	T2,T16,T7
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	1039	1039	0	0
gen_wmask[0].MaskCheck_A	381822793	7978700	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1039	1039	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	7978700	0	0
T7	325555	300	0	0
T12	3419	0	0	0
T22	67279	0	0	0
T23	120134	0	0	0
T26	0	327680	0	0
T28	393383	0	0	0
T29	962763	0	0	0
T33	344872	1350	0	0
T34	122393	0	0	0
T36	0	12500	0	0
T37	0	850	0	0
T38	0	2500	0	0
T44	0	150	0	0
T62	51044	0	0	0
T122	1011	0	0	0
T144	0	50	0	0
T149	0	300	0	0
T150	0	650	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	0	0
ALWAYS	63	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	0	1
52		unreachable
63	1	1
64	1	1
65	1	1
66	1	1
67	1	1
			==> MISSING_ELSE
72	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	63	if (req_i)
-2-:	64	if (write_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T3,T18
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	1039	1039	0	0
gen_wmask[0].MaskCheck_A	381822793	60989363	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1039	1039	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	60989363	0	0
T1	2497	100	0	0
T2	578743	0	0	0
T3	222021	50250	0	0
T4	2154	0	0	0
T6	67047	0	0	0
T7	0	104300	0	0
T15	4298	0	0	0
T16	1986	0	0	0
T17	1765	0	0	0
T18	707	50	0	0
T19	3071	0	0	0
T28	0	393216	0	0
T31	0	768	0	0
T32	0	393216	0	0
T33	0	68000	0	0
T49	0	400	0	0
T70	0	11250	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	0	0
ALWAYS	63	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	0	1
52		unreachable
63	1	1
64	1	1
65	1	1
66	1	1
67	1	1
			==> MISSING_ELSE
72	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	63	if (req_i)
-2-:	64	if (write_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T16,T93,T95
1	0	Covered	T16,T31,T93
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	1039	1039	0	0
gen_wmask[0].MaskCheck_A	381822793	7760480	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1039	1039	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	7760480	0	0
T4	2154	0	0	0
T5	143054	0	0	0
T6	67047	0	0	0
T7	325555	0	0	0
T11	594	0	0	0
T12	3419	0	0	0
T16	1986	50	0	0
T17	1765	0	0	0
T18	707	0	0	0
T19	3071	0	0	0
T26	0	679424	0	0
T30	0	628624	0	0
T45	0	50	0	0
T84	0	128000	0	0
T93	0	1062	0	0
T95	0	556	0	0
T151	0	50	0	0
T152	0	50	0	0
T153	0	50	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	0	0
ALWAYS	63	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	0	1
52		unreachable
63	1	1
64	1	1
65	1	1
66	1	1
67	1	1
			==> MISSING_ELSE
72	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	63	if (req_i)
-2-:	64	if (write_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T26,T84,T30
1	0	Covered	T84,T154,T83
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	1039	1039	0	0
gen_wmask[0].MaskCheck_A	381822793	6579550	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1039	1039	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	6579550	0	0
T26	147585	589824	0	0
T27	393860	0	0	0
T30	0	589824	0	0
T84	0	12800	0	0
T87	3315	0	0	0
T94	0	655360	0	0
T134	1584	0	0	0
T140	0	196608	0	0
T141	0	655360	0	0
T142	0	131072	0	0
T143	1827	0	0	0
T144	1787	0	0	0
T145	1499	0	0	0
T146	203621	0	0	0
T147	1291	0	0	0
T148	401215	0	0	0
T155	0	458752	0	0
T156	0	851968	0	0
T157	0	12800	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	0	0
ALWAYS	63	6	6	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	0	1
52		unreachable
63	1	1
64	1	1
65	1	1
66	1	1
67	1	1
			==> MISSING_ELSE
72	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv' or '../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	63	if (req_i)
-2-:	64	if (write_i)

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T93,T26,T84
1	0	Covered	T93,T84,T83
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	1039	1039	0	0
gen_wmask[0].MaskCheck_A	381822793	6617266	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1039	1039	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	381822793	6617266	0	0
T26	0	589824	0	0
T30	0	590080	0	0
T41	186742	0	0	0
T44	125735	0	0	0
T51	592	0	0	0
T84	0	25600	0	0
T93	97084	606	0	0
T94	0	655360	0	0
T95	160621	0	0	0
T132	392120	0	0	0
T140	0	196608	0	0
T141	0	655360	0	0
T149	271215	0	0	0
T155	0	458752	0	0
T156	0	851968	0	0
T158	0	756	0	0
T159	1263	0	0	0
T160	880	0	0	0
T161	1218	0	0	0