Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	25608477	1		T1	1133		T2	894		T3	288
full_word	7606559	1		T1	155		T2	2302		T3	239

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	33214736	1		T1	1288		T2	3196		T3	527
auto[TlIntgErrCmd]	94	1		T253	3		T254	3		T255	5
auto[TlIntgErrData]	98	1		T253	3		T254	3		T255	3
auto[TlIntgErrBoth]	108	1		T253	4		T254	4		T255	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	28734148	1		T1	1125		T2	1234		T3	421
auto[1]	4480888	1		T1	163		T2	1962		T3	106

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	24879248	1		T1	1115		T2	707		T3	263
auto[TlIntgErrNone]	partial	auto[1]	728949	1		T1	18		T2	187		T3	25
auto[TlIntgErrNone]	full_word	auto[0]	3854760	1		T1	10		T2	527		T3	158
auto[TlIntgErrNone]	full_word	auto[1]	3751779	1		T1	145		T2	1775		T3	81
auto[TlIntgErrCmd]	partial	auto[0]	40	1		T254	1		T255	2		T355	1
auto[TlIntgErrCmd]	partial	auto[1]	46	1		T253	1		T254	2		T255	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T253	1		T363	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T253	1		T361	1		T357	2
auto[TlIntgErrData]	partial	auto[0]	46	1		T255	2		T355	4		T362	3
auto[TlIntgErrData]	partial	auto[1]	44	1		T253	3		T254	2		T255	1
auto[TlIntgErrData]	full_word	auto[0]	3	1		T264	1		T358	2		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1		T254	1		T351	1		T353	2
auto[TlIntgErrBoth]	partial	auto[0]	48	1		T253	2		T254	1		T255	2
auto[TlIntgErrBoth]	partial	auto[1]	56	1		T253	2		T254	3		T355	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T361	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T357	1		T266	1		T360	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	18996	1		T114	661		T73	163		T117	330
full_word	3759202	1		T2	322		T13	10		T16	110

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3777914	1		T2	322		T13	10		T16	110
auto[TlIntgErrCmd]	71	1		T253	1		T254	2		T255	2
auto[TlIntgErrData]	108	1		T253	2		T254	4		T255	4
auto[TlIntgErrBoth]	105	1		T253	5		T254	2		T255	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3753550	1		T2	322		T13	10		T16	110
auto[1]	24648	1		T114	757		T73	224		T117	510

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1137	1		T114	43		T73	15		T117	41
auto[TlIntgErrNone]	partial	auto[1]	17596	1		T114	618		T73	148		T117	289
auto[TlIntgErrNone]	full_word	auto[0]	3752291	1		T2	322		T13	10		T16	110
auto[TlIntgErrNone]	full_word	auto[1]	6890	1		T114	139		T73	76		T117	221
auto[TlIntgErrCmd]	partial	auto[0]	24	1		T254	1		T255	1		T355	2
auto[TlIntgErrCmd]	partial	auto[1]	41	1		T253	1		T254	1		T255	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T357	1		T358	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T362	1		T264	1		T363	1
auto[TlIntgErrData]	partial	auto[0]	52	1		T253	1		T254	1		T255	2
auto[TlIntgErrData]	partial	auto[1]	48	1		T253	1		T254	2		T255	1
auto[TlIntgErrData]	full_word	auto[0]	4	1		T254	1		T351	1		T356	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T255	1		T361	1		T364	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1		T253	3		T254	2		T255	2
auto[TlIntgErrBoth]	partial	auto[1]	61	1		T253	2		T255	2		T362	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T354	1		T360	2		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T359	1		T351	1		T364	1