Unified Coverage Report :: Module :: flash_phy_rd_buf_dep

Module : flash_phy_rd_buf_dep

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.59	100.00	86.36			100.00	100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.59	100.00	86.36			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.59	100.00	86.36			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.71	100.00	90.83			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.59	100.00	86.36			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.59	100.00	86.36			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.54	100.00	90.17			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : flash_phy_rd_buf_dep

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	48	7	7	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
ALWAYS	76	6	6	100.00
ALWAYS	90	3	3	100.00
CONT_ASSIGN	97	1	1	100.00
ALWAYS	116	0	0

47                        always_comb begin
48         1/1              incr_buf_sel = '0;
           Tests:       T1 T2 T3 
49         1/1              decr_buf_sel = '0;
           Tests:       T1 T2 T3 
50         1/1              for (int unsigned i = 0; i < NumBuf; i++) begin
           Tests:       T1 T2 T3 
51         1/1                if (wr_buf_i[i]) begin
           Tests:       T1 T2 T3 
52         1/1                  incr_buf_sel = buf_mux_cnt[i];
           Tests:       T2 T3 T7 
53                            end
                        MISSING_ELSE
54         1/1                if (rd_buf_i[i]) begin
           Tests:       T1 T2 T3 
55         1/1                  decr_buf_sel = buf_mux_cnt[i];
           Tests:       T2 T3 T7 
56                            end
                        MISSING_ELSE
57                          end
58                        end // always_comb
59                      
60                        logic [BufDepCntWidth-1:0] curr_incr_cnt, curr_decr_cnt;
61         1/1            assign curr_incr_cnt = buf_dependency_cnt[incr_buf_sel];
           Tests:       T1 T2 T3 
62         1/1            assign curr_decr_cnt = buf_dependency_cnt[decr_buf_sel];
           Tests:       T1 T2 T3 
63                      
64                        logic cnt_incr, cnt_decr;
65         1/1            assign cnt_incr = en_i & fifo_wr_i & (curr_incr_cnt < RspOrderDepth);
           Tests:       T1 T2 T3 
66         1/1            assign cnt_decr = en_i & fifo_rd_i & (curr_decr_cnt > '0);
           Tests:       T1 T2 T3 
67                      
68                        //assign cnt_decr = fifo_rd_i & (rsp_fifo_vld & data_valid_o) & (curr_decr_cnt > '0);
69                      
70                        logic fin_cnt_incr, fin_cnt_decr;
71         1/1            assign fin_cnt_incr = (incr_buf_sel == decr_buf_sel) ? cnt_incr && !cnt_decr : cnt_incr;
           Tests:       T1 T2 T3 
72         1/1            assign fin_cnt_decr = (incr_buf_sel == decr_buf_sel) ? !cnt_incr && cnt_decr : cnt_decr;
           Tests:       T1 T2 T3 
73                      
74                        // This tells us which buffer currently has a dependency to an item in the rsp_order_fifo
75                        always_ff @(posedge clk_i or negedge rst_ni) begin
76         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
77         1/1                buf_dependency_cnt <= '0;
           Tests:       T1 T2 T3 
78                          end else begin
79         1/1                 if (fin_cnt_incr) begin
           Tests:       T1 T2 T3 
80         1/1                    buf_dependency_cnt[incr_buf_sel] <= curr_incr_cnt + 1'b1;
           Tests:       T2 T3 T7 
81                             end
                        MISSING_ELSE
82         1/1                 if (fin_cnt_decr) begin
           Tests:       T1 T2 T3 
83         1/1                    buf_dependency_cnt[decr_buf_sel] <= curr_decr_cnt - 1'b1;
           Tests:       T2 T3 T7 
84                             end
                        MISSING_ELSE
85                          end
86                        end
87                      
88                        // per buffer dependency determination
89                        always_comb begin
90         1/1              dependency_o = '0;
           Tests:       T1 T2 T3 
91         1/1              for (int i = 0; i < NumBuf; i++) begin
           Tests:       T1 T2 T3 
92         1/1                dependency_o[i] = |buf_dependency_cnt[i];
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // all buffer entries currently have a dependency
97         1/1            assign all_dependency_o = &dependency_o;
           Tests:       T1 T2 T3 
98                      
99                      
100                       // If there are more buffers than there are number of response fifo entries, we an never have
101                       // a fully dependent condition
102                       `ASSERT(BufferDepRsp_A, NumBuf > RspOrderDepth |-> ~all_dependency_o)
103                     
104                       // We should never attempt to increment when at max value
105                       `ASSERT(BufferIncrOverFlow_A, en_i & fifo_wr_i |-> curr_incr_cnt < RspOrderDepth)
106                     
107                       // We should never attempt to decrement when at min value
108                       `ASSERT(BufferDecrUnderRun_A, en_i & fifo_rd_i |-> (curr_decr_cnt > '0))
109                     
110                       // The total number of dependent buffers cannot never exceed the size of response queue
111                       `ifdef INC_ASSERT
112                       //VCS coverage off
113                       // pragma coverage off
114                       logic [31:0] assert_cnt;
115                       always_comb begin
116        unreachable      assert_cnt = '0;
117        unreachable      for (int unsigned i = 0; i < NumBuf; i++) begin
118        unreachable        assert_cnt = assert_cnt + dependency_o[i];

---

Cond Coverage for Module : flash_phy_rd_buf_dep

	Total	Covered	Percent
Conditions	22	19	86.36
Logical	22	19	86.36
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T7

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T7
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T7

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T13,T16
1	1	Covered	T2,T3,T7

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T13,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T7

---

Branch Coverage for Module : flash_phy_rd_buf_dep

	Line No.	Total	Covered	Percent
Branches		13	13	100.00
TERNARY	71	2	2	100.00
TERNARY	72	2	2	100.00
IF	51	2	2	100.00
IF	54	2	2	100.00
IF	76	5	5	100.00

71           assign fin_cnt_incr = (incr_buf_sel == decr_buf_sel) ? cnt_incr && !cnt_decr : cnt_incr;
                                                                  -1-  
                                                                  ==>  
                                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T7

72           assign fin_cnt_decr = (incr_buf_sel == decr_buf_sel) ? !cnt_incr && cnt_decr : cnt_decr;
                                                                  -1-  
                                                                  ==>  
                                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T7

51               if (wr_buf_i[i]) begin
                 -1-  
52                 incr_buf_sel = buf_mux_cnt[i];
                   ==>
53               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

54               if (rd_buf_i[i]) begin
                 -1-  
55                 decr_buf_sel = buf_mux_cnt[i];
                   ==>
56               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

76             if (!rst_ni) begin
               -1-  
77               buf_dependency_cnt <= '0;
                 ==>
78             end else begin
79                if (fin_cnt_incr) begin
                  -2-  
80                   buf_dependency_cnt[incr_buf_sel] <= curr_incr_cnt + 1'b1;
                     ==>
81                end
                  MISSING_ELSE
                  ==>
82                if (fin_cnt_decr) begin
                  -3-  
83                   buf_dependency_cnt[decr_buf_sel] <= curr_decr_cnt - 1'b1;
                     ==>
84                end
                  MISSING_ELSE
                  ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	-	Covered	T1,T2,T3
0	-	1	Covered	T2,T3,T7
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_rd_buf_dep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferDecrUnderRun_A	773953776	6653232	0	0
BufferDepRsp_A	773953776	772230918	0	0
BufferIncrOverFlow_A	773953776	6653244	0	0
DepBufferRspOrder_A	773953780	16737296	0	0

BufferDecrUnderRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	773953776	6653232	0	0
T2	21350	803	0	0
T3	5106	146	0	0
T7	4530	20	0	0
T13	2650	10	0	0
T14	110470	942	0	0
T15	193114	2376	0	0
T16	0	165	0	0
T17	0	1151	0	0
T20	2946	146	0	0
T21	3844	146	0	0
T22	358004	0	0	0
T23	190834	42	0	0
T27	0	52	0	0
T43	0	9503	0	0
T65	0	11397	0	0

BufferDepRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	773953776	772230918	0	0
T1	7748	7594	0	0
T2	21350	21176	0	0
T3	5106	4916	0	0
T7	4530	4346	0	0
T13	2650	2464	0	0
T14	110470	110292	0	0
T15	193114	192928	0	0
T20	2946	2820	0	0
T21	3844	3720	0	0
T22	358004	357876	0	0

BufferIncrOverFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	773953776	6653244	0	0
T2	21350	803	0	0
T3	5106	146	0	0
T7	4530	20	0	0
T13	2650	10	0	0
T14	110470	942	0	0
T15	193114	2376	0	0
T16	0	165	0	0
T17	0	1151	0	0
T20	2946	146	0	0
T21	3844	146	0	0
T22	358004	0	0	0
T23	190834	42	0	0
T27	0	52	0	0
T43	0	9503	0	0
T65	0	11397	0	0

DepBufferRspOrder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	773953780	16737296	0	0
T1	3874	32	0	0
T2	21350	835	0	0
T3	5106	178	0	0
T7	4530	52	0	0
T13	2650	42	0	0
T14	110470	974	0	0
T15	193114	2408	0	0
T16	0	66	0	0
T17	0	596	0	0
T20	2946	178	0	0
T21	3844	178	0	0
T22	358004	32	0	0
T23	95417	17	0	0
T27	0	52	0	0
T43	0	9503	0	0
T65	0	11397	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	48	7	7	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
ALWAYS	76	6	6	100.00
ALWAYS	90	3	3	100.00
CONT_ASSIGN	97	1	1	100.00
ALWAYS	116	0	0

47                        always_comb begin
48         1/1              incr_buf_sel = '0;
           Tests:       T1 T2 T3 
49         1/1              decr_buf_sel = '0;
           Tests:       T1 T2 T3 
50         1/1              for (int unsigned i = 0; i < NumBuf; i++) begin
           Tests:       T1 T2 T3 
51         1/1                if (wr_buf_i[i]) begin
           Tests:       T1 T2 T3 
52         1/1                  incr_buf_sel = buf_mux_cnt[i];
           Tests:       T2 T3 T7 
53                            end
                        MISSING_ELSE
54         1/1                if (rd_buf_i[i]) begin
           Tests:       T1 T2 T3 
55         1/1                  decr_buf_sel = buf_mux_cnt[i];
           Tests:       T2 T3 T7 
56                            end
                        MISSING_ELSE
57                          end
58                        end // always_comb
59                      
60                        logic [BufDepCntWidth-1:0] curr_incr_cnt, curr_decr_cnt;
61         1/1            assign curr_incr_cnt = buf_dependency_cnt[incr_buf_sel];
           Tests:       T1 T2 T3 
62         1/1            assign curr_decr_cnt = buf_dependency_cnt[decr_buf_sel];
           Tests:       T1 T2 T3 
63                      
64                        logic cnt_incr, cnt_decr;
65         1/1            assign cnt_incr = en_i & fifo_wr_i & (curr_incr_cnt < RspOrderDepth);
           Tests:       T1 T2 T3 
66         1/1            assign cnt_decr = en_i & fifo_rd_i & (curr_decr_cnt > '0);
           Tests:       T1 T2 T3 
67                      
68                        //assign cnt_decr = fifo_rd_i & (rsp_fifo_vld & data_valid_o) & (curr_decr_cnt > '0);
69                      
70                        logic fin_cnt_incr, fin_cnt_decr;
71         1/1            assign fin_cnt_incr = (incr_buf_sel == decr_buf_sel) ? cnt_incr && !cnt_decr : cnt_incr;
           Tests:       T1 T2 T3 
72         1/1            assign fin_cnt_decr = (incr_buf_sel == decr_buf_sel) ? !cnt_incr && cnt_decr : cnt_decr;
           Tests:       T1 T2 T3 
73                      
74                        // This tells us which buffer currently has a dependency to an item in the rsp_order_fifo
75                        always_ff @(posedge clk_i or negedge rst_ni) begin
76         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
77         1/1                buf_dependency_cnt <= '0;
           Tests:       T1 T2 T3 
78                          end else begin
79         1/1                 if (fin_cnt_incr) begin
           Tests:       T1 T2 T3 
80         1/1                    buf_dependency_cnt[incr_buf_sel] <= curr_incr_cnt + 1'b1;
           Tests:       T2 T3 T7 
81                             end
                        MISSING_ELSE
82         1/1                 if (fin_cnt_decr) begin
           Tests:       T1 T2 T3 
83         1/1                    buf_dependency_cnt[decr_buf_sel] <= curr_decr_cnt - 1'b1;
           Tests:       T2 T3 T7 
84                             end
                        MISSING_ELSE
85                          end
86                        end
87                      
88                        // per buffer dependency determination
89                        always_comb begin
90         1/1              dependency_o = '0;
           Tests:       T1 T2 T3 
91         1/1              for (int i = 0; i < NumBuf; i++) begin
           Tests:       T1 T2 T3 
92         1/1                dependency_o[i] = |buf_dependency_cnt[i];
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // all buffer entries currently have a dependency
97         1/1            assign all_dependency_o = &dependency_o;
           Tests:       T1 T2 T3 
98                      
99                      
100                       // If there are more buffers than there are number of response fifo entries, we an never have
101                       // a fully dependent condition
102                       `ASSERT(BufferDepRsp_A, NumBuf > RspOrderDepth |-> ~all_dependency_o)
103                     
104                       // We should never attempt to increment when at max value
105                       `ASSERT(BufferIncrOverFlow_A, en_i & fifo_wr_i |-> curr_incr_cnt < RspOrderDepth)
106                     
107                       // We should never attempt to decrement when at min value
108                       `ASSERT(BufferDecrUnderRun_A, en_i & fifo_rd_i |-> (curr_decr_cnt > '0))
109                     
110                       // The total number of dependent buffers cannot never exceed the size of response queue
111                       `ifdef INC_ASSERT
112                       //VCS coverage off
113                       // pragma coverage off
114                       logic [31:0] assert_cnt;
115                       always_comb begin
116        unreachable      assert_cnt = '0;
117        unreachable      for (int unsigned i = 0; i < NumBuf; i++) begin
118        unreachable        assert_cnt = assert_cnt + dependency_o[i];

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

	Total	Covered	Percent
Conditions	22	19	86.36
Logical	22	19	86.36
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T7

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T7
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T7

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T13,T16
1	1	Covered	T2,T3,T7

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T2,T3,T7
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T13,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T7

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

	Line No.	Total	Covered	Percent
Branches		13	13	100.00
TERNARY	71	2	2	100.00
TERNARY	72	2	2	100.00
IF	51	2	2	100.00
IF	54	2	2	100.00
IF	76	5	5	100.00

71           assign fin_cnt_incr = (incr_buf_sel == decr_buf_sel) ? cnt_incr && !cnt_decr : cnt_incr;
                                                                  -1-  
                                                                  ==>  
                                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T7

72           assign fin_cnt_decr = (incr_buf_sel == decr_buf_sel) ? !cnt_incr && cnt_decr : cnt_decr;
                                                                  -1-  
                                                                  ==>  
                                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T7

51               if (wr_buf_i[i]) begin
                 -1-  
52                 incr_buf_sel = buf_mux_cnt[i];
                   ==>
53               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

54               if (rd_buf_i[i]) begin
                 -1-  
55                 decr_buf_sel = buf_mux_cnt[i];
                   ==>
56               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

76             if (!rst_ni) begin
               -1-  
77               buf_dependency_cnt <= '0;
                 ==>
78             end else begin
79                if (fin_cnt_incr) begin
                  -2-  
80                   buf_dependency_cnt[incr_buf_sel] <= curr_incr_cnt + 1'b1;
                     ==>
81                end
                  MISSING_ELSE
                  ==>
82                if (fin_cnt_decr) begin
                  -3-  
83                   buf_dependency_cnt[decr_buf_sel] <= curr_decr_cnt - 1'b1;
                     ==>
84                end
                  MISSING_ELSE
                  ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T7
0	0	-	Covered	T1,T2,T3
0	-	1	Covered	T2,T3,T7
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferDecrUnderRun_A	386976888	3419839	0	0
BufferDepRsp_A	386976888	386115459	0	0
BufferIncrOverFlow_A	386976888	3419846	0	0
DepBufferRspOrder_A	386976890	8946163	0	0

BufferDecrUnderRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	3419839	0	0
T2	10675	479	0	0
T3	2553	146	0	0
T7	2265	20	0	0
T13	1325	10	0	0
T14	55235	626	0	0
T15	96557	1028	0	0
T16	0	99	0	0
T17	0	555	0	0
T20	1473	0	0	0
T21	1922	146	0	0
T22	179002	0	0	0
T23	95417	25	0	0

BufferDepRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	386115459	0	0
T1	3874	3797	0	0
T2	10675	10588	0	0
T3	2553	2458	0	0
T7	2265	2173	0	0
T13	1325	1232	0	0
T14	55235	55146	0	0
T15	96557	96464	0	0
T20	1473	1410	0	0
T21	1922	1860	0	0
T22	179002	178938	0	0

BufferIncrOverFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	3419846	0	0
T2	10675	479	0	0
T3	2553	146	0	0
T7	2265	20	0	0
T13	1325	10	0	0
T14	55235	626	0	0
T15	96557	1028	0	0
T16	0	99	0	0
T17	0	555	0	0
T20	1473	0	0	0
T21	1922	146	0	0
T22	179002	0	0	0
T23	95417	25	0	0

DepBufferRspOrder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976890	8946163	0	0
T1	3874	32	0	0
T2	10675	511	0	0
T3	2553	178	0	0
T7	2265	52	0	0
T13	1325	42	0	0
T14	55235	658	0	0
T15	96557	1060	0	0
T20	1473	32	0	0
T21	1922	178	0	0
T22	179002	32	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	48	7	7	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
ALWAYS	76	6	6	100.00
ALWAYS	90	3	3	100.00
CONT_ASSIGN	97	1	1	100.00
ALWAYS	116	0	0

47                        always_comb begin
48         1/1              incr_buf_sel = '0;
           Tests:       T1 T2 T3 
49         1/1              decr_buf_sel = '0;
           Tests:       T1 T2 T3 
50         1/1              for (int unsigned i = 0; i < NumBuf; i++) begin
           Tests:       T1 T2 T3 
51         1/1                if (wr_buf_i[i]) begin
           Tests:       T1 T2 T3 
52         1/1                  incr_buf_sel = buf_mux_cnt[i];
           Tests:       T2 T20 T14 
53                            end
                        MISSING_ELSE
54         1/1                if (rd_buf_i[i]) begin
           Tests:       T1 T2 T3 
55         1/1                  decr_buf_sel = buf_mux_cnt[i];
           Tests:       T2 T20 T14 
56                            end
                        MISSING_ELSE
57                          end
58                        end // always_comb
59                      
60                        logic [BufDepCntWidth-1:0] curr_incr_cnt, curr_decr_cnt;
61         1/1            assign curr_incr_cnt = buf_dependency_cnt[incr_buf_sel];
           Tests:       T1 T2 T3 
62         1/1            assign curr_decr_cnt = buf_dependency_cnt[decr_buf_sel];
           Tests:       T1 T2 T3 
63                      
64                        logic cnt_incr, cnt_decr;
65         1/1            assign cnt_incr = en_i & fifo_wr_i & (curr_incr_cnt < RspOrderDepth);
           Tests:       T1 T2 T3 
66         1/1            assign cnt_decr = en_i & fifo_rd_i & (curr_decr_cnt > '0);
           Tests:       T1 T2 T3 
67                      
68                        //assign cnt_decr = fifo_rd_i & (rsp_fifo_vld & data_valid_o) & (curr_decr_cnt > '0);
69                      
70                        logic fin_cnt_incr, fin_cnt_decr;
71         1/1            assign fin_cnt_incr = (incr_buf_sel == decr_buf_sel) ? cnt_incr && !cnt_decr : cnt_incr;
           Tests:       T1 T2 T3 
72         1/1            assign fin_cnt_decr = (incr_buf_sel == decr_buf_sel) ? !cnt_incr && cnt_decr : cnt_decr;
           Tests:       T1 T2 T3 
73                      
74                        // This tells us which buffer currently has a dependency to an item in the rsp_order_fifo
75                        always_ff @(posedge clk_i or negedge rst_ni) begin
76         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
77         1/1                buf_dependency_cnt <= '0;
           Tests:       T1 T2 T3 
78                          end else begin
79         1/1                 if (fin_cnt_incr) begin
           Tests:       T1 T2 T3 
80         1/1                    buf_dependency_cnt[incr_buf_sel] <= curr_incr_cnt + 1'b1;
           Tests:       T2 T20 T14 
81                             end
                        MISSING_ELSE
82         1/1                 if (fin_cnt_decr) begin
           Tests:       T1 T2 T3 
83         1/1                    buf_dependency_cnt[decr_buf_sel] <= curr_decr_cnt - 1'b1;
           Tests:       T2 T20 T14 
84                             end
                        MISSING_ELSE
85                          end
86                        end
87                      
88                        // per buffer dependency determination
89                        always_comb begin
90         1/1              dependency_o = '0;
           Tests:       T1 T2 T3 
91         1/1              for (int i = 0; i < NumBuf; i++) begin
           Tests:       T1 T2 T3 
92         1/1                dependency_o[i] = |buf_dependency_cnt[i];
           Tests:       T1 T2 T3 
93                          end
94                        end
95                      
96                        // all buffer entries currently have a dependency
97         1/1            assign all_dependency_o = &dependency_o;
           Tests:       T1 T2 T3 
98                      
99                      
100                       // If there are more buffers than there are number of response fifo entries, we an never have
101                       // a fully dependent condition
102                       `ASSERT(BufferDepRsp_A, NumBuf > RspOrderDepth |-> ~all_dependency_o)
103                     
104                       // We should never attempt to increment when at max value
105                       `ASSERT(BufferIncrOverFlow_A, en_i & fifo_wr_i |-> curr_incr_cnt < RspOrderDepth)
106                     
107                       // We should never attempt to decrement when at min value
108                       `ASSERT(BufferDecrUnderRun_A, en_i & fifo_rd_i |-> (curr_decr_cnt > '0))
109                     
110                       // The total number of dependent buffers cannot never exceed the size of response queue
111                       `ifdef INC_ASSERT
112                       //VCS coverage off
113                       // pragma coverage off
114                       logic [31:0] assert_cnt;
115                       always_comb begin
116        unreachable      assert_cnt = '0;
117        unreachable      for (int unsigned i = 0; i < NumBuf; i++) begin
118        unreachable        assert_cnt = assert_cnt + dependency_o[i];

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

	Total	Covered	Percent
Conditions	22	19	86.36
Logical	22	19	86.36
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T120,T119,T81
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T2,T20,T14

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T20,T14
1	1	0	Not Covered
1	1	1	Covered	T2,T20,T14

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T2,T20,T14
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T16,T65
1	1	Covered	T2,T20,T14

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T2,T20,T14
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T16,T65
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T20,T14

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

	Line No.	Total	Covered	Percent
Branches		13	13	100.00
TERNARY	71	2	2	100.00
TERNARY	72	2	2	100.00
IF	51	2	2	100.00
IF	54	2	2	100.00
IF	76	5	5	100.00

71           assign fin_cnt_incr = (incr_buf_sel == decr_buf_sel) ? cnt_incr && !cnt_decr : cnt_incr;
                                                                  -1-  
                                                                  ==>  
                                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T20,T14

72           assign fin_cnt_decr = (incr_buf_sel == decr_buf_sel) ? !cnt_incr && cnt_decr : cnt_decr;
                                                                  -1-  
                                                                  ==>  
                                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T20,T14

51               if (wr_buf_i[i]) begin
                 -1-  
52                 incr_buf_sel = buf_mux_cnt[i];
                   ==>
53               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T20,T14
0	Covered	T1,T2,T3

54               if (rd_buf_i[i]) begin
                 -1-  
55                 decr_buf_sel = buf_mux_cnt[i];
                   ==>
56               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T20,T14
0	Covered	T1,T2,T3

76             if (!rst_ni) begin
               -1-  
77               buf_dependency_cnt <= '0;
                 ==>
78             end else begin
79                if (fin_cnt_incr) begin
                  -2-  
80                   buf_dependency_cnt[incr_buf_sel] <= curr_incr_cnt + 1'b1;
                     ==>
81                end
                  MISSING_ELSE
                  ==>
82                if (fin_cnt_decr) begin
                  -3-  
83                   buf_dependency_cnt[decr_buf_sel] <= curr_decr_cnt - 1'b1;
                     ==>
84                end
                  MISSING_ELSE
                  ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T20,T14
0	0	-	Covered	T1,T2,T3
0	-	1	Covered	T2,T20,T14
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferDecrUnderRun_A	386976888	3233393	0	0
BufferDepRsp_A	386976888	386115459	0	0
BufferIncrOverFlow_A	386976888	3233398	0	0
DepBufferRspOrder_A	386976890	7791133	0	0

BufferDecrUnderRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	3233393	0	0
T2	10675	324	0	0
T3	2553	0	0	0
T7	2265	0	0	0
T13	1325	0	0	0
T14	55235	316	0	0
T15	96557	1348	0	0
T16	0	66	0	0
T17	0	596	0	0
T20	1473	146	0	0
T21	1922	0	0	0
T22	179002	0	0	0
T23	95417	17	0	0
T27	0	52	0	0
T43	0	9503	0	0
T65	0	11397	0	0

BufferDepRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	386115459	0	0
T1	3874	3797	0	0
T2	10675	10588	0	0
T3	2553	2458	0	0
T7	2265	2173	0	0
T13	1325	1232	0	0
T14	55235	55146	0	0
T15	96557	96464	0	0
T20	1473	1410	0	0
T21	1922	1860	0	0
T22	179002	178938	0	0

BufferIncrOverFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	3233398	0	0
T2	10675	324	0	0
T3	2553	0	0	0
T7	2265	0	0	0
T13	1325	0	0	0
T14	55235	316	0	0
T15	96557	1348	0	0
T16	0	66	0	0
T17	0	596	0	0
T20	1473	146	0	0
T21	1922	0	0	0
T22	179002	0	0	0
T23	95417	17	0	0
T27	0	52	0	0
T43	0	9503	0	0
T65	0	11397	0	0

DepBufferRspOrder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976890	7791133	0	0
T2	10675	324	0	0
T3	2553	0	0	0
T7	2265	0	0	0
T13	1325	0	0	0
T14	55235	316	0	0
T15	96557	1348	0	0
T16	0	66	0	0
T17	0	596	0	0
T20	1473	146	0	0
T21	1922	0	0	0
T22	179002	0	0	0
T23	95417	17	0	0
T27	0	52	0	0
T43	0	9503	0	0
T65	0	11397	0	0