Module Definition
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Module : prim_secded_inv_39_32_enc
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_39_32_enc.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_to_prog_fifo.u_tlul_data_integ_enc_instr.u_data_gen 0.00 0.00
tb.dut.u_to_prog_fifo.u_tlul_data_integ_enc_data.u_data_gen 0.00 0.00
tb.dut.u_to_rd_fifo.u_tlul_data_integ_enc_instr.u_data_gen 0.00 0.00
tb.dut.u_to_rd_fifo.u_tlul_data_integ_enc_data.u_data_gen 0.00 0.00
tb.dut.u_flash_ctrl_rd.u_bus_intg.u_data_gen 0.00 0.00
tb.dut.u_tl_adapter_eflash.u_tlul_data_integ_enc_instr.u_data_gen 0.00 0.00
tb.dut.u_tl_adapter_eflash.u_tlul_data_integ_enc_data.u_data_gen 0.00 0.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_bus_inv_data_intg.u_data_gen 0.00 0.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_bus_inv_data_intg.u_data_gen 0.00 0.00
tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen 100.00 100.00
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen 100.00 100.00
tb.dut.u_flash_hw_if.u_bus_intg.u_data_gen 100.00 100.00
tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen 100.00 100.00
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_rd.gen_bus_words_intg[0].u_bus_intg.u_data_gen 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_rd.gen_bus_words_intg[1].u_bus_intg.u_data_gen 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_rd.gen_bus_words_intg[0].u_bus_intg.u_data_gen 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_rd.gen_bus_words_intg[1].u_bus_intg.u_data_gen 100.00 100.00



Module Instance : tb.dut.u_to_prog_fifo.u_tlul_data_integ_enc_instr.u_data_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_tlul_data_integ_enc_instr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_to_prog_fifo.u_tlul_data_integ_enc_data.u_data_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_tlul_data_integ_enc_data


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_to_rd_fifo.u_tlul_data_integ_enc_instr.u_data_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_tlul_data_integ_enc_instr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_to_rd_fifo.u_tlul_data_integ_enc_data.u_data_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_tlul_data_integ_enc_data


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_ctrl_rd.u_bus_intg.u_data_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_bus_intg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tl_adapter_eflash.u_tlul_data_integ_enc_instr.u_data_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_tlul_data_integ_enc_instr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tl_adapter_eflash.u_tlul_data_integ_enc_data.u_data_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_tlul_data_integ_enc_data


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_bus_inv_data_intg.u_data_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_bus_inv_data_intg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_bus_inv_data_intg.u_data_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_bus_inv_data_intg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_data_intg.u_tlul_data_integ_enc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_data_intg.u_tlul_data_integ_enc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_bus_intg.u_data_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_bus_intg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_data_intg.u_tlul_data_integ_enc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_data_intg.u_tlul_data_integ_enc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_data_intg.u_tlul_data_integ_enc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_rd.gen_bus_words_intg[0].u_bus_intg.u_data_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_rd.gen_bus_words_intg[0].u_bus_intg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_rd.gen_bus_words_intg[1].u_bus_intg.u_data_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_rd.gen_bus_words_intg[1].u_bus_intg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_rd.gen_bus_words_intg[0].u_bus_intg.u_data_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_rd.gen_bus_words_intg[0].u_bus_intg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_rd.gen_bus_words_intg[1].u_bus_intg.u_data_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_rd.gen_bus_words_intg[1].u_bus_intg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_secded_inv_39_32_enc
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS1399100.00

12 always_comb begin : p_encode 13 1/1 data_o = 39'(data_i); Tests: T1 T2 T3  14 1/1 data_o[32] = ^(data_o & 39'h002606BD25); Tests: T1 T2 T3  15 1/1 data_o[33] = ^(data_o & 39'h00DEBA8050); Tests: T1 T2 T3  16 1/1 data_o[34] = ^(data_o & 39'h00413D89AA); Tests: T1 T2 T3  17 1/1 data_o[35] = ^(data_o & 39'h0031234ED1); Tests: T1 T2 T3  18 1/1 data_o[36] = ^(data_o & 39'h00C2C1323B); Tests: T1 T2 T3  19 1/1 data_o[37] = ^(data_o & 39'h002DCC624C); Tests: T1 T2 T3  20 1/1 data_o[38] = ^(data_o & 39'h0098505586); Tests: T1 T2 T3  21 1/1 data_o ^= 39'h2A00000000; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_tlul_data_integ_enc_instr.u_data_gen
Line No.TotalCoveredPercent
TOTAL900.00
ALWAYS13900.00

12 always_comb begin : p_encode 13 0/1 ==> data_o = 39'(data_i); 14 0/1 ==> data_o[32] = ^(data_o & 39'h002606BD25); 15 0/1 ==> data_o[33] = ^(data_o & 39'h00DEBA8050); 16 0/1 ==> data_o[34] = ^(data_o & 39'h00413D89AA); 17 0/1 ==> data_o[35] = ^(data_o & 39'h0031234ED1); 18 0/1 ==> data_o[36] = ^(data_o & 39'h00C2C1323B); 19 0/1 ==> data_o[37] = ^(data_o & 39'h002DCC624C); 20 0/1 ==> data_o[38] = ^(data_o & 39'h0098505586); 21 0/1 ==> data_o ^= 39'h2A00000000;
Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_tlul_data_integ_enc_data.u_data_gen
Line No.TotalCoveredPercent
TOTAL900.00
ALWAYS13900.00

12 always_comb begin : p_encode 13 0/1 ==> data_o = 39'(data_i); 14 0/1 ==> data_o[32] = ^(data_o & 39'h002606BD25); 15 0/1 ==> data_o[33] = ^(data_o & 39'h00DEBA8050); 16 0/1 ==> data_o[34] = ^(data_o & 39'h00413D89AA); 17 0/1 ==> data_o[35] = ^(data_o & 39'h0031234ED1); 18 0/1 ==> data_o[36] = ^(data_o & 39'h00C2C1323B); 19 0/1 ==> data_o[37] = ^(data_o & 39'h002DCC624C); 20 0/1 ==> data_o[38] = ^(data_o & 39'h0098505586); 21 0/1 ==> data_o ^= 39'h2A00000000;
Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_tlul_data_integ_enc_instr.u_data_gen
Line No.TotalCoveredPercent
TOTAL900.00
ALWAYS13900.00

12 always_comb begin : p_encode 13 0/1 ==> data_o = 39'(data_i); 14 0/1 ==> data_o[32] = ^(data_o & 39'h002606BD25); 15 0/1 ==> data_o[33] = ^(data_o & 39'h00DEBA8050); 16 0/1 ==> data_o[34] = ^(data_o & 39'h00413D89AA); 17 0/1 ==> data_o[35] = ^(data_o & 39'h0031234ED1); 18 0/1 ==> data_o[36] = ^(data_o & 39'h00C2C1323B); 19 0/1 ==> data_o[37] = ^(data_o & 39'h002DCC624C); 20 0/1 ==> data_o[38] = ^(data_o & 39'h0098505586); 21 0/1 ==> data_o ^= 39'h2A00000000;
Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_tlul_data_integ_enc_data.u_data_gen
Line No.TotalCoveredPercent
TOTAL900.00
ALWAYS13900.00

12 always_comb begin : p_encode 13 0/1 ==> data_o = 39'(data_i); 14 0/1 ==> data_o[32] = ^(data_o & 39'h002606BD25); 15 0/1 ==> data_o[33] = ^(data_o & 39'h00DEBA8050); 16 0/1 ==> data_o[34] = ^(data_o & 39'h00413D89AA); 17 0/1 ==> data_o[35] = ^(data_o & 39'h0031234ED1); 18 0/1 ==> data_o[36] = ^(data_o & 39'h00C2C1323B); 19 0/1 ==> data_o[37] = ^(data_o & 39'h002DCC624C); 20 0/1 ==> data_o[38] = ^(data_o & 39'h0098505586); 21 0/1 ==> data_o ^= 39'h2A00000000;
Line Coverage for Instance : tb.dut.u_flash_ctrl_rd.u_bus_intg.u_data_gen
Line No.TotalCoveredPercent
TOTAL900.00
ALWAYS13900.00

12 always_comb begin : p_encode 13 0/1 ==> data_o = 39'(data_i); 14 0/1 ==> data_o[32] = ^(data_o & 39'h002606BD25); 15 0/1 ==> data_o[33] = ^(data_o & 39'h00DEBA8050); 16 0/1 ==> data_o[34] = ^(data_o & 39'h00413D89AA); 17 0/1 ==> data_o[35] = ^(data_o & 39'h0031234ED1); 18 0/1 ==> data_o[36] = ^(data_o & 39'h00C2C1323B); 19 0/1 ==> data_o[37] = ^(data_o & 39'h002DCC624C); 20 0/1 ==> data_o[38] = ^(data_o & 39'h0098505586); 21 0/1 ==> data_o ^= 39'h2A00000000;
Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_tlul_data_integ_enc_instr.u_data_gen
Line No.TotalCoveredPercent
TOTAL900.00
ALWAYS13900.00

12 always_comb begin : p_encode 13 0/1 ==> data_o = 39'(data_i); 14 0/1 ==> data_o[32] = ^(data_o & 39'h002606BD25); 15 0/1 ==> data_o[33] = ^(data_o & 39'h00DEBA8050); 16 0/1 ==> data_o[34] = ^(data_o & 39'h00413D89AA); 17 0/1 ==> data_o[35] = ^(data_o & 39'h0031234ED1); 18 0/1 ==> data_o[36] = ^(data_o & 39'h00C2C1323B); 19 0/1 ==> data_o[37] = ^(data_o & 39'h002DCC624C); 20 0/1 ==> data_o[38] = ^(data_o & 39'h0098505586); 21 0/1 ==> data_o ^= 39'h2A00000000;
Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_tlul_data_integ_enc_data.u_data_gen
Line No.TotalCoveredPercent
TOTAL900.00
ALWAYS13900.00

12 always_comb begin : p_encode 13 0/1 ==> data_o = 39'(data_i); 14 0/1 ==> data_o[32] = ^(data_o & 39'h002606BD25); 15 0/1 ==> data_o[33] = ^(data_o & 39'h00DEBA8050); 16 0/1 ==> data_o[34] = ^(data_o & 39'h00413D89AA); 17 0/1 ==> data_o[35] = ^(data_o & 39'h0031234ED1); 18 0/1 ==> data_o[36] = ^(data_o & 39'h00C2C1323B); 19 0/1 ==> data_o[37] = ^(data_o & 39'h002DCC624C); 20 0/1 ==> data_o[38] = ^(data_o & 39'h0098505586); 21 0/1 ==> data_o ^= 39'h2A00000000;
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_bus_inv_data_intg.u_data_gen
Line No.TotalCoveredPercent
TOTAL900.00
ALWAYS13900.00

12 always_comb begin : p_encode 13 0/1 ==> data_o = 39'(data_i); 14 0/1 ==> data_o[32] = ^(data_o & 39'h002606BD25); 15 0/1 ==> data_o[33] = ^(data_o & 39'h00DEBA8050); 16 0/1 ==> data_o[34] = ^(data_o & 39'h00413D89AA); 17 0/1 ==> data_o[35] = ^(data_o & 39'h0031234ED1); 18 0/1 ==> data_o[36] = ^(data_o & 39'h00C2C1323B); 19 0/1 ==> data_o[37] = ^(data_o & 39'h002DCC624C); 20 0/1 ==> data_o[38] = ^(data_o & 39'h0098505586); 21 0/1 ==> data_o ^= 39'h2A00000000;
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_bus_inv_data_intg.u_data_gen
Line No.TotalCoveredPercent
TOTAL900.00
ALWAYS13900.00

12 always_comb begin : p_encode 13 0/1 ==> data_o = 39'(data_i); 14 0/1 ==> data_o[32] = ^(data_o & 39'h002606BD25); 15 0/1 ==> data_o[33] = ^(data_o & 39'h00DEBA8050); 16 0/1 ==> data_o[34] = ^(data_o & 39'h00413D89AA); 17 0/1 ==> data_o[35] = ^(data_o & 39'h0031234ED1); 18 0/1 ==> data_o[36] = ^(data_o & 39'h00C2C1323B); 19 0/1 ==> data_o[37] = ^(data_o & 39'h002DCC624C); 20 0/1 ==> data_o[38] = ^(data_o & 39'h0098505586); 21 0/1 ==> data_o ^= 39'h2A00000000;
Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS1399100.00

12 always_comb begin : p_encode 13 1/1 data_o = 39'(data_i); Tests: T1 T2 T3  14 1/1 data_o[32] = ^(data_o & 39'h002606BD25); Tests: T1 T2 T3  15 1/1 data_o[33] = ^(data_o & 39'h00DEBA8050); Tests: T1 T2 T3  16 1/1 data_o[34] = ^(data_o & 39'h00413D89AA); Tests: T1 T2 T3  17 1/1 data_o[35] = ^(data_o & 39'h0031234ED1); Tests: T1 T2 T3  18 1/1 data_o[36] = ^(data_o & 39'h00C2C1323B); Tests: T1 T2 T3  19 1/1 data_o[37] = ^(data_o & 39'h002DCC624C); Tests: T1 T2 T3  20 1/1 data_o[38] = ^(data_o & 39'h0098505586); Tests: T1 T2 T3  21 1/1 data_o ^= 39'h2A00000000; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS1399100.00

12 always_comb begin : p_encode 13 1/1 data_o = 39'(data_i); Tests: T1 T2 T3  14 1/1 data_o[32] = ^(data_o & 39'h002606BD25); Tests: T1 T2 T3  15 1/1 data_o[33] = ^(data_o & 39'h00DEBA8050); Tests: T1 T2 T3  16 1/1 data_o[34] = ^(data_o & 39'h00413D89AA); Tests: T1 T2 T3  17 1/1 data_o[35] = ^(data_o & 39'h0031234ED1); Tests: T1 T2 T3  18 1/1 data_o[36] = ^(data_o & 39'h00C2C1323B); Tests: T1 T2 T3  19 1/1 data_o[37] = ^(data_o & 39'h002DCC624C); Tests: T1 T2 T3  20 1/1 data_o[38] = ^(data_o & 39'h0098505586); Tests: T1 T2 T3  21 1/1 data_o ^= 39'h2A00000000; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_flash_hw_if.u_bus_intg.u_data_gen
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS1399100.00

12 always_comb begin : p_encode 13 1/1 data_o = 39'(data_i); Tests: T1 T2 T3  14 1/1 data_o[32] = ^(data_o & 39'h002606BD25); Tests: T1 T2 T3  15 1/1 data_o[33] = ^(data_o & 39'h00DEBA8050); Tests: T1 T2 T3  16 1/1 data_o[34] = ^(data_o & 39'h00413D89AA); Tests: T1 T2 T3  17 1/1 data_o[35] = ^(data_o & 39'h0031234ED1); Tests: T1 T2 T3  18 1/1 data_o[36] = ^(data_o & 39'h00C2C1323B); Tests: T1 T2 T3  19 1/1 data_o[37] = ^(data_o & 39'h002DCC624C); Tests: T1 T2 T3  20 1/1 data_o[38] = ^(data_o & 39'h0098505586); Tests: T1 T2 T3  21 1/1 data_o ^= 39'h2A00000000; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS1399100.00

12 always_comb begin : p_encode 13 1/1 data_o = 39'(data_i); Tests: T1 T2 T3  14 1/1 data_o[32] = ^(data_o & 39'h002606BD25); Tests: T1 T2 T3  15 1/1 data_o[33] = ^(data_o & 39'h00DEBA8050); Tests: T1 T2 T3  16 1/1 data_o[34] = ^(data_o & 39'h00413D89AA); Tests: T1 T2 T3  17 1/1 data_o[35] = ^(data_o & 39'h0031234ED1); Tests: T1 T2 T3  18 1/1 data_o[36] = ^(data_o & 39'h00C2C1323B); Tests: T1 T2 T3  19 1/1 data_o[37] = ^(data_o & 39'h002DCC624C); Tests: T1 T2 T3  20 1/1 data_o[38] = ^(data_o & 39'h0098505586); Tests: T1 T2 T3  21 1/1 data_o ^= 39'h2A00000000; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS1399100.00

12 always_comb begin : p_encode 13 1/1 data_o = 39'(data_i); Tests: T1 T2 T3  14 1/1 data_o[32] = ^(data_o & 39'h002606BD25); Tests: T1 T2 T3  15 1/1 data_o[33] = ^(data_o & 39'h00DEBA8050); Tests: T1 T2 T3  16 1/1 data_o[34] = ^(data_o & 39'h00413D89AA); Tests: T1 T2 T3  17 1/1 data_o[35] = ^(data_o & 39'h0031234ED1); Tests: T1 T2 T3  18 1/1 data_o[36] = ^(data_o & 39'h00C2C1323B); Tests: T1 T2 T3  19 1/1 data_o[37] = ^(data_o & 39'h002DCC624C); Tests: T1 T2 T3  20 1/1 data_o[38] = ^(data_o & 39'h0098505586); Tests: T1 T2 T3  21 1/1 data_o ^= 39'h2A00000000; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen.gen_data_intg.u_tlul_data_integ_enc.u_data_gen
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS1399100.00

12 always_comb begin : p_encode 13 1/1 data_o = 39'(data_i); Tests: T1 T2 T3  14 1/1 data_o[32] = ^(data_o & 39'h002606BD25); Tests: T1 T2 T3  15 1/1 data_o[33] = ^(data_o & 39'h00DEBA8050); Tests: T1 T2 T3  16 1/1 data_o[34] = ^(data_o & 39'h00413D89AA); Tests: T1 T2 T3  17 1/1 data_o[35] = ^(data_o & 39'h0031234ED1); Tests: T1 T2 T3  18 1/1 data_o[36] = ^(data_o & 39'h00C2C1323B); Tests: T1 T2 T3  19 1/1 data_o[37] = ^(data_o & 39'h002DCC624C); Tests: T1 T2 T3  20 1/1 data_o[38] = ^(data_o & 39'h0098505586); Tests: T1 T2 T3  21 1/1 data_o ^= 39'h2A00000000; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_rd.gen_bus_words_intg[0].u_bus_intg.u_data_gen
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS1399100.00

12 always_comb begin : p_encode 13 1/1 data_o = 39'(data_i); Tests: T1 T2 T3  14 1/1 data_o[32] = ^(data_o & 39'h002606BD25); Tests: T1 T2 T3  15 1/1 data_o[33] = ^(data_o & 39'h00DEBA8050); Tests: T1 T2 T3  16 1/1 data_o[34] = ^(data_o & 39'h00413D89AA); Tests: T1 T2 T3  17 1/1 data_o[35] = ^(data_o & 39'h0031234ED1); Tests: T1 T2 T3  18 1/1 data_o[36] = ^(data_o & 39'h00C2C1323B); Tests: T1 T2 T3  19 1/1 data_o[37] = ^(data_o & 39'h002DCC624C); Tests: T1 T2 T3  20 1/1 data_o[38] = ^(data_o & 39'h0098505586); Tests: T1 T2 T3  21 1/1 data_o ^= 39'h2A00000000; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_rd.gen_bus_words_intg[1].u_bus_intg.u_data_gen
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS1399100.00

12 always_comb begin : p_encode 13 1/1 data_o = 39'(data_i); Tests: T1 T2 T3  14 1/1 data_o[32] = ^(data_o & 39'h002606BD25); Tests: T1 T2 T3  15 1/1 data_o[33] = ^(data_o & 39'h00DEBA8050); Tests: T1 T2 T3  16 1/1 data_o[34] = ^(data_o & 39'h00413D89AA); Tests: T1 T2 T3  17 1/1 data_o[35] = ^(data_o & 39'h0031234ED1); Tests: T1 T2 T3  18 1/1 data_o[36] = ^(data_o & 39'h00C2C1323B); Tests: T1 T2 T3  19 1/1 data_o[37] = ^(data_o & 39'h002DCC624C); Tests: T1 T2 T3  20 1/1 data_o[38] = ^(data_o & 39'h0098505586); Tests: T1 T2 T3  21 1/1 data_o ^= 39'h2A00000000; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_rd.gen_bus_words_intg[0].u_bus_intg.u_data_gen
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS1399100.00

12 always_comb begin : p_encode 13 1/1 data_o = 39'(data_i); Tests: T1 T2 T3  14 1/1 data_o[32] = ^(data_o & 39'h002606BD25); Tests: T1 T2 T3  15 1/1 data_o[33] = ^(data_o & 39'h00DEBA8050); Tests: T1 T2 T3  16 1/1 data_o[34] = ^(data_o & 39'h00413D89AA); Tests: T1 T2 T3  17 1/1 data_o[35] = ^(data_o & 39'h0031234ED1); Tests: T1 T2 T3  18 1/1 data_o[36] = ^(data_o & 39'h00C2C1323B); Tests: T1 T2 T3  19 1/1 data_o[37] = ^(data_o & 39'h002DCC624C); Tests: T1 T2 T3  20 1/1 data_o[38] = ^(data_o & 39'h0098505586); Tests: T1 T2 T3  21 1/1 data_o ^= 39'h2A00000000; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_rd.gen_bus_words_intg[1].u_bus_intg.u_data_gen
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS1399100.00

12 always_comb begin : p_encode 13 1/1 data_o = 39'(data_i); Tests: T1 T2 T3  14 1/1 data_o[32] = ^(data_o & 39'h002606BD25); Tests: T1 T2 T3  15 1/1 data_o[33] = ^(data_o & 39'h00DEBA8050); Tests: T1 T2 T3  16 1/1 data_o[34] = ^(data_o & 39'h00413D89AA); Tests: T1 T2 T3  17 1/1 data_o[35] = ^(data_o & 39'h0031234ED1); Tests: T1 T2 T3  18 1/1 data_o[36] = ^(data_o & 39'h00C2C1323B); Tests: T1 T2 T3  19 1/1 data_o[37] = ^(data_o & 39'h002DCC624C); Tests: T1 T2 T3  20 1/1 data_o[38] = ^(data_o & 39'h0098505586); Tests: T1 T2 T3  21 1/1 data_o ^= 39'h2A00000000; Tests: T1 T2 T3 
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