Unified Coverage Report :: Module :: flash_ctrl_erase

Module : flash_ctrl_erase

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_erase.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_ctrl_erase	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_flash_ctrl_erase

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.85	97.12	94.40	98.44		100.00	84.29	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : flash_ctrl_erase

	Line No.	Total	Covered	Percent
TOTAL		9	9	100.00
CONT_ASSIGN	43	0	0
CONT_ASSIGN	46	1	1	100.00
ALWAYS	49	3	3	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	57	1	1	100.00
CONT_ASSIGN	58	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	66	1	1	100.00

42                        logic oob_err;
43         unreachable    assign oob_err = op_start_i & op_addr_oob_i;
44                      
45                        // IO assignments
46         1/1            assign op_done_o = flash_req_o & (flash_done_i | oob_err);
           Tests:       T1 T2 T3 
47                      
48                        always_comb begin
49         1/1              op_err_o = '0;
           Tests:       T1 T2 T3 
50         1/1              op_err_o.oob_err = op_done_o & oob_err;
           Tests:       T1 T2 T3 
51         1/1              op_err_o.mp_err = op_done_o & flash_mp_err_i;
           Tests:       T1 T2 T3 
52                        end
53                      
54                      
55                        // Flash Interface assignments
56         1/1            assign flash_req_o = op_start_i & ~op_addr_oob_i;
           Tests:       T1 T2 T3 
57         1/1            assign flash_op_o = op_type_i;
           Tests:       T1 T2 T3 
58         1/1            assign flash_addr_o = (op_type_i == FlashErasePage) ?
           Tests:       T1 T2 T3 
59                                              op_addr_i & PageAddrMask :
60                                              op_addr_i & BankAddrMask;
61                      
62         1/1            assign op_err_addr_o = flash_addr_o;
           Tests:       T1 T2 T3 
63                      
64                        // unused bus
65                        logic [WordsBitWidth-1:0] unused_addr_i;
66         1/1            assign unused_addr_i = op_addr_i[WordsBitWidth-1:0];
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : flash_ctrl_erase

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       43
 EXPRESSION (op_start_i & op_addr_oob_i)
             -----1----   ------2------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T7,T15,T23
1	1	Unreachable

 LINE       46
 EXPRESSION (flash_req_o & (flash_done_i | oob_err))
             -----1-----   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T14,T22,T17
1	0	Covered	T7,T15,T23
1	1	Covered	T7,T15,T23

 LINE       46
 SUB-EXPRESSION (flash_done_i | oob_err)
                 ------1-----   ---2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T7,T14,T22

 LINE       50
 EXPRESSION (op_done_o & oob_err)
             ----1----   ---2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T7,T15,T23
1	1	Unreachable

 LINE       51
 EXPRESSION (op_done_o & flash_mp_err_i)
             ----1----   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T14,T22,T17
1	0	Covered	T7,T15,T23
1	1	Covered	T27,T35,T36

 LINE       56
 EXPRESSION (op_start_i & ((~op_addr_oob_i)))
             -----1----   ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T7,T15,T23

 LINE       58
 EXPRESSION ((op_type_i == FlashErasePage) ? ((op_addr_i & PageAddrMask)) : ((op_addr_i & BankAddrMask)))
             --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       58
 SUB-EXPRESSION (op_type_i == FlashErasePage)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : flash_ctrl_erase

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
TERNARY	58	2	2	100.00

58           assign flash_addr_o = (op_type_i == FlashErasePage) ?
                                                                 -1-  
                                                                 ==>  
                                                                 ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3