Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T7  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T7  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T7 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T7 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T13,T16

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T13,T16
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T13,T16
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T16,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T13,T16

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T13,T16
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T16,T17
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T13,T16

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T13,T16

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1547907552	1544461836	0	0
CheckNGreaterZero_A	4160	4160	0	0
GntImpliesReady_A	1547907552	410169414	0	0
GntImpliesValid_A	1547907552	410169414	0	0
GrantKnown_A	1547907552	1544461836	0	0
IdxKnown_A	1547907552	1544461836	0	0
IndexIsCorrect_A	1547907552	410169414	0	0
NoReadyValidNoGrant_A	1547907552	174106588	0	0
Priority_A	1547907552	434233774	0	0
ReadyAndValidImplyGrant_A	1547907552	410169414	0	0
ReqAndReadyImplyGrant_A	1547907552	410169414	0	0
ReqImpliesValid_A	1547907552	434233774	0	0
ValidKnown_A	1547907552	1544461836	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1547907552	1544461836	0	0
T1	15496	15188	0	0
T2	42700	42352	0	0
T3	10212	9832	0	0
T7	9060	8692	0	0
T13	5300	4928	0	0
T14	220940	220584	0	0
T15	386228	385856	0	0
T20	5892	5640	0	0
T21	7688	7440	0	0
T22	716008	715752	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4160	4160	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T7	4	4	0	0
T13	4	4	0	0
T14	4	4	0	0
T15	4	4	0	0
T20	4	4	0	0
T21	4	4	0	0
T22	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1547907552	410169414	0	0
T1	7748	4430	0	0
T2	42700	1670	0	0
T3	10212	356	0	0
T7	9060	1178	0	0
T13	5300	84	0	0
T14	220940	73310	0	0
T15	386228	121968	0	0
T16	0	1340	0	0
T17	0	48124	0	0
T20	5892	356	0	0
T21	7688	356	0	0
T22	716008	301672	0	0
T23	190834	16806	0	0
T43	0	19006	0	0
T65	0	23386	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1547907552	410169414	0	0
T1	7748	4430	0	0
T2	42700	1670	0	0
T3	10212	356	0	0
T7	9060	1178	0	0
T13	5300	84	0	0
T14	220940	73310	0	0
T15	386228	121968	0	0
T16	0	1340	0	0
T17	0	48124	0	0
T20	5892	356	0	0
T21	7688	356	0	0
T22	716008	301672	0	0
T23	190834	16806	0	0
T43	0	19006	0	0
T65	0	23386	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1547907552	1544461836	0	0
T1	15496	15188	0	0
T2	42700	42352	0	0
T3	10212	9832	0	0
T7	9060	8692	0	0
T13	5300	4928	0	0
T14	220940	220584	0	0
T15	386228	385856	0	0
T20	5892	5640	0	0
T21	7688	7440	0	0
T22	716008	715752	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1547907552	1544461836	0	0
T1	15496	15188	0	0
T2	42700	42352	0	0
T3	10212	9832	0	0
T7	9060	8692	0	0
T13	5300	4928	0	0
T14	220940	220584	0	0
T15	386228	385856	0	0
T20	5892	5640	0	0
T21	7688	7440	0	0
T22	716008	715752	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1547907552	410169414	0	0
T1	7748	4430	0	0
T2	42700	1670	0	0
T3	10212	356	0	0
T7	9060	1178	0	0
T13	5300	84	0	0
T14	220940	73310	0	0
T15	386228	121968	0	0
T16	0	1340	0	0
T17	0	48124	0	0
T20	5892	356	0	0
T21	7688	356	0	0
T22	716008	301672	0	0
T23	190834	16806	0	0
T43	0	19006	0	0
T65	0	23386	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1547907552	174106588	0	0
T1	7748	256	0	0
T2	42700	2652	0	0
T3	10212	694	0	0
T7	9060	316	0	0
T13	5300	286	0	0
T14	220940	3152	0	0
T15	386228	7384	0	0
T16	0	114	0	0
T17	0	3006	0	0
T20	5892	992	0	0
T21	7688	694	0	0
T22	716008	256	0	0
T23	190834	68	0	0
T27	0	212	0	0
T43	0	56570	0	0
T65	0	30194	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1547907552	434233774	0	0
T1	7748	4430	0	0
T2	42700	1672	0	0
T3	10212	356	0	0
T7	9060	1178	0	0
T13	5300	84	0	0
T14	220940	73310	0	0
T15	386228	121968	0	0
T16	0	1340	0	0
T17	0	48124	0	0
T20	5892	356	0	0
T21	7688	356	0	0
T22	716008	301672	0	0
T23	190834	16806	0	0
T43	0	20702	0	0
T65	0	36014	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1547907552	410169414	0	0
T1	7748	4430	0	0
T2	42700	1670	0	0
T3	10212	356	0	0
T7	9060	1178	0	0
T13	5300	84	0	0
T14	220940	73310	0	0
T15	386228	121968	0	0
T16	0	1340	0	0
T17	0	48124	0	0
T20	5892	356	0	0
T21	7688	356	0	0
T22	716008	301672	0	0
T23	190834	16806	0	0
T43	0	19006	0	0
T65	0	23386	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1547907552	410169414	0	0
T1	7748	4430	0	0
T2	42700	1670	0	0
T3	10212	356	0	0
T7	9060	1178	0	0
T13	5300	84	0	0
T14	220940	73310	0	0
T15	386228	121968	0	0
T16	0	1340	0	0
T17	0	48124	0	0
T20	5892	356	0	0
T21	7688	356	0	0
T22	716008	301672	0	0
T23	190834	16806	0	0
T43	0	19006	0	0
T65	0	23386	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1547907552	434233774	0	0
T1	7748	4430	0	0
T2	42700	1672	0	0
T3	10212	356	0	0
T7	9060	1178	0	0
T13	5300	84	0	0
T14	220940	73310	0	0
T15	386228	121968	0	0
T16	0	1340	0	0
T17	0	48124	0	0
T20	5892	356	0	0
T21	7688	356	0	0
T22	716008	301672	0	0
T23	190834	16806	0	0
T43	0	20702	0	0
T65	0	36014	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1547907552	1544461836	0	0
T1	15496	15188	0	0
T2	42700	42352	0	0
T3	10212	9832	0	0
T7	9060	8692	0	0
T13	5300	4928	0	0
T14	220940	220584	0	0
T15	386228	385856	0	0
T20	5892	5640	0	0
T21	7688	7440	0	0
T22	716008	715752	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T7  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T7  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T7 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T7 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T13,T16

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T13,T16
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T13,T16
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T43
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T13,T16

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T13,T16
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T17,T43
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T13,T16

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T13,T16

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	386976888	386115459	0	0
CheckNGreaterZero_A	1040	1040	0	0
GntImpliesReady_A	386976888	105857390	0	0
GntImpliesValid_A	386976888	105857390	0	0
GrantKnown_A	386976888	386115459	0	0
IdxKnown_A	386976888	386115459	0	0
IndexIsCorrect_A	386976888	105857390	0	0
NoReadyValidNoGrant_A	386976888	45421459	0	0
Priority_A	386976888	111844685	0	0
ReadyAndValidImplyGrant_A	386976888	105857390	0	0
ReqAndReadyImplyGrant_A	386976888	105857390	0	0
ReqImpliesValid_A	386976888	111844685	0	0
ValidKnown_A	386976888	386115459	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	386115459	0	0
T1	3874	3797	0	0
T2	10675	10588	0	0
T3	2553	2458	0	0
T7	2265	2173	0	0
T13	1325	1232	0	0
T14	55235	55146	0	0
T15	96557	96464	0	0
T20	1473	1410	0	0
T21	1922	1860	0	0
T22	179002	178938	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1040	1040	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	105857390	0	0
T1	3874	2215	0	0
T2	10675	511	0	0
T3	2553	178	0	0
T7	2265	589	0	0
T13	1325	42	0	0
T14	55235	19044	0	0
T15	96557	26598	0	0
T20	1473	32	0	0
T21	1922	178	0	0
T22	179002	80486	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	105857390	0	0
T1	3874	2215	0	0
T2	10675	511	0	0
T3	2553	178	0	0
T7	2265	589	0	0
T13	1325	42	0	0
T14	55235	19044	0	0
T15	96557	26598	0	0
T20	1473	32	0	0
T21	1922	178	0	0
T22	179002	80486	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	386115459	0	0
T1	3874	3797	0	0
T2	10675	10588	0	0
T3	2553	2458	0	0
T7	2265	2173	0	0
T13	1325	1232	0	0
T14	55235	55146	0	0
T15	96557	96464	0	0
T20	1473	1410	0	0
T21	1922	1860	0	0
T22	179002	178938	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	386115459	0	0
T1	3874	3797	0	0
T2	10675	10588	0	0
T3	2553	2458	0	0
T7	2265	2173	0	0
T13	1325	1232	0	0
T14	55235	55146	0	0
T15	96557	96464	0	0
T20	1473	1410	0	0
T21	1922	1860	0	0
T22	179002	178938	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	105857390	0	0
T1	3874	2215	0	0
T2	10675	511	0	0
T3	2553	178	0	0
T7	2265	589	0	0
T13	1325	42	0	0
T14	55235	19044	0	0
T15	96557	26598	0	0
T20	1473	32	0	0
T21	1922	178	0	0
T22	179002	80486	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	45421459	0	0
T1	3874	128	0	0
T2	10675	842	0	0
T3	2553	347	0	0
T7	2265	158	0	0
T13	1325	143	0	0
T14	55235	1100	0	0
T15	96557	1670	0	0
T20	1473	128	0	0
T21	1922	347	0	0
T22	179002	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	111844685	0	0
T1	3874	2215	0	0
T2	10675	511	0	0
T3	2553	178	0	0
T7	2265	589	0	0
T13	1325	42	0	0
T14	55235	19044	0	0
T15	96557	26598	0	0
T20	1473	32	0	0
T21	1922	178	0	0
T22	179002	80486	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	105857390	0	0
T1	3874	2215	0	0
T2	10675	511	0	0
T3	2553	178	0	0
T7	2265	589	0	0
T13	1325	42	0	0
T14	55235	19044	0	0
T15	96557	26598	0	0
T20	1473	32	0	0
T21	1922	178	0	0
T22	179002	80486	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	105857390	0	0
T1	3874	2215	0	0
T2	10675	511	0	0
T3	2553	178	0	0
T7	2265	589	0	0
T13	1325	42	0	0
T14	55235	19044	0	0
T15	96557	26598	0	0
T20	1473	32	0	0
T21	1922	178	0	0
T22	179002	80486	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	111844685	0	0
T1	3874	2215	0	0
T2	10675	511	0	0
T3	2553	178	0	0
T7	2265	589	0	0
T13	1325	42	0	0
T14	55235	19044	0	0
T15	96557	26598	0	0
T20	1473	32	0	0
T21	1922	178	0	0
T22	179002	80486	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	386115459	0	0
T1	3874	3797	0	0
T2	10675	10588	0	0
T3	2553	2458	0	0
T7	2265	2173	0	0
T13	1325	1232	0	0
T14	55235	55146	0	0
T15	96557	96464	0	0
T20	1473	1410	0	0
T21	1922	1860	0	0
T22	179002	178938	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T7  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T7  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T7 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T7 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T13,T16

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T13,T16
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T13,T16
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T16,T17,T43
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T13,T16

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T13,T16
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T17,T43
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T13,T16

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T13,T16

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	386976888	386115459	0	0
CheckNGreaterZero_A	1040	1040	0	0
GntImpliesReady_A	386976888	105857427	0	0
GntImpliesValid_A	386976888	105857427	0	0
GrantKnown_A	386976888	386115459	0	0
IdxKnown_A	386976888	386115459	0	0
IndexIsCorrect_A	386976888	105857427	0	0
NoReadyValidNoGrant_A	386976888	45421447	0	0
Priority_A	386976888	111844734	0	0
ReadyAndValidImplyGrant_A	386976888	105857427	0	0
ReqAndReadyImplyGrant_A	386976888	105857427	0	0
ReqImpliesValid_A	386976888	111844734	0	0
ValidKnown_A	386976888	386115459	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	386115459	0	0
T1	3874	3797	0	0
T2	10675	10588	0	0
T3	2553	2458	0	0
T7	2265	2173	0	0
T13	1325	1232	0	0
T14	55235	55146	0	0
T15	96557	96464	0	0
T20	1473	1410	0	0
T21	1922	1860	0	0
T22	179002	178938	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1040	1040	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	105857427	0	0
T1	3874	2215	0	0
T2	10675	511	0	0
T3	2553	178	0	0
T7	2265	589	0	0
T13	1325	42	0	0
T14	55235	19044	0	0
T15	96557	26598	0	0
T20	1473	32	0	0
T21	1922	178	0	0
T22	179002	80486	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	105857427	0	0
T1	3874	2215	0	0
T2	10675	511	0	0
T3	2553	178	0	0
T7	2265	589	0	0
T13	1325	42	0	0
T14	55235	19044	0	0
T15	96557	26598	0	0
T20	1473	32	0	0
T21	1922	178	0	0
T22	179002	80486	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	386115459	0	0
T1	3874	3797	0	0
T2	10675	10588	0	0
T3	2553	2458	0	0
T7	2265	2173	0	0
T13	1325	1232	0	0
T14	55235	55146	0	0
T15	96557	96464	0	0
T20	1473	1410	0	0
T21	1922	1860	0	0
T22	179002	178938	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	386115459	0	0
T1	3874	3797	0	0
T2	10675	10588	0	0
T3	2553	2458	0	0
T7	2265	2173	0	0
T13	1325	1232	0	0
T14	55235	55146	0	0
T15	96557	96464	0	0
T20	1473	1410	0	0
T21	1922	1860	0	0
T22	179002	178938	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	105857427	0	0
T1	3874	2215	0	0
T2	10675	511	0	0
T3	2553	178	0	0
T7	2265	589	0	0
T13	1325	42	0	0
T14	55235	19044	0	0
T15	96557	26598	0	0
T20	1473	32	0	0
T21	1922	178	0	0
T22	179002	80486	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	45421447	0	0
T1	3874	128	0	0
T2	10675	842	0	0
T3	2553	347	0	0
T7	2265	158	0	0
T13	1325	143	0	0
T14	55235	1100	0	0
T15	96557	1670	0	0
T20	1473	128	0	0
T21	1922	347	0	0
T22	179002	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	111844734	0	0
T1	3874	2215	0	0
T2	10675	511	0	0
T3	2553	178	0	0
T7	2265	589	0	0
T13	1325	42	0	0
T14	55235	19044	0	0
T15	96557	26598	0	0
T20	1473	32	0	0
T21	1922	178	0	0
T22	179002	80486	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	105857427	0	0
T1	3874	2215	0	0
T2	10675	511	0	0
T3	2553	178	0	0
T7	2265	589	0	0
T13	1325	42	0	0
T14	55235	19044	0	0
T15	96557	26598	0	0
T20	1473	32	0	0
T21	1922	178	0	0
T22	179002	80486	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	105857427	0	0
T1	3874	2215	0	0
T2	10675	511	0	0
T3	2553	178	0	0
T7	2265	589	0	0
T13	1325	42	0	0
T14	55235	19044	0	0
T15	96557	26598	0	0
T20	1473	32	0	0
T21	1922	178	0	0
T22	179002	80486	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	111844734	0	0
T1	3874	2215	0	0
T2	10675	511	0	0
T3	2553	178	0	0
T7	2265	589	0	0
T13	1325	42	0	0
T14	55235	19044	0	0
T15	96557	26598	0	0
T20	1473	32	0	0
T21	1922	178	0	0
T22	179002	80486	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	386115459	0	0
T1	3874	3797	0	0
T2	10675	10588	0	0
T3	2553	2458	0	0
T7	2265	2173	0	0
T13	1325	1232	0	0
T14	55235	55146	0	0
T15	96557	96464	0	0
T20	1473	1410	0	0
T21	1922	1860	0	0
T22	179002	178938	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T7  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T7  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T7 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T7 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T20,T14
1	0	Covered	T2,T16,T17

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T16,T17
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T16,T17
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T17,T43
1	0	Covered	T2,T20,T14
1	1	Covered	T2,T16,T17

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T16,T17
1	1	Covered	T2,T20,T14

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T17,T43
1	1	Covered	T2,T20,T14

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T16,T17

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T16,T17

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	386976888	386115459	0	0
CheckNGreaterZero_A	1040	1040	0	0
GntImpliesReady_A	386976888	99227264	0	0
GntImpliesValid_A	386976888	99227264	0	0
GrantKnown_A	386976888	386115459	0	0
IdxKnown_A	386976888	386115459	0	0
IndexIsCorrect_A	386976888	99227264	0	0
NoReadyValidNoGrant_A	386976888	41631845	0	0
Priority_A	386976888	105272139	0	0
ReadyAndValidImplyGrant_A	386976888	99227264	0	0
ReqAndReadyImplyGrant_A	386976888	99227264	0	0
ReqImpliesValid_A	386976888	105272139	0	0
ValidKnown_A	386976888	386115459	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	386115459	0	0
T1	3874	3797	0	0
T2	10675	10588	0	0
T3	2553	2458	0	0
T7	2265	2173	0	0
T13	1325	1232	0	0
T14	55235	55146	0	0
T15	96557	96464	0	0
T20	1473	1410	0	0
T21	1922	1860	0	0
T22	179002	178938	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1040	1040	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	99227264	0	0
T2	10675	324	0	0
T3	2553	0	0	0
T7	2265	0	0	0
T13	1325	0	0	0
T14	55235	17611	0	0
T15	96557	34386	0	0
T16	0	670	0	0
T17	0	24062	0	0
T20	1473	146	0	0
T21	1922	0	0	0
T22	179002	70350	0	0
T23	95417	8403	0	0
T43	0	9503	0	0
T65	0	11693	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	99227264	0	0
T2	10675	324	0	0
T3	2553	0	0	0
T7	2265	0	0	0
T13	1325	0	0	0
T14	55235	17611	0	0
T15	96557	34386	0	0
T16	0	670	0	0
T17	0	24062	0	0
T20	1473	146	0	0
T21	1922	0	0	0
T22	179002	70350	0	0
T23	95417	8403	0	0
T43	0	9503	0	0
T65	0	11693	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	386115459	0	0
T1	3874	3797	0	0
T2	10675	10588	0	0
T3	2553	2458	0	0
T7	2265	2173	0	0
T13	1325	1232	0	0
T14	55235	55146	0	0
T15	96557	96464	0	0
T20	1473	1410	0	0
T21	1922	1860	0	0
T22	179002	178938	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	386115459	0	0
T1	3874	3797	0	0
T2	10675	10588	0	0
T3	2553	2458	0	0
T7	2265	2173	0	0
T13	1325	1232	0	0
T14	55235	55146	0	0
T15	96557	96464	0	0
T20	1473	1410	0	0
T21	1922	1860	0	0
T22	179002	178938	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	99227264	0	0
T2	10675	324	0	0
T3	2553	0	0	0
T7	2265	0	0	0
T13	1325	0	0	0
T14	55235	17611	0	0
T15	96557	34386	0	0
T16	0	670	0	0
T17	0	24062	0	0
T20	1473	146	0	0
T21	1922	0	0	0
T22	179002	70350	0	0
T23	95417	8403	0	0
T43	0	9503	0	0
T65	0	11693	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	41631845	0	0
T2	10675	484	0	0
T3	2553	0	0	0
T7	2265	0	0	0
T13	1325	0	0	0
T14	55235	476	0	0
T15	96557	2022	0	0
T16	0	57	0	0
T17	0	1503	0	0
T20	1473	368	0	0
T21	1922	0	0	0
T22	179002	0	0	0
T23	95417	34	0	0
T27	0	106	0	0
T43	0	28285	0	0
T65	0	15097	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	105272139	0	0
T2	10675	325	0	0
T3	2553	0	0	0
T7	2265	0	0	0
T13	1325	0	0	0
T14	55235	17611	0	0
T15	96557	34386	0	0
T16	0	670	0	0
T17	0	24062	0	0
T20	1473	146	0	0
T21	1922	0	0	0
T22	179002	70350	0	0
T23	95417	8403	0	0
T43	0	10351	0	0
T65	0	18007	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	99227264	0	0
T2	10675	324	0	0
T3	2553	0	0	0
T7	2265	0	0	0
T13	1325	0	0	0
T14	55235	17611	0	0
T15	96557	34386	0	0
T16	0	670	0	0
T17	0	24062	0	0
T20	1473	146	0	0
T21	1922	0	0	0
T22	179002	70350	0	0
T23	95417	8403	0	0
T43	0	9503	0	0
T65	0	11693	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	99227264	0	0
T2	10675	324	0	0
T3	2553	0	0	0
T7	2265	0	0	0
T13	1325	0	0	0
T14	55235	17611	0	0
T15	96557	34386	0	0
T16	0	670	0	0
T17	0	24062	0	0
T20	1473	146	0	0
T21	1922	0	0	0
T22	179002	70350	0	0
T23	95417	8403	0	0
T43	0	9503	0	0
T65	0	11693	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	105272139	0	0
T2	10675	325	0	0
T3	2553	0	0	0
T7	2265	0	0	0
T13	1325	0	0	0
T14	55235	17611	0	0
T15	96557	34386	0	0
T16	0	670	0	0
T17	0	24062	0	0
T20	1473	146	0	0
T21	1922	0	0	0
T22	179002	70350	0	0
T23	95417	8403	0	0
T43	0	10351	0	0
T65	0	18007	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	386115459	0	0
T1	3874	3797	0	0
T2	10675	10588	0	0
T3	2553	2458	0	0
T7	2265	2173	0	0
T13	1325	1232	0	0
T14	55235	55146	0	0
T15	96557	96464	0	0
T20	1473	1410	0	0
T21	1922	1860	0	0
T22	179002	178938	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T7  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T7  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T7 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T7 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T20,T14
1	0	Covered	T2,T16,T17

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T16,T17
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T16,T17
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T17,T43
1	0	Covered	T2,T20,T14
1	1	Covered	T2,T16,T17

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T16,T17
1	1	Covered	T2,T20,T14

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T17,T43
1	1	Covered	T2,T20,T14

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T16,T17

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T16,T17

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	386976888	386115459	0	0
CheckNGreaterZero_A	1040	1040	0	0
GntImpliesReady_A	386976888	99227333	0	0
GntImpliesValid_A	386976888	99227333	0	0
GrantKnown_A	386976888	386115459	0	0
IdxKnown_A	386976888	386115459	0	0
IndexIsCorrect_A	386976888	99227333	0	0
NoReadyValidNoGrant_A	386976888	41631837	0	0
Priority_A	386976888	105272216	0	0
ReadyAndValidImplyGrant_A	386976888	99227333	0	0
ReqAndReadyImplyGrant_A	386976888	99227333	0	0
ReqImpliesValid_A	386976888	105272216	0	0
ValidKnown_A	386976888	386115459	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	386115459	0	0
T1	3874	3797	0	0
T2	10675	10588	0	0
T3	2553	2458	0	0
T7	2265	2173	0	0
T13	1325	1232	0	0
T14	55235	55146	0	0
T15	96557	96464	0	0
T20	1473	1410	0	0
T21	1922	1860	0	0
T22	179002	178938	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1040	1040	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	99227333	0	0
T2	10675	324	0	0
T3	2553	0	0	0
T7	2265	0	0	0
T13	1325	0	0	0
T14	55235	17611	0	0
T15	96557	34386	0	0
T16	0	670	0	0
T17	0	24062	0	0
T20	1473	146	0	0
T21	1922	0	0	0
T22	179002	70350	0	0
T23	95417	8403	0	0
T43	0	9503	0	0
T65	0	11693	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	99227333	0	0
T2	10675	324	0	0
T3	2553	0	0	0
T7	2265	0	0	0
T13	1325	0	0	0
T14	55235	17611	0	0
T15	96557	34386	0	0
T16	0	670	0	0
T17	0	24062	0	0
T20	1473	146	0	0
T21	1922	0	0	0
T22	179002	70350	0	0
T23	95417	8403	0	0
T43	0	9503	0	0
T65	0	11693	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	386115459	0	0
T1	3874	3797	0	0
T2	10675	10588	0	0
T3	2553	2458	0	0
T7	2265	2173	0	0
T13	1325	1232	0	0
T14	55235	55146	0	0
T15	96557	96464	0	0
T20	1473	1410	0	0
T21	1922	1860	0	0
T22	179002	178938	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	386115459	0	0
T1	3874	3797	0	0
T2	10675	10588	0	0
T3	2553	2458	0	0
T7	2265	2173	0	0
T13	1325	1232	0	0
T14	55235	55146	0	0
T15	96557	96464	0	0
T20	1473	1410	0	0
T21	1922	1860	0	0
T22	179002	178938	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	99227333	0	0
T2	10675	324	0	0
T3	2553	0	0	0
T7	2265	0	0	0
T13	1325	0	0	0
T14	55235	17611	0	0
T15	96557	34386	0	0
T16	0	670	0	0
T17	0	24062	0	0
T20	1473	146	0	0
T21	1922	0	0	0
T22	179002	70350	0	0
T23	95417	8403	0	0
T43	0	9503	0	0
T65	0	11693	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	41631837	0	0
T2	10675	484	0	0
T3	2553	0	0	0
T7	2265	0	0	0
T13	1325	0	0	0
T14	55235	476	0	0
T15	96557	2022	0	0
T16	0	57	0	0
T17	0	1503	0	0
T20	1473	368	0	0
T21	1922	0	0	0
T22	179002	0	0	0
T23	95417	34	0	0
T27	0	106	0	0
T43	0	28285	0	0
T65	0	15097	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	105272216	0	0
T2	10675	325	0	0
T3	2553	0	0	0
T7	2265	0	0	0
T13	1325	0	0	0
T14	55235	17611	0	0
T15	96557	34386	0	0
T16	0	670	0	0
T17	0	24062	0	0
T20	1473	146	0	0
T21	1922	0	0	0
T22	179002	70350	0	0
T23	95417	8403	0	0
T43	0	10351	0	0
T65	0	18007	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	99227333	0	0
T2	10675	324	0	0
T3	2553	0	0	0
T7	2265	0	0	0
T13	1325	0	0	0
T14	55235	17611	0	0
T15	96557	34386	0	0
T16	0	670	0	0
T17	0	24062	0	0
T20	1473	146	0	0
T21	1922	0	0	0
T22	179002	70350	0	0
T23	95417	8403	0	0
T43	0	9503	0	0
T65	0	11693	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	99227333	0	0
T2	10675	324	0	0
T3	2553	0	0	0
T7	2265	0	0	0
T13	1325	0	0	0
T14	55235	17611	0	0
T15	96557	34386	0	0
T16	0	670	0	0
T17	0	24062	0	0
T20	1473	146	0	0
T21	1922	0	0	0
T22	179002	70350	0	0
T23	95417	8403	0	0
T43	0	9503	0	0
T65	0	11693	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	105272216	0	0
T2	10675	325	0	0
T3	2553	0	0	0
T7	2265	0	0	0
T13	1325	0	0	0
T14	55235	17611	0	0
T15	96557	34386	0	0
T16	0	670	0	0
T17	0	24062	0	0
T20	1473	146	0	0
T21	1922	0	0	0
T22	179002	70350	0	0
T23	95417	8403	0	0
T43	0	10351	0	0
T65	0	18007	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386976888	386115459	0	0
T1	3874	3797	0	0
T2	10675	10588	0	0
T3	2553	2458	0	0
T7	2265	2173	0	0
T13	1325	1232	0	0
T14	55235	55146	0	0
T15	96557	96464	0	0
T20	1473	1410	0	0
T21	1922	1860	0	0
T22	179002	178938	0	0