Unified Coverage Report :: Module :: flash_mp_data_region_sel

Module : flash_mp_data_region_sel

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_mp.u_sw_sel	100.00	100.00	100.00			100.00
tb.dut.u_flash_mp.u_hw_sel	100.00	100.00				100.00
tb.dut.u_eflash.u_region_sel	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_flash_mp.u_sw_sel

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.64	100.00	98.56			100.00	100.00	u_flash_mp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_flash_mp.u_hw_sel

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.64	100.00	98.56			100.00	100.00	u_flash_mp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_region_sel

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.89	97.67	90.00			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : flash_mp_data_region_sel ( parameter Regions=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_flash_mp.u_sw_sel

SCORE	LINE
100.00	100.00

tb.dut.u_eflash.u_region_sel

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
ALWAYS	35	0	0
ALWAYS	35	3	3	100.00
ALWAYS	49	4	4	100.00

27                        // decode for software interface region
28         1/1            assign region_sel[0] = region_match[0];
           Tests:       T1 T2 T3 
29                        for (genvar i = 1; i < Regions; i++) begin: gen_region_priority
30         8/8              assign region_sel[i] = region_match[i] & ~|region_match[i-1:0];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
31                        end
32                      
33                        // check for region match
34                        always_comb begin
35         1/1              for (int i = 0; i < Regions; i++) begin: gen_region_comps
           Tests:       T1 T2 T3 
36         1/1                region_end[i] = {1'b0, region_attrs_i[i].cfg.base} + region_attrs_i[i].cfg.size;
           Tests:       T1 T2 T3 
37                      
38                            // region matches if address within range and if the partition matches
39         1/1                region_match[i] = addr_i >= region_attrs_i[i].cfg.base &
           Tests:       T1 T2 T3 
40                                              {1'b0, addr_i} < region_end[i] &
41                                              phase_i == region_attrs_i[i].phase &
42                                              mubi4_test_true_strict(region_attrs_i[i].cfg.en) &
43                                              req_i;
44                          end
45                        end
46                      
47                        // select appropriate region configuration
48                        always_comb begin
49         1/1              sel_cfg_o = '0;
           Tests:       T1 T2 T3 
50         1/1              for (int i = 0; i < Regions; i++) begin: gen_region_sel
           Tests:       T1 T2 T3 
51         1/1                if (region_sel[i]) begin
           Tests:       T1 T2 T3 
52         1/1                  sel_cfg_o = region_attrs_i[i].cfg;
           Tests:       T1 T2 T3 
53                            end
                        MISSING_ELSE

---

Line Coverage for Module : flash_mp_data_region_sel ( parameter Regions=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_flash_mp.u_hw_sel

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	28	1	1	100.00
ALWAYS	35	0	0
ALWAYS	35	3	3	100.00
ALWAYS	49	4	4	100.00

27                        // decode for software interface region
28         1/1            assign region_sel[0] = region_match[0];
           Tests:       T1 T2 T3 
29                        for (genvar i = 1; i < Regions; i++) begin: gen_region_priority
30                          assign region_sel[i] = region_match[i] & ~|region_match[i-1:0];
31                        end
32                      
33                        // check for region match
34                        always_comb begin
35         1/1              for (int i = 0; i < Regions; i++) begin: gen_region_comps
           Tests:       T1 T2 T3 
36         1/1                region_end[i] = {1'b0, region_attrs_i[i].cfg.base} + region_attrs_i[i].cfg.size;
           Tests:       T1 T2 T3 
37                      
38                            // region matches if address within range and if the partition matches
39         1/1                region_match[i] = addr_i >= region_attrs_i[i].cfg.base &
           Tests:       T1 T2 T3 
40                                              {1'b0, addr_i} < region_end[i] &
41                                              phase_i == region_attrs_i[i].phase &
42                                              mubi4_test_true_strict(region_attrs_i[i].cfg.en) &
43                                              req_i;
44                          end
45                        end
46                      
47                        // select appropriate region configuration
48                        always_comb begin
49         1/1              sel_cfg_o = '0;
           Tests:       T1 T2 T3 
50         1/1              for (int i = 0; i < Regions; i++) begin: gen_region_sel
           Tests:       T1 T2 T3 
51         1/1                if (region_sel[i]) begin
           Tests:       T1 T2 T3 
52         1/1                  sel_cfg_o = region_attrs_i[i].cfg;
           Tests:       T104 T90 T75 
53                            end
                        MISSING_ELSE

---

Cond Coverage for Module : flash_mp_data_region_sel

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       30
 EXPRESSION (region_match[1] & ((~|region_match[0])))
             -------1-------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T64,T27
1	1	Covered	T22,T64,T27

 LINE       30
 EXPRESSION (region_match[2] & ((~|region_match[(2 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T64,T36,T48
1	1	Covered	T14,T27,T8

 LINE       30
 EXPRESSION (region_match[3] & ((~|region_match[(3 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T64,T27,T48
1	1	Covered	T22,T64,T65

 LINE       30
 EXPRESSION (region_match[4] & ((~|region_match[(4 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T64,T48,T50
1	1	Covered	T27,T66,T67

 LINE       30
 EXPRESSION (region_match[5] & ((~|region_match[(5 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T64,T111,T48
1	1	Covered	T14,T22,T17

 LINE       30
 EXPRESSION (region_match[6] & ((~|region_match[(6 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T67,T236
1	1	Covered	T17,T43,T27

 LINE       30
 EXPRESSION (region_match[7] & ((~|region_match[(7 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T64,T27
1	1	Covered	T65,T27,T66

 LINE       30
 EXPRESSION (region_match[8] & ((~|region_match[(8 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T14,T22
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : flash_mp_data_region_sel

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	51	2	2	100.00

51               if (region_sel[i]) begin
                 -1-  
52                 sel_cfg_o = region_attrs_i[i].cfg;
                   ==>
53               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_mp.u_sw_sel

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
ALWAYS	35	0	0
ALWAYS	35	3	3	100.00
ALWAYS	49	4	4	100.00

27                        // decode for software interface region
28         1/1            assign region_sel[0] = region_match[0];
           Tests:       T1 T2 T3 
29                        for (genvar i = 1; i < Regions; i++) begin: gen_region_priority
30         8/8              assign region_sel[i] = region_match[i] & ~|region_match[i-1:0];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
31                        end
32                      
33                        // check for region match
34                        always_comb begin
35         1/1              for (int i = 0; i < Regions; i++) begin: gen_region_comps
           Tests:       T1 T2 T3 
36         1/1                region_end[i] = {1'b0, region_attrs_i[i].cfg.base} + region_attrs_i[i].cfg.size;
           Tests:       T1 T2 T3 
37                      
38                            // region matches if address within range and if the partition matches
39         1/1                region_match[i] = addr_i >= region_attrs_i[i].cfg.base &
           Tests:       T1 T2 T3 
40                                              {1'b0, addr_i} < region_end[i] &
41                                              phase_i == region_attrs_i[i].phase &
42                                              mubi4_test_true_strict(region_attrs_i[i].cfg.en) &
43                                              req_i;
44                          end
45                        end
46                      
47                        // select appropriate region configuration
48                        always_comb begin
49         1/1              sel_cfg_o = '0;
           Tests:       T1 T2 T3 
50         1/1              for (int i = 0; i < Regions; i++) begin: gen_region_sel
           Tests:       T1 T2 T3 
51         1/1                if (region_sel[i]) begin
           Tests:       T1 T2 T3 
52         1/1                  sel_cfg_o = region_attrs_i[i].cfg;
           Tests:       T1 T2 T3 
53                            end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_flash_mp.u_sw_sel

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       30
 EXPRESSION (region_match[1] & ((~|region_match[0])))
             -------1-------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T64,T48
1	1	Covered	T22,T64,T27

 LINE       30
 EXPRESSION (region_match[2] & ((~|region_match[(2 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T64,T36,T48
1	1	Covered	T14,T27,T8

 LINE       30
 EXPRESSION (region_match[3] & ((~|region_match[(3 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T64,T27,T48
1	1	Covered	T22,T64,T65

 LINE       30
 EXPRESSION (region_match[4] & ((~|region_match[(4 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T64,T48,T50
1	1	Covered	T236,T61,T71

 LINE       30
 EXPRESSION (region_match[5] & ((~|region_match[(5 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T64,T48,T272
1	1	Covered	T14,T22,T17

 LINE       30
 EXPRESSION (region_match[6] & ((~|region_match[(6 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T236,T29
1	1	Covered	T27,T10,T236

 LINE       30
 EXPRESSION (region_match[7] & ((~|region_match[(7 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T64,T27
1	1	Covered	T65,T27,T61

 LINE       30
 EXPRESSION (region_match[8] & ((~|region_match[(8 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T22,T16
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_flash_mp.u_sw_sel

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	51	2	2	100.00

51               if (region_sel[i]) begin
                 -1-  
52                 sel_cfg_o = region_attrs_i[i].cfg;
                   ==>
53               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_mp.u_hw_sel

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	28	1	1	100.00
ALWAYS	35	0	0
ALWAYS	35	3	3	100.00
ALWAYS	49	4	4	100.00

27                        // decode for software interface region
28         1/1            assign region_sel[0] = region_match[0];
           Tests:       T1 T2 T3 
29                        for (genvar i = 1; i < Regions; i++) begin: gen_region_priority
30                          assign region_sel[i] = region_match[i] & ~|region_match[i-1:0];
31                        end
32                      
33                        // check for region match
34                        always_comb begin
35         1/1              for (int i = 0; i < Regions; i++) begin: gen_region_comps
           Tests:       T1 T2 T3 
36         1/1                region_end[i] = {1'b0, region_attrs_i[i].cfg.base} + region_attrs_i[i].cfg.size;
           Tests:       T1 T2 T3 
37                      
38                            // region matches if address within range and if the partition matches
39         1/1                region_match[i] = addr_i >= region_attrs_i[i].cfg.base &
           Tests:       T1 T2 T3 
40                                              {1'b0, addr_i} < region_end[i] &
41                                              phase_i == region_attrs_i[i].phase &
42                                              mubi4_test_true_strict(region_attrs_i[i].cfg.en) &
43                                              req_i;
44                          end
45                        end
46                      
47                        // select appropriate region configuration
48                        always_comb begin
49         1/1              sel_cfg_o = '0;
           Tests:       T1 T2 T3 
50         1/1              for (int i = 0; i < Regions; i++) begin: gen_region_sel
           Tests:       T1 T2 T3 
51         1/1                if (region_sel[i]) begin
           Tests:       T1 T2 T3 
52         1/1                  sel_cfg_o = region_attrs_i[i].cfg;
           Tests:       T104 T90 T75 
53                            end
                        MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_flash_mp.u_hw_sel

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	51	2	2	100.00

51               if (region_sel[i]) begin
                 -1-  
52                 sel_cfg_o = region_attrs_i[i].cfg;
                   ==>
53               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T104,T90,T75
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.u_region_sel

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
CONT_ASSIGN	30	1	1	100.00
ALWAYS	35	0	0
ALWAYS	35	3	3	100.00
ALWAYS	49	4	4	100.00

27                        // decode for software interface region
28         1/1            assign region_sel[0] = region_match[0];
           Tests:       T1 T2 T7 
29                        for (genvar i = 1; i < Regions; i++) begin: gen_region_priority
30         8/8              assign region_sel[i] = region_match[i] & ~|region_match[i-1:0];
           Tests:       T1 T2 T7  | T1 T2 T7  | T1 T2 T7  | T1 T2 T7  | T1 T2 T7  | T1 T2 T7  | T1 T2 T7  | T1 T2 T7 
31                        end
32                      
33                        // check for region match
34                        always_comb begin
35         1/1              for (int i = 0; i < Regions; i++) begin: gen_region_comps
           Tests:       T1 T2 T3 
36         1/1                region_end[i] = {1'b0, region_attrs_i[i].cfg.base} + region_attrs_i[i].cfg.size;
           Tests:       T1 T2 T3 
37                      
38                            // region matches if address within range and if the partition matches
39         1/1                region_match[i] = addr_i >= region_attrs_i[i].cfg.base &
           Tests:       T1 T2 T3 
40                                              {1'b0, addr_i} < region_end[i] &
41                                              phase_i == region_attrs_i[i].phase &
42                                              mubi4_test_true_strict(region_attrs_i[i].cfg.en) &
43                                              req_i;
44                          end
45                        end
46                      
47                        // select appropriate region configuration
48                        always_comb begin
49         1/1              sel_cfg_o = '0;
           Tests:       T1 T2 T3 
50         1/1              for (int i = 0; i < Regions; i++) begin: gen_region_sel
           Tests:       T1 T2 T3 
51         1/1                if (region_sel[i]) begin
           Tests:       T1 T2 T3 
52         1/1                  sel_cfg_o = region_attrs_i[i].cfg;
           Tests:       T2 T13 T16 
53                            end
                        MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_eflash.u_region_sel

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       30
 EXPRESSION (region_match[1] & ((~|region_match[0])))
             -------1-------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T64,T27
1	1	Covered	T64,T27,T58

 LINE       30
 EXPRESSION (region_match[2] & ((~|region_match[(2 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T64,T48,T228
1	1	Covered	T27,T66,T33

 LINE       30
 EXPRESSION (region_match[3] & ((~|region_match[(3 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T64,T27,T48
1	1	Covered	T27,T71,T29

 LINE       30
 EXPRESSION (region_match[4] & ((~|region_match[(4 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T64,T48,T228
1	1	Covered	T27,T66,T67

 LINE       30
 EXPRESSION (region_match[5] & ((~|region_match[(5 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T64,T111,T48
1	1	Covered	T66,T67,T172

 LINE       30
 EXPRESSION (region_match[6] & ((~|region_match[(6 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T67,T228
1	1	Covered	T17,T43,T27

 LINE       30
 EXPRESSION (region_match[7] & ((~|region_match[(7 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T64,T27
1	1	Covered	T66,T111,T148

 LINE       30
 EXPRESSION (region_match[8] & ((~|region_match[(8 - 1):0])))
             -------1-------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T16,T17
1	1	Covered	T2,T16,T17

---

Branch Coverage for Instance : tb.dut.u_eflash.u_region_sel

	Line No.	Total	Covered	Percent
Branches		2	2	100.00
IF	51	2	2	100.00

51               if (region_sel[i]) begin
                 -1-  
52                 sel_cfg_o = region_attrs_i[i].cfg;
                   ==>
53               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T13,T16
0	Covered	T1,T2,T3