Unified Coverage Report :: Module :: flash_phy_erase

Module : flash_phy_erase

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.22	100.00	88.89		100.00	100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_erase.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_erase	97.22	100.00	88.89		100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_erase	97.22	100.00	88.89		100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_erase

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.22	100.00	88.89		100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.22	100.00	88.89		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.25	100.00	96.23		100.00	100.00	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_erase

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.22	100.00	88.89		100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.22	100.00	88.89		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.55	100.00	84.91		100.00	97.83	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : flash_phy_erase

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	39	3	3	100.00
ALWAYS	47	17	17	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

38                        always_ff @(posedge clk_i or negedge rst_ni) begin
39         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
40         1/1                state_q <= StEraseIdle;
           Tests:       T1 T2 T3 
41                          end else begin
42         1/1                state_q <= state_d;
           Tests:       T1 T2 T3 
43                          end
44                        end
45                      
46                        always_comb begin
47         1/1              req_valid = 1'b0;
           Tests:       T1 T2 T3 
48         1/1              suspend_valid = 1'b0;
           Tests:       T1 T2 T3 
49         1/1              ack_o = 1'b0;
           Tests:       T1 T2 T3 
50         1/1              state_d = state_q;
           Tests:       T1 T2 T3 
51                      
52         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
53                            StEraseIdle: begin
54         1/1                  req_valid = 1'b1;
           Tests:       T1 T2 T3 
55                      
56         1/1                  if ((pg_erase_req_o || bk_erase_req_o) && ack_i) begin
           Tests:       T1 T2 T3 
57         1/1                    state_d = StEraseBusy;
           Tests:       T7 T15 T23 
58                              end
                        MISSING_ELSE
59                            end
60                      
61                            StEraseBusy: begin
62         1/1                  suspend_valid = '1;
           Tests:       T7 T15 T23 
63                      
64         1/1                  if (suspend_req_i && ack_i) begin
           Tests:       T7 T15 T23 
65         1/1                    state_d = StEraseSuspend;
           Tests:       T23 T97 T50 
66         1/1                  end else if (done_i) begin
           Tests:       T7 T15 T23 
67         1/1                    ack_o = 1'b1;
           Tests:       T7 T15 T23 
68         1/1                    state_d = StEraseIdle;
           Tests:       T7 T15 T23 
69                              end
                        MISSING_ELSE
70                            end
71                      
72                            StEraseSuspend: begin
73         1/1                  if (done_i) begin
           Tests:       T23 T97 T12 
74         1/1                    ack_o = 1'b1;
           Tests:       T23 T97 T12 
75         1/1                    state_d = StEraseIdle;
           Tests:       T23 T97 T12 
76                              end
                        MISSING_ELSE
77                            end
78                      
79                            default:;
80                          endcase // unique case (state_q)
81                        end
82                      
83         1/1            assign pg_erase_req_o = pg_erase_req_i & req_valid;
           Tests:       T1 T2 T3 
84         1/1            assign bk_erase_req_o = bk_erase_req_i & req_valid;
           Tests:       T1 T2 T3 
85         1/1            assign suspend_req_o = suspend_req_i & suspend_valid;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : flash_phy_erase

	Total	Covered	Percent
Conditions	18	16	88.89
Logical	18	16	88.89
Non-Logical	0	0
Event	0	0

 LINE       56
 EXPRESSION ((pg_erase_req_o || bk_erase_req_o) && ack_i)
             -----------------1----------------    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T15,T23

 LINE       56
 SUB-EXPRESSION (pg_erase_req_o || bk_erase_req_o)
                 -------1------    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T36,T48,T49
1	0	Covered	T7,T15,T23

 LINE       64
 EXPRESSION (suspend_req_i && ack_i)
             ------1------    --2--

-1-	-2-	Status	Tests
0	1	Covered	T7,T15,T23
1	0	Not Covered
1	1	Covered	T23,T97,T50

 LINE       83
 EXPRESSION (pg_erase_req_i & req_valid)
             -------1------   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T15,T23
1	1	Covered	T7,T15,T23

 LINE       84
 EXPRESSION (bk_erase_req_i & req_valid)
             -------1------   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T36,T48,T49
1	1	Covered	T36,T48,T49

 LINE       85
 EXPRESSION (suspend_req_i & suspend_valid)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T15,T23
1	0	Covered	T23,T97,T50
1	1	Covered	T23,T97,T50

---

FSM Coverage for Module : flash_phy_erase

Summary for FSM :: state_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	4	4	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StEraseBusy	57	Covered	T7,T15,T23
StEraseIdle	68	Covered	T1,T2,T3
StEraseSuspend	65	Covered	T23,T97,T50

transitions	Line No.	Covered	Tests
StEraseBusy->StEraseIdle	68	Covered	T7,T15,T23
StEraseBusy->StEraseSuspend	65	Covered	T23,T97,T50
StEraseIdle->StEraseBusy	57	Covered	T7,T15,T23
StEraseSuspend->StEraseIdle	75	Covered	T23,T97,T50

---

Branch Coverage for Module : flash_phy_erase

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
IF	39	2	2	100.00
CASE	52	8	8	100.00

39             if (!rst_ni) begin
               -1-  
40               state_q <= StEraseIdle;
                 ==>
41             end else begin
42               state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

52             unique case (state_q)
                      -1-  
53               StEraseIdle: begin
54                 req_valid = 1'b1;
55         
56                 if ((pg_erase_req_o || bk_erase_req_o) && ack_i) begin
                   -2-  
57                   state_d = StEraseBusy;
                     ==>
58                 end
                   MISSING_ELSE
                   ==>
59               end
60         
61               StEraseBusy: begin
62                 suspend_valid = '1;
63         
64                 if (suspend_req_i && ack_i) begin
                   -3-  
65                   state_d = StEraseSuspend;
                     ==>
66                 end else if (done_i) begin
                            -4-  
67                   ack_o = 1'b1;
                     ==>
68                   state_d = StEraseIdle;
69                 end
                   MISSING_ELSE
                   ==>
70               end
71         
72               StEraseSuspend: begin
73                 if (done_i) begin
                   -5-  
74                   ack_o = 1'b1;
                     ==>
75                   state_d = StEraseIdle;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78         
79               default:;
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StEraseIdle	1	-	-	-	Covered	T7,T15,T23
StEraseIdle	0	-	-	-	Covered	T1,T2,T3
StEraseBusy	-	1	-	-	Covered	T23,T97,T50
StEraseBusy	-	0	1	-	Covered	T7,T15,T23
StEraseBusy	-	0	0	-	Covered	T7,T15,T23
StEraseSuspend	-	-	-	1	Covered	T23,T97,T12
StEraseSuspend	-	-	-	0	Covered	T12
default	-	-	-	-	Covered	T12

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_erase

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	39	3	3	100.00
ALWAYS	47	17	17	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

38                        always_ff @(posedge clk_i or negedge rst_ni) begin
39         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
40         1/1                state_q <= StEraseIdle;
           Tests:       T1 T2 T3 
41                          end else begin
42         1/1                state_q <= state_d;
           Tests:       T1 T2 T3 
43                          end
44                        end
45                      
46                        always_comb begin
47         1/1              req_valid = 1'b0;
           Tests:       T1 T2 T3 
48         1/1              suspend_valid = 1'b0;
           Tests:       T1 T2 T3 
49         1/1              ack_o = 1'b0;
           Tests:       T1 T2 T3 
50         1/1              state_d = state_q;
           Tests:       T1 T2 T3 
51                      
52         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
53                            StEraseIdle: begin
54         1/1                  req_valid = 1'b1;
           Tests:       T1 T2 T3 
55                      
56         1/1                  if ((pg_erase_req_o || bk_erase_req_o) && ack_i) begin
           Tests:       T1 T2 T3 
57         1/1                    state_d = StEraseBusy;
           Tests:       T7 T15 T23 
58                              end
                        MISSING_ELSE
59                            end
60                      
61                            StEraseBusy: begin
62         1/1                  suspend_valid = '1;
           Tests:       T7 T15 T23 
63                      
64         1/1                  if (suspend_req_i && ack_i) begin
           Tests:       T7 T15 T23 
65         1/1                    state_d = StEraseSuspend;
           Tests:       T23 T50 T153 
66         1/1                  end else if (done_i) begin
           Tests:       T7 T15 T23 
67         1/1                    ack_o = 1'b1;
           Tests:       T7 T15 T23 
68         1/1                    state_d = StEraseIdle;
           Tests:       T7 T15 T23 
69                              end
                        MISSING_ELSE
70                            end
71                      
72                            StEraseSuspend: begin
73         1/1                  if (done_i) begin
           Tests:       T23 T12 T50 
74         1/1                    ack_o = 1'b1;
           Tests:       T23 T12 T50 
75         1/1                    state_d = StEraseIdle;
           Tests:       T23 T12 T50 
76                              end
                        MISSING_ELSE
77                            end
78                      
79                            default:;
80                          endcase // unique case (state_q)
81                        end
82                      
83         1/1            assign pg_erase_req_o = pg_erase_req_i & req_valid;
           Tests:       T1 T2 T3 
84         1/1            assign bk_erase_req_o = bk_erase_req_i & req_valid;
           Tests:       T1 T2 T3 
85         1/1            assign suspend_req_o = suspend_req_i & suspend_valid;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_erase

	Total	Covered	Percent
Conditions	18	16	88.89
Logical	18	16	88.89
Non-Logical	0	0
Event	0	0

 LINE       56
 EXPRESSION ((pg_erase_req_o || bk_erase_req_o) && ack_i)
             -----------------1----------------    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T15,T23

 LINE       56
 SUB-EXPRESSION (pg_erase_req_o || bk_erase_req_o)
                 -------1------    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T48,T49,T50
1	0	Covered	T7,T15,T23

 LINE       64
 EXPRESSION (suspend_req_i && ack_i)
             ------1------    --2--

-1-	-2-	Status	Tests
0	1	Covered	T7,T15,T23
1	0	Not Covered
1	1	Covered	T23,T50,T153

 LINE       83
 EXPRESSION (pg_erase_req_i & req_valid)
             -------1------   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T15,T23
1	1	Covered	T7,T15,T23

 LINE       84
 EXPRESSION (bk_erase_req_i & req_valid)
             -------1------   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T48,T49,T50
1	1	Covered	T48,T49,T50

 LINE       85
 EXPRESSION (suspend_req_i & suspend_valid)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T15,T23
1	0	Covered	T23,T97,T50
1	1	Covered	T23,T50,T153

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_erase

Summary for FSM :: state_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	4	4	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StEraseBusy	57	Covered	T7,T15,T23
StEraseIdle	68	Covered	T1,T2,T3
StEraseSuspend	65	Covered	T23,T50,T153

transitions	Line No.	Covered	Tests
StEraseBusy->StEraseIdle	68	Covered	T7,T15,T23
StEraseBusy->StEraseSuspend	65	Covered	T23,T50,T153
StEraseIdle->StEraseBusy	57	Covered	T7,T15,T23
StEraseSuspend->StEraseIdle	75	Covered	T23,T50,T153

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_erase

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
IF	39	2	2	100.00
CASE	52	8	8	100.00

39             if (!rst_ni) begin
               -1-  
40               state_q <= StEraseIdle;
                 ==>
41             end else begin
42               state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

52             unique case (state_q)
                      -1-  
53               StEraseIdle: begin
54                 req_valid = 1'b1;
55         
56                 if ((pg_erase_req_o || bk_erase_req_o) && ack_i) begin
                   -2-  
57                   state_d = StEraseBusy;
                     ==>
58                 end
                   MISSING_ELSE
                   ==>
59               end
60         
61               StEraseBusy: begin
62                 suspend_valid = '1;
63         
64                 if (suspend_req_i && ack_i) begin
                   -3-  
65                   state_d = StEraseSuspend;
                     ==>
66                 end else if (done_i) begin
                            -4-  
67                   ack_o = 1'b1;
                     ==>
68                   state_d = StEraseIdle;
69                 end
                   MISSING_ELSE
                   ==>
70               end
71         
72               StEraseSuspend: begin
73                 if (done_i) begin
                   -5-  
74                   ack_o = 1'b1;
                     ==>
75                   state_d = StEraseIdle;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78         
79               default:;
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StEraseIdle	1	-	-	-	Covered	T7,T15,T23
StEraseIdle	0	-	-	-	Covered	T1,T2,T3
StEraseBusy	-	1	-	-	Covered	T23,T50,T153
StEraseBusy	-	0	1	-	Covered	T7,T15,T23
StEraseBusy	-	0	0	-	Covered	T7,T15,T23
StEraseSuspend	-	-	-	1	Covered	T23,T12,T50
StEraseSuspend	-	-	-	0	Covered	T12
default	-	-	-	-	Covered	T12

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_erase

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	39	3	3	100.00
ALWAYS	47	17	17	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

38                        always_ff @(posedge clk_i or negedge rst_ni) begin
39         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
40         1/1                state_q <= StEraseIdle;
           Tests:       T1 T2 T3 
41                          end else begin
42         1/1                state_q <= state_d;
           Tests:       T1 T2 T3 
43                          end
44                        end
45                      
46                        always_comb begin
47         1/1              req_valid = 1'b0;
           Tests:       T1 T2 T3 
48         1/1              suspend_valid = 1'b0;
           Tests:       T1 T2 T3 
49         1/1              ack_o = 1'b0;
           Tests:       T1 T2 T3 
50         1/1              state_d = state_q;
           Tests:       T1 T2 T3 
51                      
52         1/1              unique case (state_q)
           Tests:       T1 T2 T3 
53                            StEraseIdle: begin
54         1/1                  req_valid = 1'b1;
           Tests:       T1 T2 T3 
55                      
56         1/1                  if ((pg_erase_req_o || bk_erase_req_o) && ack_i) begin
           Tests:       T1 T2 T3 
57         1/1                    state_d = StEraseBusy;
           Tests:       T15 T23 T27 
58                              end
                        MISSING_ELSE
59                            end
60                      
61                            StEraseBusy: begin
62         1/1                  suspend_valid = '1;
           Tests:       T15 T23 T27 
63                      
64         1/1                  if (suspend_req_i && ack_i) begin
           Tests:       T15 T23 T27 
65         1/1                    state_d = StEraseSuspend;
           Tests:       T97 T50 T153 
66         1/1                  end else if (done_i) begin
           Tests:       T15 T23 T27 
67         1/1                    ack_o = 1'b1;
           Tests:       T15 T23 T27 
68         1/1                    state_d = StEraseIdle;
           Tests:       T15 T23 T27 
69                              end
                        MISSING_ELSE
70                            end
71                      
72                            StEraseSuspend: begin
73         1/1                  if (done_i) begin
           Tests:       T97 T12 T50 
74         1/1                    ack_o = 1'b1;
           Tests:       T97 T12 T50 
75         1/1                    state_d = StEraseIdle;
           Tests:       T97 T12 T50 
76                              end
                        MISSING_ELSE
77                            end
78                      
79                            default:;
80                          endcase // unique case (state_q)
81                        end
82                      
83         1/1            assign pg_erase_req_o = pg_erase_req_i & req_valid;
           Tests:       T1 T2 T3 
84         1/1            assign bk_erase_req_o = bk_erase_req_i & req_valid;
           Tests:       T1 T2 T3 
85         1/1            assign suspend_req_o = suspend_req_i & suspend_valid;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_erase

	Total	Covered	Percent
Conditions	18	16	88.89
Logical	18	16	88.89
Non-Logical	0	0
Event	0	0

 LINE       56
 EXPRESSION ((pg_erase_req_o || bk_erase_req_o) && ack_i)
             -----------------1----------------    --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T15,T23,T27

 LINE       56
 SUB-EXPRESSION (pg_erase_req_o || bk_erase_req_o)
                 -------1------    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T36,T51,T50
1	0	Covered	T15,T23,T27

 LINE       64
 EXPRESSION (suspend_req_i && ack_i)
             ------1------    --2--

-1-	-2-	Status	Tests
0	1	Covered	T15,T23,T27
1	0	Not Covered
1	1	Covered	T97,T50,T153

 LINE       83
 EXPRESSION (pg_erase_req_i & req_valid)
             -------1------   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T15,T23,T27
1	1	Covered	T15,T23,T27

 LINE       84
 EXPRESSION (bk_erase_req_i & req_valid)
             -------1------   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T36,T51,T50
1	1	Covered	T36,T51,T50

 LINE       85
 EXPRESSION (suspend_req_i & suspend_valid)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T15,T23,T27
1	0	Covered	T23,T97,T50
1	1	Covered	T97,T50,T153

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_erase

Summary for FSM :: state_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	4	4	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StEraseBusy	57	Covered	T15,T23,T27
StEraseIdle	68	Covered	T1,T2,T3
StEraseSuspend	65	Covered	T97,T50,T153

transitions	Line No.	Covered	Tests
StEraseBusy->StEraseIdle	68	Covered	T15,T23,T27
StEraseBusy->StEraseSuspend	65	Covered	T97,T50,T153
StEraseIdle->StEraseBusy	57	Covered	T15,T23,T27
StEraseSuspend->StEraseIdle	75	Covered	T97,T50,T153

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_erase

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
IF	39	2	2	100.00
CASE	52	8	8	100.00

39             if (!rst_ni) begin
               -1-  
40               state_q <= StEraseIdle;
                 ==>
41             end else begin
42               state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

52             unique case (state_q)
                      -1-  
53               StEraseIdle: begin
54                 req_valid = 1'b1;
55         
56                 if ((pg_erase_req_o || bk_erase_req_o) && ack_i) begin
                   -2-  
57                   state_d = StEraseBusy;
                     ==>
58                 end
                   MISSING_ELSE
                   ==>
59               end
60         
61               StEraseBusy: begin
62                 suspend_valid = '1;
63         
64                 if (suspend_req_i && ack_i) begin
                   -3-  
65                   state_d = StEraseSuspend;
                     ==>
66                 end else if (done_i) begin
                            -4-  
67                   ack_o = 1'b1;
                     ==>
68                   state_d = StEraseIdle;
69                 end
                   MISSING_ELSE
                   ==>
70               end
71         
72               StEraseSuspend: begin
73                 if (done_i) begin
                   -5-  
74                   ack_o = 1'b1;
                     ==>
75                   state_d = StEraseIdle;
76                 end
                   MISSING_ELSE
                   ==>
77               end
78         
79               default:;
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StEraseIdle	1	-	-	-	Covered	T15,T23,T27
StEraseIdle	0	-	-	-	Covered	T1,T2,T3
StEraseBusy	-	1	-	-	Covered	T97,T50,T153
StEraseBusy	-	0	1	-	Covered	T15,T23,T27
StEraseBusy	-	0	0	-	Covered	T15,T23,T27
StEraseSuspend	-	-	-	1	Covered	T97,T12,T50
StEraseSuspend	-	-	-	0	Covered	T12
default	-	-	-	-	Covered	T12