Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_generic_buf
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_buf_0/rtl/prim_generic_buf.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_data_bufs[0].u_dat_buf.gen_generic.u_impl_generic 0.00 0.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_data_bufs[1].u_dat_buf.gen_generic.u_impl_generic 0.00 0.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_data_bufs[0].u_dat_buf.gen_generic.u_impl_generic 0.00 0.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_data_bufs[1].u_dat_buf.gen_generic.u_impl_generic 0.00 0.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_data_bufs[0].u_dat_buf.gen_generic.u_impl_generic 0.00 0.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_data_bufs[1].u_dat_buf.gen_generic.u_impl_generic 0.00 0.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_data_bufs[0].u_dat_buf.gen_generic.u_impl_generic 0.00 0.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_data_bufs[1].u_dat_buf.gen_generic.u_impl_generic 0.00 0.00
tb.dut.u_reg_core.u_prim_reg_we_check.u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[2].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[2].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[2].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[2].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_disable_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_disable_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_disable_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_disable_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_disable_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_disable_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_disable_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_disable_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_disable_buf.gen_buffs[2].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_disable_buf.gen_buffs[2].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_disable_buf.gen_buffs[2].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_disable_buf.gen_buffs[2].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_disable_buf.gen_buffs[3].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_disable_buf.gen_buffs[3].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_disable_buf.gen_buffs[3].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_disable_buf.gen_buffs[3].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_disable_buf.gen_buffs[4].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_disable_buf.gen_buffs[4].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_disable_buf.gen_buffs[4].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_disable_buf.gen_buffs[4].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_disable_buf.gen_buffs[5].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_disable_buf.gen_buffs[5].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_disable_buf.gen_buffs[5].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_disable_buf.gen_buffs[5].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_disable_buf.gen_buffs[6].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_disable_buf.gen_buffs[6].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_disable_buf.gen_buffs[6].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_disable_buf.gen_buffs[6].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_disable_buf.gen_buffs[7].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_disable_buf.gen_buffs[7].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_disable_buf.gen_buffs[7].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_disable_buf.gen_buffs[7].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_exec_en_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_disable_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_disable_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_disable_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_disable_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_disable_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_disable_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_disable_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_disable_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_disable_buf.gen_buffs[2].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_disable_buf.gen_buffs[2].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_disable_buf.gen_buffs[2].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_disable_buf.gen_buffs[2].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].u_req_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_data_bufs[0].u_dat_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_data_bufs[1].u_dat_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].u_req_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_data_bufs[0].u_dat_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_data_bufs[1].u_dat_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].u_req_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_data_bufs[0].u_dat_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_data_bufs[1].u_dat_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].u_req_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_data_bufs[0].u_dat_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_data_bufs[1].u_dat_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_prim_reg_we_check.u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[2].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[2].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[2].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[2].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[3].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[3].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[3].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[3].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].u_req_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].u_req_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_prim_buf_data_xor_out.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_intg_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_rd.gen_bus_words_intg[0].u_prim_buf_intg.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_rd.gen_bus_words_intg[1].u_prim_buf_intg.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[2].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[2].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[2].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[2].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[3].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[3].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[3].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[3].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].u_req_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].u_req_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_prim_buf_data_xor_out.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_intg_buf.u_secure_anchor_buf.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_rd.gen_bus_words_intg[0].u_prim_buf_intg.gen_generic.u_impl_generic 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_rd.gen_bus_words_intg[1].u_prim_buf_intg.gen_generic.u_impl_generic 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_data_bufs[0].u_dat_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_input_bufs[0].gen_data_bufs[0].u_dat_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_data_bufs[1].u_dat_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_input_bufs[0].gen_data_bufs[1].u_dat_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_data_bufs[0].u_dat_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_input_bufs[1].gen_data_bufs[0].u_dat_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_data_bufs[1].u_dat_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_input_bufs[1].gen_data_bufs[1].u_dat_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_data_bufs[0].u_dat_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_input_bufs[0].gen_data_bufs[0].u_dat_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_data_bufs[1].u_dat_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_input_bufs[0].gen_data_bufs[1].u_dat_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_data_bufs[0].u_dat_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_input_bufs[1].gen_data_bufs[0].u_dat_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_data_bufs[1].u_dat_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_input_bufs[1].gen_data_bufs[1].u_dat_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_prim_reg_we_check.u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[2].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[2].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[2].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[2].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_disable_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_disable_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_disable_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_disable_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_disable_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_disable_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_disable_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_disable_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_disable_buf.gen_buffs[2].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[2].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_disable_buf.gen_buffs[2].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[2].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_disable_buf.gen_buffs[2].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[2].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_disable_buf.gen_buffs[2].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[2].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_disable_buf.gen_buffs[3].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[3].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_disable_buf.gen_buffs[3].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[3].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_disable_buf.gen_buffs[3].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[3].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_disable_buf.gen_buffs[3].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[3].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_disable_buf.gen_buffs[4].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[4].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_disable_buf.gen_buffs[4].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[4].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_disable_buf.gen_buffs[4].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[4].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_disable_buf.gen_buffs[4].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[4].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_disable_buf.gen_buffs[5].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[5].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_disable_buf.gen_buffs[5].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[5].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_disable_buf.gen_buffs[5].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[5].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_disable_buf.gen_buffs[5].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[5].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_disable_buf.gen_buffs[6].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[6].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_disable_buf.gen_buffs[6].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[6].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_disable_buf.gen_buffs[6].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[6].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_disable_buf.gen_buffs[6].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[6].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_disable_buf.gen_buffs[7].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[7].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_disable_buf.gen_buffs[7].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[7].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_disable_buf.gen_buffs[7].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[7].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_disable_buf.gen_buffs[7].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[7].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_exec_en_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_disable_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_disable_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_disable_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_disable_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_disable_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_disable_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_disable_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_disable_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_disable_buf.gen_buffs[2].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[2].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_disable_buf.gen_buffs[2].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[2].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_disable_buf.gen_buffs[2].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[2].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_disable_buf.gen_buffs[2].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[2].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].u_req_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_input_bufs[0].u_req_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_data_bufs[0].u_dat_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_input_bufs[0].gen_data_bufs[0].u_dat_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_data_bufs[1].u_dat_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_input_bufs[0].gen_data_bufs[1].u_dat_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].u_req_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_input_bufs[1].u_req_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_data_bufs[0].u_dat_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_input_bufs[1].gen_data_bufs[0].u_dat_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_data_bufs[1].u_dat_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_input_bufs[1].gen_data_bufs[1].u_dat_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].u_req_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_input_bufs[0].u_req_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_data_bufs[0].u_dat_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_input_bufs[0].gen_data_bufs[0].u_dat_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_data_bufs[1].u_dat_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_input_bufs[0].gen_data_bufs[1].u_dat_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].u_req_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_input_bufs[1].u_req_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_data_bufs[0].u_dat_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_input_bufs[1].gen_data_bufs[0].u_dat_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_data_bufs[1].u_dat_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_input_bufs[1].gen_data_bufs[1].u_dat_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_prim_reg_we_check.u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[2].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[2].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[2].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[2].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[2].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[2].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[2].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[2].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[3].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[3].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[3].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[3].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[3].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[3].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[3].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[3].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].u_req_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_input_bufs[0].u_req_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].u_req_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_input_bufs[1].u_req_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_prim_buf_data_xor_out.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_buf_data_xor_out


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_intg_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_rd.gen_bus_words_intg[0].u_prim_buf_intg.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_rd.gen_bus_words_intg[0].u_prim_buf_intg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_rd.gen_bus_words_intg[1].u_prim_buf_intg.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_rd.gen_bus_words_intg[1].u_prim_buf_intg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[0].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[1].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[2].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[2].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[2].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[2].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[2].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[2].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[2].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[2].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[3].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[3].gen_bits[0].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[3].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[3].gen_bits[1].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[3].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[3].gen_bits[2].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[3].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_buffs[3].gen_bits[3].u_prim_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].u_req_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_input_bufs[0].u_req_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].u_req_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_input_bufs[1].u_req_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_prim_buf_data_xor_out.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_buf_data_xor_out


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_intg_buf.u_secure_anchor_buf.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_secure_anchor_buf


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_rd.gen_bus_words_intg[0].u_prim_buf_intg.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_rd.gen_bus_words_intg[0].u_prim_buf_intg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_rd.gen_bus_words_intg[1].u_prim_buf_intg.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_rd.gen_bus_words_intg[1].u_prim_buf_intg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_buf
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_data_bufs[0].u_dat_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL200.00
CONT_ASSIGN15100.00
CONT_ASSIGN16100.00

14 logic [Width-1:0] inv; 15 0/1 ==> assign inv = ~in_i; 16 0/1 ==> assign out_o = ~inv;
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_data_bufs[1].u_dat_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL200.00
CONT_ASSIGN15100.00
CONT_ASSIGN16100.00

14 logic [Width-1:0] inv; 15 0/1 ==> assign inv = ~in_i; 16 0/1 ==> assign out_o = ~inv;
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_data_bufs[0].u_dat_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL200.00
CONT_ASSIGN15100.00
CONT_ASSIGN16100.00

14 logic [Width-1:0] inv; 15 0/1 ==> assign inv = ~in_i; 16 0/1 ==> assign out_o = ~inv;
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_data_bufs[1].u_dat_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL200.00
CONT_ASSIGN15100.00
CONT_ASSIGN16100.00

14 logic [Width-1:0] inv; 15 0/1 ==> assign inv = ~in_i; 16 0/1 ==> assign out_o = ~inv;
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_data_bufs[0].u_dat_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL200.00
CONT_ASSIGN15100.00
CONT_ASSIGN16100.00

14 logic [Width-1:0] inv; 15 0/1 ==> assign inv = ~in_i; 16 0/1 ==> assign out_o = ~inv;
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_data_bufs[1].u_dat_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL200.00
CONT_ASSIGN15100.00
CONT_ASSIGN16100.00

14 logic [Width-1:0] inv; 15 0/1 ==> assign inv = ~in_i; 16 0/1 ==> assign out_o = ~inv;
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_data_bufs[0].u_dat_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL200.00
CONT_ASSIGN15100.00
CONT_ASSIGN16100.00

14 logic [Width-1:0] inv; 15 0/1 ==> assign inv = ~in_i; 16 0/1 ==> assign out_o = ~inv;
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_data_bufs[1].u_dat_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL200.00
CONT_ASSIGN15100.00
CONT_ASSIGN16100.00

14 logic [Width-1:0] inv; 15 0/1 ==> assign inv = ~in_i; 16 0/1 ==> assign out_o = ~inv;
Line Coverage for Instance : tb.dut.u_reg_core.u_prim_reg_we_check.u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi.gen_sec_buf.u_prim_sec_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_lc_seed_hw_rd_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[2].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[2].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[2].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_rma_req.gen_buffs[2].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_prog_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_lc_escalation_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_disable_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_disable_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_disable_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_disable_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_disable_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_disable_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_disable_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_disable_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_disable_buf.gen_buffs[2].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_disable_buf.gen_buffs[2].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_disable_buf.gen_buffs[2].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_disable_buf.gen_buffs[2].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_disable_buf.gen_buffs[3].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_disable_buf.gen_buffs[3].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_disable_buf.gen_buffs[3].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_disable_buf.gen_buffs[3].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_disable_buf.gen_buffs[4].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_disable_buf.gen_buffs[4].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_disable_buf.gen_buffs[4].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_disable_buf.gen_buffs[4].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_disable_buf.gen_buffs[5].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_disable_buf.gen_buffs[5].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_disable_buf.gen_buffs[5].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_disable_buf.gen_buffs[5].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_disable_buf.gen_buffs[6].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_disable_buf.gen_buffs[6].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_disable_buf.gen_buffs[6].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_disable_buf.gen_buffs[6].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_disable_buf.gen_buffs[7].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_disable_buf.gen_buffs[7].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_disable_buf.gen_buffs[7].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_disable_buf.gen_buffs[7].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_exec_en_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_tl_gate.u_err_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_disable_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_disable_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_disable_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_disable_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_disable_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_disable_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_disable_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_disable_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_disable_buf.gen_buffs[2].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_disable_buf.gen_buffs[2].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_disable_buf.gen_buffs[2].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_disable_buf.gen_buffs[2].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].u_req_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_data_bufs[0].u_dat_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_data_bufs[1].u_dat_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].u_req_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_data_bufs[0].u_dat_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_data_bufs[1].u_dat_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].u_req_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_data_bufs[0].u_dat_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_data_bufs[1].u_dat_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].u_req_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_data_bufs[0].u_dat_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_data_bufs[1].u_dat_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[0].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[1].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[2].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[3].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[0].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[1].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[2].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_buffs[4].gen_bits[3].u_prim_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_prim_reg_we_check.u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T72 T114 T73  16 1/1 assign out_o = ~inv; Tests: T72 T114 T73 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[2].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[2].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[2].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[2].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[3].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[3].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[3].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_buffs[3].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].u_req_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].u_req_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_prim_buf_data_xor_out.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_intg_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_rd.gen_bus_words_intg[0].u_prim_buf_intg.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_rd.gen_bus_words_intg[1].u_prim_buf_intg.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[0].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[0].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[0].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[0].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[1].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[1].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[1].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[1].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[2].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[2].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[2].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[2].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[3].gen_bits[0].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[3].gen_bits[1].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[3].gen_bits[2].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_buffs[3].gen_bits[3].u_prim_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].u_req_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].u_req_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_prim_buf_data_xor_out.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_intg_buf.u_secure_anchor_buf.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_rd.gen_bus_words_intg[0].u_prim_buf_intg.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_rd.gen_bus_words_intg[1].u_prim_buf_intg.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN1511100.00
CONT_ASSIGN1611100.00

14 logic [Width-1:0] inv; 15 1/1 assign inv = ~in_i; Tests: T1 T2 T3  16 1/1 assign out_o = ~inv; Tests: T1 T2 T3 
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%