Module Definition
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Module : prim_fifo_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.07 100.00 72.29 100.00 100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_to_prog_fifo.u_sramreqfifo 67.47 85.71 38.46 85.71 60.00
tb.dut.u_to_prog_fifo.u_rspfifo 71.27 92.31 47.06 85.71 60.00
tb.dut.u_to_rd_fifo.u_sramreqfifo 90.62 100.00 62.50 100.00 100.00
tb.dut.u_to_prog_fifo.u_reqfifo 92.19 100.00 68.75 100.00 100.00
tb.dut.u_to_rd_fifo.u_reqfifo 92.19 100.00 68.75 100.00 100.00
tb.dut.u_tl_adapter_eflash.u_reqfifo 92.19 100.00 68.75 100.00 100.00
tb.dut.u_tl_adapter_eflash.u_sramreqfifo 92.19 100.00 68.75 100.00 100.00
tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo 92.19 100.00 68.75 100.00 100.00
tb.dut.u_eflash.u_bank_sequence_fifo 92.19 100.00 68.75 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo 92.19 100.00 68.75 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage 92.19 100.00 68.75 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage 92.19 100.00 68.75 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_addr_xor_storage 92.19 100.00 68.75 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo 92.19 100.00 68.75 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage 92.19 100.00 68.75 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage 92.19 100.00 68.75 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_addr_xor_storage 92.19 100.00 68.75 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo 93.75 100.00 75.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo 93.75 100.00 75.00 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo 93.75 100.00 75.00 100.00 100.00
tb.dut.u_sw_rd_fifo 94.79 100.00 79.17 100.00 100.00
tb.dut.u_tl_adapter_eflash.u_rspfifo 94.79 100.00 79.17 100.00 100.00
tb.dut.u_prog_fifo 95.83 100.00 83.33 100.00 100.00
tb.dut.u_to_rd_fifo.u_rspfifo 95.83 100.00 83.33 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo 95.83 100.00 83.33 100.00 100.00
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo 100.00 100.00 100.00
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo 100.00 100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo 100.00 100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo 100.00 100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo 100.00 100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo 100.00 100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo 100.00 100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo 100.00 100.00 100.00

Line Coverage for Module : prim_fifo_sync ( parameter Width=109,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo

Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300

43 // device facing 44 1/1 assign rvalid_o = wvalid_i; Tests: T1 T2 T3  45 1/1 assign rdata_o = wdata_i; Tests: T1 T2 T3  46 47 // host facing 48 1/1 assign wready_o = rready_i; Tests: T1 T2 T3  49 1/1 assign full_o = rready_i; Tests: T1 T2 T3  50 51 // this avoids lint warnings 52 logic unused_clr; 53 unreachable assign unused_clr = clr_i;

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=1,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
92.19 100.00
tb.dut.u_to_prog_fifo.u_reqfifo

SCORELINE
92.19 100.00
tb.dut.u_to_rd_fifo.u_reqfifo

Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00

68 always_ff @(posedge clk_i or negedge rst_ni) begin 69 1/1 if (!rst_ni) begin Tests: T1 T2 T3  70 1/1 under_rst <= 1'b1; Tests: T1 T2 T3  71 1/1 end else if (under_rst) begin Tests: T1 T2 T3  72 1/1 under_rst <= ~under_rst; Tests: T1 T2 T3  73 end MISSING_ELSE 74 end 75 76 logic empty; 77 78 // full and not ready for write are two different concepts. 79 // The latter can be '0' when under reset, while the former is an indication that no more 80 // entries can be written. 81 1/1 assign wready_o = ~full_o & ~under_rst; Tests: T1 T2 T3  82 1/1 assign rvalid_o = ~empty & ~under_rst; Tests: T1 T2 T3  83 84 prim_fifo_sync_cnt #( 85 .Depth(Depth), 86 .Secure(Secure) 87 ) u_fifo_cnt ( 88 .clk_i, 89 .rst_ni, 90 .clr_i, 91 .incr_wptr_i(fifo_incr_wptr), 92 .incr_rptr_i(fifo_incr_rptr), 93 .wptr_o(fifo_wptr), 94 .rptr_o(fifo_rptr), 95 .full_o, 96 .empty_o(fifo_empty), 97 .depth_o, 98 .err_o 99 ); 100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst; Tests: T1 T2 T3  101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst; Tests: T1 T2 T3  102 103 // the generate blocks below are needed to avoid lint errors due to array indexing 104 // in the where the fifo only has one storage element 105 logic [Depth-1:0][Width-1:0] storage; 106 logic [Width-1:0] storage_rdata; 107 if (Depth == 1) begin : gen_depth_eq1 108 1/1 assign storage_rdata = storage[0]; Tests: T1 T2 T3  109 110 always_ff @(posedge clk_i) 111 1/1 if (fifo_incr_wptr) begin Tests: T1 T2 T3  112 1/1 storage[0] <= wdata_i; Tests: T1 T2 T3  113 end MISSING_ELSE 114 115 logic unused_ptrs; 116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr}; Tests: T1 T2 T3  117 118 // fifo with more than one storage element 119 end else begin : gen_depth_gt1 120 assign storage_rdata = storage[fifo_rptr]; 121 122 always_ff @(posedge clk_i) 123 if (fifo_incr_wptr) begin 124 storage[fifo_wptr] <= wdata_i; 125 end 126 end 127 128 logic [Width-1:0] rdata_int; 129 if (Pass == 1'b1) begin : gen_pass 130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata; 131 assign empty = fifo_empty & ~wvalid_i; 132 end else begin : gen_nopass 133 1/1 assign rdata_int = storage_rdata; Tests: T1 T2 T3  134 1/1 assign empty = fifo_empty; Tests: T1 T2 T3  135 end 136 137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero 138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int; Tests: T1 T2 T3 

Line Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=1,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
67.47 85.71
tb.dut.u_to_prog_fifo.u_sramreqfifo

SCORELINE
90.62 100.00
tb.dut.u_to_rd_fifo.u_sramreqfifo

Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00

68 always_ff @(posedge clk_i or negedge rst_ni) begin 69 1/1 if (!rst_ni) begin Tests: T1 T2 T3  70 1/1 under_rst <= 1'b1; Tests: T1 T2 T3  71 1/1 end else if (under_rst) begin Tests: T1 T2 T3  72 1/1 under_rst <= ~under_rst; Tests: T1 T2 T3  73 end MISSING_ELSE 74 end 75 76 logic empty; 77 78 // full and not ready for write are two different concepts. 79 // The latter can be '0' when under reset, while the former is an indication that no more 80 // entries can be written. 81 1/1 assign wready_o = ~full_o & ~under_rst; Tests: T1 T2 T3  82 1/1 assign rvalid_o = ~empty & ~under_rst; Tests: T1 T2 T3  83 84 prim_fifo_sync_cnt #( 85 .Depth(Depth), 86 .Secure(Secure) 87 ) u_fifo_cnt ( 88 .clk_i, 89 .rst_ni, 90 .clr_i, 91 .incr_wptr_i(fifo_incr_wptr), 92 .incr_rptr_i(fifo_incr_rptr), 93 .wptr_o(fifo_wptr), 94 .rptr_o(fifo_rptr), 95 .full_o, 96 .empty_o(fifo_empty), 97 .depth_o, 98 .err_o 99 ); 100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst; Tests: T1 T2 T3  101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst; Tests: T1 T2 T3  102 103 // the generate blocks below are needed to avoid lint errors due to array indexing 104 // in the where the fifo only has one storage element 105 logic [Depth-1:0][Width-1:0] storage; 106 logic [Width-1:0] storage_rdata; 107 if (Depth == 1) begin : gen_depth_eq1 108 1/1 assign storage_rdata = storage[0]; Tests: T2 T3 T7  109 110 always_ff @(posedge clk_i) 111 1/1 if (fifo_incr_wptr) begin Tests: T1 T2 T3  112 1/1 storage[0] <= wdata_i; Tests: T2 T3 T7  113 end MISSING_ELSE 114 115 logic unused_ptrs; 116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr}; Tests: T1 T2 T3  117 118 // fifo with more than one storage element 119 end else begin : gen_depth_gt1 120 assign storage_rdata = storage[fifo_rptr]; 121 122 always_ff @(posedge clk_i) 123 if (fifo_incr_wptr) begin 124 storage[fifo_wptr] <= wdata_i; 125 end 126 end 127 128 logic [Width-1:0] rdata_int; 129 if (Pass == 1'b1) begin : gen_pass 130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata; 131 assign empty = fifo_empty & ~wvalid_i; 132 end else begin : gen_nopass 133 1/1 assign rdata_int = storage_rdata; Tests: T2 T3 T7  134 1/1 assign empty = fifo_empty; Tests: T1 T2 T3  135 end 136 137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero 138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int; Tests: T1 T2 T3 

Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=1,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
71.27 92.31
tb.dut.u_to_prog_fifo.u_rspfifo

SCORELINE
95.83 100.00
tb.dut.u_to_rd_fifo.u_rspfifo

SCORELINE
95.83 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

SCORELINE
93.75 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo

Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00

68 always_ff @(posedge clk_i or negedge rst_ni) begin 69 1/1 if (!rst_ni) begin Tests: T1 T2 T3  70 1/1 under_rst <= 1'b1; Tests: T1 T2 T3  71 1/1 end else if (under_rst) begin Tests: T1 T2 T3  72 1/1 under_rst <= ~under_rst; Tests: T1 T2 T3  73 end MISSING_ELSE 74 end 75 76 logic empty; 77 78 // full and not ready for write are two different concepts. 79 // The latter can be '0' when under reset, while the former is an indication that no more 80 // entries can be written. 81 1/1 assign wready_o = ~full_o & ~under_rst; Tests: T1 T2 T3  82 1/1 assign rvalid_o = ~empty & ~under_rst; Tests: T1 T2 T3  83 84 prim_fifo_sync_cnt #( 85 .Depth(Depth), 86 .Secure(Secure) 87 ) u_fifo_cnt ( 88 .clk_i, 89 .rst_ni, 90 .clr_i, 91 .incr_wptr_i(fifo_incr_wptr), 92 .incr_rptr_i(fifo_incr_rptr), 93 .wptr_o(fifo_wptr), 94 .rptr_o(fifo_rptr), 95 .full_o, 96 .empty_o(fifo_empty), 97 .depth_o, 98 .err_o 99 ); 100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst; Tests: T1 T2 T3  101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst; Tests: T1 T2 T3  102 103 // the generate blocks below are needed to avoid lint errors due to array indexing 104 // in the where the fifo only has one storage element 105 logic [Depth-1:0][Width-1:0] storage; 106 logic [Width-1:0] storage_rdata; 107 if (Depth == 1) begin : gen_depth_eq1 108 1/1 assign storage_rdata = storage[0]; Tests: T2 T3 T7  109 110 always_ff @(posedge clk_i) 111 1/1 if (fifo_incr_wptr) begin Tests: T1 T2 T3  112 1/1 storage[0] <= wdata_i; Tests: T2 T3 T7  113 end MISSING_ELSE 114 115 logic unused_ptrs; 116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr}; Tests: T1 T2 T3  117 118 // fifo with more than one storage element 119 end else begin : gen_depth_gt1 120 assign storage_rdata = storage[fifo_rptr]; 121 122 always_ff @(posedge clk_i) 123 if (fifo_incr_wptr) begin 124 storage[fifo_wptr] <= wdata_i; 125 end 126 end 127 128 logic [Width-1:0] rdata_int; 129 if (Pass == 1'b1) begin : gen_pass 130 1/1 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata; Tests: T1 T2 T3  131 1/1 assign empty = fifo_empty & ~wvalid_i; Tests: T1 T2 T3  132 end else begin : gen_nopass 133 assign rdata_int = storage_rdata; 134 assign empty = fifo_empty; 135 end 136 137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero 138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int; Tests: T1 T2 T3 

Line Coverage for Module : prim_fifo_sync ( parameter Width=39,Pass=1,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=39,Pass=1,Depth=16,OutputZeroIfEmpty=1,Secure=0,DepthW=5,gen_normal_fifo.PtrW=4 )
Line Coverage for Module self-instances :
SCORELINE
95.83 100.00
tb.dut.u_prog_fifo

SCORELINE
94.79 100.00
tb.dut.u_sw_rd_fifo

Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00

68 always_ff @(posedge clk_i or negedge rst_ni) begin 69 1/1 if (!rst_ni) begin Tests: T1 T2 T3  70 1/1 under_rst <= 1'b1; Tests: T1 T2 T3  71 1/1 end else if (under_rst) begin Tests: T1 T2 T3  72 1/1 under_rst <= ~under_rst; Tests: T1 T2 T3  73 end MISSING_ELSE 74 end 75 76 logic empty; 77 78 // full and not ready for write are two different concepts. 79 // The latter can be '0' when under reset, while the former is an indication that no more 80 // entries can be written. 81 1/1 assign wready_o = ~full_o & ~under_rst; Tests: T1 T2 T3  82 1/1 assign rvalid_o = ~empty & ~under_rst; Tests: T1 T2 T3  83 84 prim_fifo_sync_cnt #( 85 .Depth(Depth), 86 .Secure(Secure) 87 ) u_fifo_cnt ( 88 .clk_i, 89 .rst_ni, 90 .clr_i, 91 .incr_wptr_i(fifo_incr_wptr), 92 .incr_rptr_i(fifo_incr_rptr), 93 .wptr_o(fifo_wptr), 94 .rptr_o(fifo_rptr), 95 .full_o, 96 .empty_o(fifo_empty), 97 .depth_o, 98 .err_o 99 ); 100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst; Tests: T1 T2 T3  101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst; Tests: T1 T2 T3  102 103 // the generate blocks below are needed to avoid lint errors due to array indexing 104 // in the where the fifo only has one storage element 105 logic [Depth-1:0][Width-1:0] storage; 106 logic [Width-1:0] storage_rdata; 107 if (Depth == 1) begin : gen_depth_eq1 108 assign storage_rdata = storage[0]; 109 110 always_ff @(posedge clk_i) 111 if (fifo_incr_wptr) begin 112 storage[0] <= wdata_i; 113 end 114 115 logic unused_ptrs; 116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr}; 117 118 // fifo with more than one storage element 119 end else begin : gen_depth_gt1 120 1/1 assign storage_rdata = storage[fifo_rptr]; Tests: T1 T2 T3  121 122 always_ff @(posedge clk_i) 123 1/1 if (fifo_incr_wptr) begin Tests: T1 T2 T3  124 1/1 storage[fifo_wptr] <= wdata_i; Tests: T1 T2 T3  125 end MISSING_ELSE 126 end 127 128 logic [Width-1:0] rdata_int; 129 if (Pass == 1'b1) begin : gen_pass 130 1/1 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata; Tests: T1 T2 T3  131 1/1 assign empty = fifo_empty & ~wvalid_i; Tests: T1 T2 T3  132 end else begin : gen_nopass 133 assign rdata_int = storage_rdata; 134 assign empty = fifo_empty; 135 end 136 137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero 138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int; Tests: T1 T2 T3 

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 + Width=17,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
92.19 100.00
tb.dut.u_tl_adapter_eflash.u_reqfifo

SCORELINE
92.19 100.00
tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo

Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00

68 always_ff @(posedge clk_i or negedge rst_ni) begin 69 1/1 if (!rst_ni) begin Tests: T1 T2 T3  70 1/1 under_rst <= 1'b1; Tests: T1 T2 T3  71 1/1 end else if (under_rst) begin Tests: T1 T2 T3  72 1/1 under_rst <= ~under_rst; Tests: T1 T2 T3  73 end MISSING_ELSE 74 end 75 76 logic empty; 77 78 // full and not ready for write are two different concepts. 79 // The latter can be '0' when under reset, while the former is an indication that no more 80 // entries can be written. 81 1/1 assign wready_o = ~full_o & ~under_rst; Tests: T1 T2 T3  82 1/1 assign rvalid_o = ~empty & ~under_rst; Tests: T1 T2 T3  83 84 prim_fifo_sync_cnt #( 85 .Depth(Depth), 86 .Secure(Secure) 87 ) u_fifo_cnt ( 88 .clk_i, 89 .rst_ni, 90 .clr_i, 91 .incr_wptr_i(fifo_incr_wptr), 92 .incr_rptr_i(fifo_incr_rptr), 93 .wptr_o(fifo_wptr), 94 .rptr_o(fifo_rptr), 95 .full_o, 96 .empty_o(fifo_empty), 97 .depth_o, 98 .err_o 99 ); 100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst; Tests: T1 T2 T3  101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst; Tests: T1 T2 T3  102 103 // the generate blocks below are needed to avoid lint errors due to array indexing 104 // in the where the fifo only has one storage element 105 logic [Depth-1:0][Width-1:0] storage; 106 logic [Width-1:0] storage_rdata; 107 if (Depth == 1) begin : gen_depth_eq1 108 assign storage_rdata = storage[0]; 109 110 always_ff @(posedge clk_i) 111 if (fifo_incr_wptr) begin 112 storage[0] <= wdata_i; 113 end 114 115 logic unused_ptrs; 116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr}; 117 118 // fifo with more than one storage element 119 end else begin : gen_depth_gt1 120 1/1 assign storage_rdata = storage[fifo_rptr]; Tests: T1 T2 T3  121 122 always_ff @(posedge clk_i) 123 1/1 if (fifo_incr_wptr) begin Tests: T1 T2 T3  124 1/1 storage[fifo_wptr] <= wdata_i; Tests: T2 T13 T16  125 end MISSING_ELSE 126 end 127 128 logic [Width-1:0] rdata_int; 129 if (Pass == 1'b1) begin : gen_pass 130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata; 131 assign empty = fifo_empty & ~wvalid_i; 132 end else begin : gen_nopass 133 1/1 assign rdata_int = storage_rdata; Tests: T2 T13 T16  134 1/1 assign empty = fifo_empty; Tests: T1 T2 T3  135 end 136 137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero 138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int; Tests: T1 T2 T3 

Line Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
92.19 100.00
tb.dut.u_tl_adapter_eflash.u_sramreqfifo

Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00

68 always_ff @(posedge clk_i or negedge rst_ni) begin 69 1/1 if (!rst_ni) begin Tests: T1 T2 T3  70 1/1 under_rst <= 1'b1; Tests: T1 T2 T3  71 1/1 end else if (under_rst) begin Tests: T1 T2 T3  72 1/1 under_rst <= ~under_rst; Tests: T1 T2 T3  73 end MISSING_ELSE 74 end 75 76 logic empty; 77 78 // full and not ready for write are two different concepts. 79 // The latter can be '0' when under reset, while the former is an indication that no more 80 // entries can be written. 81 1/1 assign wready_o = ~full_o & ~under_rst; Tests: T1 T2 T3  82 1/1 assign rvalid_o = ~empty & ~under_rst; Tests: T1 T2 T3  83 84 prim_fifo_sync_cnt #( 85 .Depth(Depth), 86 .Secure(Secure) 87 ) u_fifo_cnt ( 88 .clk_i, 89 .rst_ni, 90 .clr_i, 91 .incr_wptr_i(fifo_incr_wptr), 92 .incr_rptr_i(fifo_incr_rptr), 93 .wptr_o(fifo_wptr), 94 .rptr_o(fifo_rptr), 95 .full_o, 96 .empty_o(fifo_empty), 97 .depth_o, 98 .err_o 99 ); 100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst; Tests: T1 T2 T3  101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst; Tests: T1 T2 T3  102 103 // the generate blocks below are needed to avoid lint errors due to array indexing 104 // in the where the fifo only has one storage element 105 logic [Depth-1:0][Width-1:0] storage; 106 logic [Width-1:0] storage_rdata; 107 if (Depth == 1) begin : gen_depth_eq1 108 assign storage_rdata = storage[0]; 109 110 always_ff @(posedge clk_i) 111 if (fifo_incr_wptr) begin 112 storage[0] <= wdata_i; 113 end 114 115 logic unused_ptrs; 116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr}; 117 118 // fifo with more than one storage element 119 end else begin : gen_depth_gt1 120 1/1 assign storage_rdata = storage[fifo_rptr]; Tests: T1 T2 T3  121 122 always_ff @(posedge clk_i) 123 1/1 if (fifo_incr_wptr) begin Tests: T1 T2 T3  124 1/1 storage[fifo_wptr] <= wdata_i; Tests: T2 T13 T16  125 end MISSING_ELSE 126 end 127 128 logic [Width-1:0] rdata_int; 129 if (Pass == 1'b1) begin : gen_pass 130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata; 131 assign empty = fifo_empty & ~wvalid_i; 132 end else begin : gen_nopass 133 1/1 assign rdata_int = storage_rdata; Tests: T2 T13 T16  134 1/1 assign empty = fifo_empty; Tests: T1 T2 T3  135 end 136 137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero 138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int; Tests: T1 T2 T3 

Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
94.79 100.00
tb.dut.u_tl_adapter_eflash.u_rspfifo

Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00

68 always_ff @(posedge clk_i or negedge rst_ni) begin 69 1/1 if (!rst_ni) begin Tests: T1 T2 T3  70 1/1 under_rst <= 1'b1; Tests: T1 T2 T3  71 1/1 end else if (under_rst) begin Tests: T1 T2 T3  72 1/1 under_rst <= ~under_rst; Tests: T1 T2 T3  73 end MISSING_ELSE 74 end 75 76 logic empty; 77 78 // full and not ready for write are two different concepts. 79 // The latter can be '0' when under reset, while the former is an indication that no more 80 // entries can be written. 81 1/1 assign wready_o = ~full_o & ~under_rst; Tests: T1 T2 T3  82 1/1 assign rvalid_o = ~empty & ~under_rst; Tests: T1 T2 T3  83 84 prim_fifo_sync_cnt #( 85 .Depth(Depth), 86 .Secure(Secure) 87 ) u_fifo_cnt ( 88 .clk_i, 89 .rst_ni, 90 .clr_i, 91 .incr_wptr_i(fifo_incr_wptr), 92 .incr_rptr_i(fifo_incr_rptr), 93 .wptr_o(fifo_wptr), 94 .rptr_o(fifo_rptr), 95 .full_o, 96 .empty_o(fifo_empty), 97 .depth_o, 98 .err_o 99 ); 100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst; Tests: T1 T2 T3  101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst; Tests: T1 T2 T3  102 103 // the generate blocks below are needed to avoid lint errors due to array indexing 104 // in the where the fifo only has one storage element 105 logic [Depth-1:0][Width-1:0] storage; 106 logic [Width-1:0] storage_rdata; 107 if (Depth == 1) begin : gen_depth_eq1 108 assign storage_rdata = storage[0]; 109 110 always_ff @(posedge clk_i) 111 if (fifo_incr_wptr) begin 112 storage[0] <= wdata_i; 113 end 114 115 logic unused_ptrs; 116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr}; 117 118 // fifo with more than one storage element 119 end else begin : gen_depth_gt1 120 1/1 assign storage_rdata = storage[fifo_rptr]; Tests: T1 T2 T3  121 122 always_ff @(posedge clk_i) 123 1/1 if (fifo_incr_wptr) begin Tests: T1 T2 T3  124 1/1 storage[fifo_wptr] <= wdata_i; Tests: T2 T13 T16  125 end MISSING_ELSE 126 end 127 128 logic [Width-1:0] rdata_int; 129 if (Pass == 1'b1) begin : gen_pass 130 1/1 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata; Tests: T1 T2 T3  131 1/1 assign empty = fifo_empty & ~wvalid_i; Tests: T1 T2 T3  132 end else begin : gen_nopass 133 assign rdata_int = storage_rdata; 134 assign empty = fifo_empty; 135 end 136 137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero 138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int; Tests: T1 T2 T3 

Line Coverage for Module : prim_fifo_sync ( parameter Width=1,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
92.19 100.00
tb.dut.u_eflash.u_bank_sequence_fifo

Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00

68 always_ff @(posedge clk_i or negedge rst_ni) begin 69 1/1 if (!rst_ni) begin Tests: T1 T2 T3  70 1/1 under_rst <= 1'b1; Tests: T1 T2 T3  71 1/1 end else if (under_rst) begin Tests: T1 T2 T3  72 1/1 under_rst <= ~under_rst; Tests: T1 T2 T3  73 end MISSING_ELSE 74 end 75 76 logic empty; 77 78 // full and not ready for write are two different concepts. 79 // The latter can be '0' when under reset, while the former is an indication that no more 80 // entries can be written. 81 1/1 assign wready_o = ~full_o & ~under_rst; Tests: T1 T2 T3  82 1/1 assign rvalid_o = ~empty & ~under_rst; Tests: T1 T2 T3  83 84 prim_fifo_sync_cnt #( 85 .Depth(Depth), 86 .Secure(Secure) 87 ) u_fifo_cnt ( 88 .clk_i, 89 .rst_ni, 90 .clr_i, 91 .incr_wptr_i(fifo_incr_wptr), 92 .incr_rptr_i(fifo_incr_rptr), 93 .wptr_o(fifo_wptr), 94 .rptr_o(fifo_rptr), 95 .full_o, 96 .empty_o(fifo_empty), 97 .depth_o, 98 .err_o 99 ); 100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst; Tests: T1 T2 T3  101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst; Tests: T1 T2 T3  102 103 // the generate blocks below are needed to avoid lint errors due to array indexing 104 // in the where the fifo only has one storage element 105 logic [Depth-1:0][Width-1:0] storage; 106 logic [Width-1:0] storage_rdata; 107 if (Depth == 1) begin : gen_depth_eq1 108 assign storage_rdata = storage[0]; 109 110 always_ff @(posedge clk_i) 111 if (fifo_incr_wptr) begin 112 storage[0] <= wdata_i; 113 end 114 115 logic unused_ptrs; 116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr}; 117 118 // fifo with more than one storage element 119 end else begin : gen_depth_gt1 120 1/1 assign storage_rdata = storage[fifo_rptr]; Tests: T1 T2 T3  121 122 always_ff @(posedge clk_i) 123 1/1 if (fifo_incr_wptr) begin Tests: T1 T2 T3  124 1/1 storage[fifo_wptr] <= wdata_i; Tests: T2 T13 T16  125 end MISSING_ELSE 126 end 127 128 logic [Width-1:0] rdata_int; 129 if (Pass == 1'b1) begin : gen_pass 130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata; 131 assign empty = fifo_empty & ~wvalid_i; 132 end else begin : gen_nopass 133 1/1 assign rdata_int = storage_rdata; Tests: T2 T13 T16  134 1/1 assign empty = fifo_empty; Tests: T1 T2 T3  135 end 136 137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero 138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int; Tests: T1 T2 T3 

Line Coverage for Module : prim_fifo_sync ( parameter Width=6,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
92.19 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo

SCORELINE
92.19 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo

Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00

68 always_ff @(posedge clk_i or negedge rst_ni) begin 69 1/1 if (!rst_ni) begin Tests: T1 T2 T3  70 1/1 under_rst <= 1'b1; Tests: T1 T2 T3  71 1/1 end else if (under_rst) begin Tests: T1 T2 T3  72 1/1 under_rst <= ~under_rst; Tests: T1 T2 T3  73 end MISSING_ELSE 74 end 75 76 logic empty; 77 78 // full and not ready for write are two different concepts. 79 // The latter can be '0' when under reset, while the former is an indication that no more 80 // entries can be written. 81 1/1 assign wready_o = ~full_o & ~under_rst; Tests: T1 T2 T3  82 1/1 assign rvalid_o = ~empty & ~under_rst; Tests: T1 T2 T3  83 84 prim_fifo_sync_cnt #( 85 .Depth(Depth), 86 .Secure(Secure) 87 ) u_fifo_cnt ( 88 .clk_i, 89 .rst_ni, 90 .clr_i, 91 .incr_wptr_i(fifo_incr_wptr), 92 .incr_rptr_i(fifo_incr_rptr), 93 .wptr_o(fifo_wptr), 94 .rptr_o(fifo_rptr), 95 .full_o, 96 .empty_o(fifo_empty), 97 .depth_o, 98 .err_o 99 ); 100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst; Tests: T1 T2 T3  101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst; Tests: T1 T2 T3  102 103 // the generate blocks below are needed to avoid lint errors due to array indexing 104 // in the where the fifo only has one storage element 105 logic [Depth-1:0][Width-1:0] storage; 106 logic [Width-1:0] storage_rdata; 107 if (Depth == 1) begin : gen_depth_eq1 108 assign storage_rdata = storage[0]; 109 110 always_ff @(posedge clk_i) 111 if (fifo_incr_wptr) begin 112 storage[0] <= wdata_i; 113 end 114 115 logic unused_ptrs; 116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr}; 117 118 // fifo with more than one storage element 119 end else begin : gen_depth_gt1 120 1/1 assign storage_rdata = storage[fifo_rptr]; Tests: T1 T2 T3  121 122 always_ff @(posedge clk_i) 123 1/1 if (fifo_incr_wptr) begin Tests: T1 T2 T3  124 1/1 storage[fifo_wptr] <= wdata_i; Tests: T1 T2 T3  125 end MISSING_ELSE 126 end 127 128 logic [Width-1:0] rdata_int; 129 if (Pass == 1'b1) begin : gen_pass 130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata; 131 assign empty = fifo_empty & ~wvalid_i; 132 end else begin : gen_nopass 133 1/1 assign rdata_int = storage_rdata; Tests: T1 T2 T3  134 1/1 assign empty = fifo_empty; Tests: T1 T2 T3  135 end 136 137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero 138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int; Tests: T1 T2 T3 

Line Coverage for Module : prim_fifo_sync ( parameter Width=76,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
92.19 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

SCORELINE
92.19 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage

Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00

68 always_ff @(posedge clk_i or negedge rst_ni) begin 69 1/1 if (!rst_ni) begin Tests: T1 T2 T3  70 1/1 under_rst <= 1'b1; Tests: T1 T2 T3  71 1/1 end else if (under_rst) begin Tests: T1 T2 T3  72 1/1 under_rst <= ~under_rst; Tests: T1 T2 T3  73 end MISSING_ELSE 74 end 75 76 logic empty; 77 78 // full and not ready for write are two different concepts. 79 // The latter can be '0' when under reset, while the former is an indication that no more 80 // entries can be written. 81 1/1 assign wready_o = ~full_o & ~under_rst; Tests: T1 T2 T3  82 1/1 assign rvalid_o = ~empty & ~under_rst; Tests: T1 T2 T3  83 84 prim_fifo_sync_cnt #( 85 .Depth(Depth), 86 .Secure(Secure) 87 ) u_fifo_cnt ( 88 .clk_i, 89 .rst_ni, 90 .clr_i, 91 .incr_wptr_i(fifo_incr_wptr), 92 .incr_rptr_i(fifo_incr_rptr), 93 .wptr_o(fifo_wptr), 94 .rptr_o(fifo_rptr), 95 .full_o, 96 .empty_o(fifo_empty), 97 .depth_o, 98 .err_o 99 ); 100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst; Tests: T1 T2 T3  101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst; Tests: T1 T2 T3  102 103 // the generate blocks below are needed to avoid lint errors due to array indexing 104 // in the where the fifo only has one storage element 105 logic [Depth-1:0][Width-1:0] storage; 106 logic [Width-1:0] storage_rdata; 107 if (Depth == 1) begin : gen_depth_eq1 108 assign storage_rdata = storage[0]; 109 110 always_ff @(posedge clk_i) 111 if (fifo_incr_wptr) begin 112 storage[0] <= wdata_i; 113 end 114 115 logic unused_ptrs; 116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr}; 117 118 // fifo with more than one storage element 119 end else begin : gen_depth_gt1 120 1/1 assign storage_rdata = storage[fifo_rptr]; Tests: T1 T2 T3  121 122 always_ff @(posedge clk_i) 123 1/1 if (fifo_incr_wptr) begin Tests: T1 T2 T3  124 1/1 storage[fifo_wptr] <= wdata_i; Tests: T1 T2 T3  125 end MISSING_ELSE 126 end 127 128 logic [Width-1:0] rdata_int; 129 if (Pass == 1'b1) begin : gen_pass 130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata; 131 assign empty = fifo_empty & ~wvalid_i; 132 end else begin : gen_nopass 133 1/1 assign rdata_int = storage_rdata; Tests: T1 T2 T3  134 1/1 assign empty = fifo_empty; Tests: T1 T2 T3  135 end 136 137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero 138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int; Tests: T1 T2 T3 

Line Coverage for Module : prim_fifo_sync ( parameter Width=64,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
92.19 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage

SCORELINE
92.19 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage

Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00

68 always_ff @(posedge clk_i or negedge rst_ni) begin 69 1/1 if (!rst_ni) begin Tests: T1 T2 T3  70 1/1 under_rst <= 1'b1; Tests: T1 T2 T3  71 1/1 end else if (under_rst) begin Tests: T1 T2 T3  72 1/1 under_rst <= ~under_rst; Tests: T1 T2 T3  73 end MISSING_ELSE 74 end 75 76 logic empty; 77 78 // full and not ready for write are two different concepts. 79 // The latter can be '0' when under reset, while the former is an indication that no more 80 // entries can be written. 81 1/1 assign wready_o = ~full_o & ~under_rst; Tests: T1 T2 T3  82 1/1 assign rvalid_o = ~empty & ~under_rst; Tests: T1 T2 T3  83 84 prim_fifo_sync_cnt #( 85 .Depth(Depth), 86 .Secure(Secure) 87 ) u_fifo_cnt ( 88 .clk_i, 89 .rst_ni, 90 .clr_i, 91 .incr_wptr_i(fifo_incr_wptr), 92 .incr_rptr_i(fifo_incr_rptr), 93 .wptr_o(fifo_wptr), 94 .rptr_o(fifo_rptr), 95 .full_o, 96 .empty_o(fifo_empty), 97 .depth_o, 98 .err_o 99 ); 100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst; Tests: T1 T2 T3  101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst; Tests: T1 T2 T3  102 103 // the generate blocks below are needed to avoid lint errors due to array indexing 104 // in the where the fifo only has one storage element 105 logic [Depth-1:0][Width-1:0] storage; 106 logic [Width-1:0] storage_rdata; 107 if (Depth == 1) begin : gen_depth_eq1 108 assign storage_rdata = storage[0]; 109 110 always_ff @(posedge clk_i) 111 if (fifo_incr_wptr) begin 112 storage[0] <= wdata_i; 113 end 114 115 logic unused_ptrs; 116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr}; 117 118 // fifo with more than one storage element 119 end else begin : gen_depth_gt1 120 1/1 assign storage_rdata = storage[fifo_rptr]; Tests: T1 T2 T3  121 122 always_ff @(posedge clk_i) 123 1/1 if (fifo_incr_wptr) begin Tests: T1 T2 T3  124 1/1 storage[fifo_wptr] <= wdata_i; Tests: T1 T2 T3  125 end MISSING_ELSE 126 end 127 128 logic [Width-1:0] rdata_int; 129 if (Pass == 1'b1) begin : gen_pass 130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata; 131 assign empty = fifo_empty & ~wvalid_i; 132 end else begin : gen_nopass 133 1/1 assign rdata_int = storage_rdata; Tests: T1 T2 T3  134 1/1 assign empty = fifo_empty; Tests: T1 T2 T3  135 end 136 137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero 138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int; Tests: T1 T2 T3 

Line Coverage for Module : prim_fifo_sync ( parameter Width=16,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
92.19 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_addr_xor_storage

SCORELINE
92.19 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_addr_xor_storage

Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00

68 always_ff @(posedge clk_i or negedge rst_ni) begin 69 1/1 if (!rst_ni) begin Tests: T1 T2 T3  70 1/1 under_rst <= 1'b1; Tests: T1 T2 T3  71 1/1 end else if (under_rst) begin Tests: T1 T2 T3  72 1/1 under_rst <= ~under_rst; Tests: T1 T2 T3  73 end MISSING_ELSE 74 end 75 76 logic empty; 77 78 // full and not ready for write are two different concepts. 79 // The latter can be '0' when under reset, while the former is an indication that no more 80 // entries can be written. 81 1/1 assign wready_o = ~full_o & ~under_rst; Tests: T1 T2 T3  82 1/1 assign rvalid_o = ~empty & ~under_rst; Tests: T1 T2 T3  83 84 prim_fifo_sync_cnt #( 85 .Depth(Depth), 86 .Secure(Secure) 87 ) u_fifo_cnt ( 88 .clk_i, 89 .rst_ni, 90 .clr_i, 91 .incr_wptr_i(fifo_incr_wptr), 92 .incr_rptr_i(fifo_incr_rptr), 93 .wptr_o(fifo_wptr), 94 .rptr_o(fifo_rptr), 95 .full_o, 96 .empty_o(fifo_empty), 97 .depth_o, 98 .err_o 99 ); 100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst; Tests: T1 T2 T3  101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst; Tests: T1 T2 T3  102 103 // the generate blocks below are needed to avoid lint errors due to array indexing 104 // in the where the fifo only has one storage element 105 logic [Depth-1:0][Width-1:0] storage; 106 logic [Width-1:0] storage_rdata; 107 if (Depth == 1) begin : gen_depth_eq1 108 assign storage_rdata = storage[0]; 109 110 always_ff @(posedge clk_i) 111 if (fifo_incr_wptr) begin 112 storage[0] <= wdata_i; 113 end 114 115 logic unused_ptrs; 116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr}; 117 118 // fifo with more than one storage element 119 end else begin : gen_depth_gt1 120 1/1 assign storage_rdata = storage[fifo_rptr]; Tests: T1 T2 T3  121 122 always_ff @(posedge clk_i) 123 1/1 if (fifo_incr_wptr) begin Tests: T1 T2 T3  124 1/1 storage[fifo_wptr] <= wdata_i; Tests: T1 T2 T3  125 end MISSING_ELSE 126 end 127 128 logic [Width-1:0] rdata_int; 129 if (Pass == 1'b1) begin : gen_pass 130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata; 131 assign empty = fifo_empty & ~wvalid_i; 132 end else begin : gen_nopass 133 1/1 assign rdata_int = storage_rdata; Tests: T1 T2 T3  134 1/1 assign empty = fifo_empty; Tests: T1 T2 T3  135 end 136 137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero 138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int; Tests: T1 T2 T3 

Line Coverage for Module : prim_fifo_sync ( parameter Width=101,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
93.75 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

SCORELINE
93.75 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00

68 always_ff @(posedge clk_i or negedge rst_ni) begin 69 1/1 if (!rst_ni) begin Tests: T1 T2 T3  70 1/1 under_rst <= 1'b1; Tests: T1 T2 T3  71 1/1 end else if (under_rst) begin Tests: T1 T2 T3  72 1/1 under_rst <= ~under_rst; Tests: T1 T2 T3  73 end MISSING_ELSE 74 end 75 76 logic empty; 77 78 // full and not ready for write are two different concepts. 79 // The latter can be '0' when under reset, while the former is an indication that no more 80 // entries can be written. 81 1/1 assign wready_o = ~full_o & ~under_rst; Tests: T1 T2 T3  82 1/1 assign rvalid_o = ~empty & ~under_rst; Tests: T1 T2 T3  83 84 prim_fifo_sync_cnt #( 85 .Depth(Depth), 86 .Secure(Secure) 87 ) u_fifo_cnt ( 88 .clk_i, 89 .rst_ni, 90 .clr_i, 91 .incr_wptr_i(fifo_incr_wptr), 92 .incr_rptr_i(fifo_incr_rptr), 93 .wptr_o(fifo_wptr), 94 .rptr_o(fifo_rptr), 95 .full_o, 96 .empty_o(fifo_empty), 97 .depth_o, 98 .err_o 99 ); 100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst; Tests: T1 T2 T3  101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst; Tests: T1 T2 T3  102 103 // the generate blocks below are needed to avoid lint errors due to array indexing 104 // in the where the fifo only has one storage element 105 logic [Depth-1:0][Width-1:0] storage; 106 logic [Width-1:0] storage_rdata; 107 if (Depth == 1) begin : gen_depth_eq1 108 assign storage_rdata = storage[0]; 109 110 always_ff @(posedge clk_i) 111 if (fifo_incr_wptr) begin 112 storage[0] <= wdata_i; 113 end 114 115 logic unused_ptrs; 116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr}; 117 118 // fifo with more than one storage element 119 end else begin : gen_depth_gt1 120 1/1 assign storage_rdata = storage[fifo_rptr]; Tests: T1 T2 T3  121 122 always_ff @(posedge clk_i) 123 1/1 if (fifo_incr_wptr) begin Tests: T1 T2 T3  124 1/1 storage[fifo_wptr] <= wdata_i; Tests: T1 T2 T3  125 end MISSING_ELSE 126 end 127 128 logic [Width-1:0] rdata_int; 129 if (Pass == 1'b1) begin : gen_pass 130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata; 131 assign empty = fifo_empty & ~wvalid_i; 132 end else begin : gen_nopass 133 1/1 assign rdata_int = storage_rdata; Tests: T1 T2 T3  134 1/1 assign empty = fifo_empty; Tests: T1 T2 T3  135 end 136 137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero 138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int; Tests: T1 T2 T3 

Cond Coverage for Module : prim_fifo_sync ( parameter Width=6,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
92.19 68.75
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo

SCORECOND
92.19 68.75
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo

TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T16,T17
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (6'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=101,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
93.75 75.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

SCORECOND
93.75 75.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

TotalCoveredPercent
Conditions161275.00
Logical161275.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T7,T14
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T7,T14
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T7,T14
110Not Covered
111CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (101'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=64,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
92.19 68.75
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage

SCORECOND
92.19 68.75
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage

TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT2,T3,T7
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (64'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=1,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
67.47 38.46
tb.dut.u_to_prog_fifo.u_sramreqfifo

SCORECOND
92.19 68.75
tb.dut.u_tl_adapter_eflash.u_sramreqfifo

SCORECOND
90.62 62.50
tb.dut.u_to_rd_fifo.u_sramreqfifo

TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T3,T7
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T3,T7

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT2,T3,T7

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T13,T16
110Not Covered
111CoveredT2,T3,T7

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT2,T3,T7
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=16,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
92.19 68.75
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_addr_xor_storage

SCORECOND
92.19 68.75
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_addr_xor_storage

TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T16,T17
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (16'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=1,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
92.19 68.75
tb.dut.u_eflash.u_bank_sequence_fifo

TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T16,T17
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T13,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT2,T13,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T13,T16
110Not Covered
111CoveredT2,T13,T16

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (1'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT2,T13,T16
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=39,Pass=1,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=39,Pass=1,Depth=16,OutputZeroIfEmpty=1,Secure=0,DepthW=5,gen_normal_fifo.PtrW=4 )
Cond Coverage for Module self-instances :
SCORECOND
95.83 83.33
tb.dut.u_prog_fifo

SCORECOND
94.79 79.17
tb.dut.u_sw_rd_fifo

TotalCoveredPercent
Conditions242083.33
Logical242083.33
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T7,T14
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT7,T9,T10
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (39'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=76,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
92.19 68.75
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

SCORECOND
92.19 68.75
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage

TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT18
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (76'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=40,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 + Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=1,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
71.27 47.06
tb.dut.u_to_prog_fifo.u_rspfifo

SCORECOND
94.79 79.17
tb.dut.u_tl_adapter_eflash.u_rspfifo

SCORECOND
95.83 83.33
tb.dut.u_to_rd_fifo.u_rspfifo

SCORECOND
95.83 83.33
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

SCORECOND
93.75 75.00
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo

TotalCoveredPercent
Conditions242083.33
Logical242083.33
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT23,T17,T66
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T3,T7

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT66,T68,T18
110Not Covered
111CoveredT2,T3,T7

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT13,T14,T15
110Not Covered
111CoveredT2,T3,T7

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T7

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT66,T68,T69
10CoveredT1,T2,T3
11CoveredT2,T3,T7

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT13,T23,T17
10CoveredT2,T3,T7
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT2,T3,T7
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=17,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=1,DepthW=1,gen_normal_fifo.PtrW=1 + Width=17,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
92.19 68.75
tb.dut.u_to_prog_fifo.u_reqfifo

SCORECOND
92.19 68.75
tb.dut.u_tl_adapter_eflash.u_reqfifo

SCORECOND
92.19 68.75
tb.dut.u_to_rd_fifo.u_reqfifo

SCORECOND
92.19 68.75
tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo

TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T13,T14
110Not Covered
111CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=39,Pass=1,Depth=4,OutputZeroIfEmpty=1,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=39,Pass=1,Depth=16,OutputZeroIfEmpty=1,Secure=0,DepthW=5,gen_normal_fifo.PtrW=4 + Width=40,Pass=1,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 + Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=1,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
71.27 85.71
tb.dut.u_to_prog_fifo.u_rspfifo

SCOREBRANCH
95.83 100.00
tb.dut.u_prog_fifo

SCOREBRANCH
94.79 100.00
tb.dut.u_sw_rd_fifo

SCOREBRANCH
94.79 100.00
tb.dut.u_tl_adapter_eflash.u_rspfifo

SCOREBRANCH
95.83 100.00
tb.dut.u_to_rd_fifo.u_rspfifo

SCOREBRANCH
95.83 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

SCOREBRANCH
93.75 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo

Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00


130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


138 assign rdata_o = empty ? Width'(0) : rdata_int; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


69 if (!rst_ni) begin -1- 70 under_rst <= 1'b1; ==> 71 end else if (under_rst) begin -2- 72 under_rst <= ~under_rst; ==> 73 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


111 if (fifo_incr_wptr) begin -1- 112 storage[0] <= wdata_i; ==> 113 end MISSING_ELSE ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Branch Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=17,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 + Width=1,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 + Width=6,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 + Width=76,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=1,DepthW=2,gen_normal_fifo.PtrW=1 + Width=64,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 + Width=16,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 + Width=101,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=1,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=1,DepthW=1,gen_normal_fifo.PtrW=1 + Width=17,Pass=0,Depth=2,OutputZeroIfEmpty=1,Secure=0,DepthW=2,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
92.19 100.00
tb.dut.u_to_prog_fifo.u_reqfifo

SCOREBRANCH
67.47 85.71
tb.dut.u_to_prog_fifo.u_sramreqfifo

SCOREBRANCH
92.19 100.00
tb.dut.u_tl_adapter_eflash.u_reqfifo

SCOREBRANCH
92.19 100.00
tb.dut.u_tl_adapter_eflash.u_sramreqfifo

SCOREBRANCH
92.19 100.00
tb.dut.u_eflash.u_bank_sequence_fifo

SCOREBRANCH
92.19 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo

SCOREBRANCH
92.19 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo

SCOREBRANCH
92.19 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

SCOREBRANCH
92.19 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage

SCOREBRANCH
92.19 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage

SCOREBRANCH
92.19 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage

SCOREBRANCH
92.19 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_addr_xor_storage

SCOREBRANCH
92.19 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_addr_xor_storage

SCOREBRANCH
93.75 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

SCOREBRANCH
93.75 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

SCOREBRANCH
92.19 100.00
tb.dut.u_to_rd_fifo.u_reqfifo

SCOREBRANCH
90.62 100.00
tb.dut.u_to_rd_fifo.u_sramreqfifo

SCOREBRANCH
92.19 100.00
tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo

Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00


138 assign rdata_o = empty ? Width'(0) : rdata_int; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


69 if (!rst_ni) begin -1- 70 under_rst <= 1'b1; ==> 71 end else if (under_rst) begin -2- 72 under_rst <= ~under_rst; ==> 73 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


111 if (fifo_incr_wptr) begin -1- 112 storage[0] <= wdata_i; ==> 113 end MISSING_ELSE ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_fifo_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2147483647 942582209 0 0
DepthKnown_A 2147483647 2147483647 0 0
RvalidKnown_A 2147483647 2147483647 0 0
WreadyKnown_A 2147483647 2147483647 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 2147483647 788571237 0 0
gen_passthru_fifo.paramCheckPass 10040 10040 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 942582209 0 0
T1 50362 384 0 0
T2 320250 2790 0 0
T3 76590 895 0 0
T7 67950 454 0 0
T13 39750 429 0 0
T14 1712285 3164 0 0
T15 2993267 6004 0 0
T16 3578 163 0 0
T17 76086 2139 0 0
T20 45663 900 0 0
T21 59582 895 0 0
T22 5549062 384 0 0
T23 1717506 34 0 0
T26 0 154 0 0
T27 0 144 0 0
T43 56502 59200 0 0
T61 0 18148 0 0
T64 5152 91 0 0
T65 0 39730 0 0
T66 0 190 0 0
T67 0 16 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 127842 125301 0 0
T2 352275 349404 0 0
T3 84249 81114 0 0
T7 74745 71709 0 0
T13 43725 40656 0 0
T14 1822755 1819818 0 0
T15 3186381 3183312 0 0
T20 48609 46530 0 0
T21 63426 61380 0 0
T22 5907066 5904954 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 127842 125301 0 0
T2 352275 349404 0 0
T3 84249 81114 0 0
T7 74745 71709 0 0
T13 43725 40656 0 0
T14 1822755 1819818 0 0
T15 3186381 3183312 0 0
T20 48609 46530 0 0
T21 63426 61380 0 0
T22 5907066 5904954 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 127842 125301 0 0
T2 352275 349404 0 0
T3 84249 81114 0 0
T7 74745 71709 0 0
T13 43725 40656 0 0
T14 1822755 1819818 0 0
T15 3186381 3183312 0 0
T20 48609 46530 0 0
T21 63426 61380 0 0
T22 5907066 5904954 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 788571237 0 0
T1 27118 384 0 0
T2 234850 2790 0 0
T3 56166 895 0 0
T7 49830 454 0 0
T13 29150 429 0 0
T14 1270405 3164 0 0
T15 2220811 6004 0 0
T16 3578 163 0 0
T17 76086 2139 0 0
T20 33879 900 0 0
T21 44206 895 0 0
T22 4117046 384 0 0
T23 1526672 34 0 0
T26 0 154 0 0
T27 0 144 0 0
T43 56502 59200 0 0
T61 0 18148 0 0
T64 5152 91 0 0
T65 0 39730 0 0
T66 0 190 0 0
T67 0 16 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 10040 10040 0 0
T1 8 8 0 0
T2 8 8 0 0
T3 8 8 0 0
T7 8 8 0 0
T13 8 8 0 0
T14 8 8 0 0
T15 8 8 0 0
T20 8 8 0 0
T21 8 8 0 0
T22 8 8 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%