Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	367710	1		T1	1		T2	2		T3	2
all_values[1]	367710	1		T1	1		T2	2		T3	2
all_values[2]	367710	1		T1	1		T2	2		T3	2
all_values[3]	367710	1		T1	1		T2	2		T3	2
all_values[4]	367710	1		T1	1		T2	2		T3	2
all_values[5]	367710	1		T1	1		T2	2		T3	2

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	741740	1		T1	6		T2	12		T3	12
auto[1]	1464520	1		T37	5600		T40	6456		T43	13392

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1077177	1		T1	4		T2	7		T3	7
auto[1]	1129083	1		T1	2		T2	5		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	367569	1		T1	1		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	141	1		T267	5		T276	3		T327	1
all_values[1]	auto[0]	auto[1]	367566	1		T1	1		T2	2		T3	2
all_values[1]	auto[1]	auto[1]	144	1		T267	5		T276	4		T328	2
all_values[2]	auto[0]	auto[0]	1596	1		T1	1		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	57	1		T267	2		T276	2		T327	1
all_values[2]	auto[1]	auto[0]	366012	1		T37	1400		T40	1614		T43	3348
all_values[2]	auto[1]	auto[1]	45	1		T327	1		T328	2		T347	1
all_values[3]	auto[0]	auto[0]	1593	1		T1	1		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	51	1		T276	1		T327	1		T328	1
all_values[3]	auto[1]	auto[0]	87089	1		T37	1400		T40	1614		T43	1674
all_values[3]	auto[1]	auto[1]	278977	1		T43	1674		T49	1523		T50	1651
all_values[4]	auto[0]	auto[0]	1123	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	533	1		T2	1		T3	1		T5	1
all_values[4]	auto[1]	auto[0]	252220	1		T37	1		T40	1		T43	1674
all_values[4]	auto[1]	auto[1]	113834	1		T37	1399		T40	1613		T43	1674
all_values[5]	auto[0]	auto[0]	1545	1		T1	1		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	107	1		T36	1		T51	1		T52	1
all_values[5]	auto[1]	auto[0]	365999	1		T37	1400		T40	1614		T43	3348
all_values[5]	auto[1]	auto[1]	59	1		T267	2		T327	1		T330	2