Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.87 95.23 93.61 98.31 91.84 97.12 96.89 98.09


Total tests in report: 1241
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
59.13 59.13 85.17 85.17 58.75 58.75 53.29 53.29 42.18 42.18 80.80 80.80 74.17 74.17 19.54 19.54 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wr_intg.3884294694
67.86 8.73 89.12 3.95 70.01 11.25 69.00 15.71 52.38 10.20 86.11 5.31 82.04 7.86 26.39 6.84 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_re_evict.1442771273
73.40 5.53 92.21 3.09 75.45 5.45 71.25 2.25 52.38 0.00 91.91 5.80 90.97 8.93 39.61 13.22 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.799814280
77.44 4.04 92.77 0.56 76.67 1.22 73.14 1.90 64.63 12.24 92.92 1.00 91.46 0.49 50.46 10.85 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mid_op_rst.3281041315
79.79 2.35 92.89 0.12 80.17 3.49 83.26 10.12 64.63 0.00 93.00 0.09 91.46 0.00 53.11 2.65 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_intg.858891356
82.12 2.33 93.51 0.62 80.58 0.42 87.39 4.13 74.83 10.20 93.71 0.70 91.55 0.10 53.24 0.12 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma_reset.527626293
84.00 1.89 93.63 0.12 85.03 4.45 87.39 0.00 76.19 1.36 94.22 0.51 91.94 0.39 59.62 6.38 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_serr.3141901139
85.80 1.80 93.63 0.00 85.63 0.60 87.39 0.00 76.19 0.00 94.22 0.00 92.04 0.10 71.49 11.87 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.1609813857
87.41 1.61 93.70 0.07 85.74 0.10 87.39 0.00 76.19 0.00 94.28 0.06 92.23 0.19 82.34 10.85 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mp_regions.2605862468
88.94 1.53 93.88 0.18 86.55 0.82 91.41 4.02 77.55 1.36 95.03 0.75 95.53 3.30 82.61 0.28 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_cm.4003699136
89.74 0.80 94.00 0.12 87.83 1.28 93.59 2.18 77.55 0.00 95.03 0.00 95.53 0.00 84.65 2.03 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_sec_otp.4287041554
90.41 0.67 94.06 0.06 88.25 0.42 94.91 1.32 79.59 2.04 95.33 0.30 95.63 0.10 85.11 0.46 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_write_word_sweep.166660258
90.93 0.52 94.15 0.09 88.28 0.03 94.96 0.05 82.99 3.40 95.41 0.09 95.63 0.00 85.11 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mid_op_rst.1139555542
91.29 0.36 94.19 0.04 88.72 0.44 95.42 0.47 82.99 0.00 95.63 0.21 95.63 0.00 86.47 1.36 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fetch_code.394787123
91.61 0.32 94.25 0.06 89.11 0.39 95.49 0.06 82.99 0.00 95.71 0.09 95.73 0.10 88.01 1.54 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_oversize_error.772537802
91.93 0.32 94.28 0.03 89.16 0.06 95.49 0.00 85.03 2.04 95.82 0.11 95.73 0.00 88.01 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_otp_reset.668750239
92.22 0.29 94.28 0.00 89.60 0.44 95.49 0.00 85.03 0.00 95.82 0.00 95.92 0.19 89.40 1.39 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.31623654
92.44 0.22 94.39 0.12 89.61 0.01 95.49 0.00 85.03 0.00 95.82 0.00 95.92 0.00 90.84 1.45 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_intr_test.147893356
92.66 0.22 94.54 0.14 89.71 0.10 95.90 0.42 85.71 0.68 95.99 0.17 95.92 0.00 90.84 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rma_err.427277281
92.86 0.20 94.54 0.01 89.78 0.08 95.94 0.03 85.71 0.00 96.01 0.02 95.92 0.00 92.14 1.29 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.100664118
93.06 0.20 94.54 0.00 89.79 0.01 95.94 0.00 87.07 1.36 96.01 0.00 95.92 0.00 92.17 0.03 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mid_op_rst.24306816
93.26 0.20 94.60 0.05 90.21 0.42 95.94 0.00 87.76 0.68 96.05 0.04 96.12 0.19 92.17 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_erase_suspend.1294731614
93.46 0.19 94.60 0.00 90.21 0.00 95.94 0.00 89.12 1.36 96.05 0.00 96.12 0.00 92.17 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_otp_reset.3125865748
93.64 0.18 94.67 0.07 90.46 0.25 96.03 0.10 89.12 0.00 96.20 0.15 96.12 0.00 92.88 0.71 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd.3471482203
93.81 0.17 94.68 0.01 90.52 0.06 96.39 0.35 89.80 0.68 96.24 0.04 96.12 0.00 92.91 0.03 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_lcmgr_intg.4171656833
93.97 0.16 94.70 0.02 90.54 0.03 96.64 0.26 90.48 0.68 96.31 0.06 96.12 0.00 92.97 0.06 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.118606397
94.12 0.16 94.75 0.05 90.67 0.12 97.00 0.35 90.48 0.00 96.44 0.13 96.12 0.00 93.40 0.43 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_info_access.238371769
94.25 0.13 94.85 0.10 90.77 0.10 97.45 0.45 90.48 0.00 96.44 0.00 96.12 0.00 93.65 0.25 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_alert_test.185081703
94.38 0.13 94.92 0.07 91.02 0.25 97.45 0.00 90.48 0.00 96.52 0.09 96.12 0.00 94.14 0.49 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fs_sup.2970776036
94.50 0.12 94.92 0.00 91.02 0.00 97.64 0.19 91.16 0.68 96.52 0.00 96.12 0.00 94.14 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_otp_reset.2978784553
94.61 0.11 94.93 0.01 91.04 0.02 97.64 0.00 91.84 0.68 96.56 0.04 96.12 0.00 94.14 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_otp_reset.2680077756
94.71 0.10 94.94 0.01 91.45 0.41 97.64 0.00 91.84 0.00 96.61 0.04 96.21 0.10 94.27 0.12 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_derr.1481698931
94.80 0.09 94.97 0.04 91.95 0.50 97.67 0.03 91.84 0.00 96.61 0.00 96.21 0.00 94.36 0.09 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3509665772
94.88 0.08 95.03 0.06 92.02 0.07 97.67 0.00 91.84 0.00 96.65 0.04 96.50 0.29 94.45 0.09 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mp_regions.1676669530
94.94 0.06 95.03 0.00 92.12 0.10 97.67 0.00 91.84 0.00 96.67 0.02 96.50 0.00 94.73 0.28 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_re_evict.187053727
94.99 0.06 95.03 0.00 92.12 0.00 97.67 0.00 91.84 0.00 96.67 0.00 96.89 0.39 94.73 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2574851258
95.04 0.05 95.03 0.00 92.15 0.04 97.67 0.00 91.84 0.00 96.71 0.04 96.89 0.00 95.01 0.28 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd_slow_flash.1276127544
95.09 0.05 95.03 0.00 92.44 0.29 97.67 0.00 91.84 0.00 96.71 0.00 96.89 0.00 95.04 0.03 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_errors.418418953
95.13 0.04 95.03 0.00 92.44 0.00 97.67 0.00 91.84 0.00 96.71 0.00 96.89 0.00 95.35 0.31 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_intr_test.3240267594
95.17 0.04 95.03 0.00 92.51 0.07 97.70 0.03 91.84 0.00 96.74 0.02 96.89 0.00 95.50 0.15 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_invalid_op.4160188913
95.21 0.04 95.03 0.00 92.52 0.01 97.70 0.00 91.84 0.00 96.74 0.00 96.89 0.00 95.75 0.25 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1569520788
95.25 0.04 95.03 0.00 92.53 0.01 97.70 0.00 91.84 0.00 96.74 0.00 96.89 0.00 95.99 0.25 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd.2348360070
95.28 0.03 95.09 0.05 92.54 0.02 97.77 0.06 91.84 0.00 96.78 0.04 96.89 0.00 96.02 0.03 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_disable.3337833790
95.30 0.03 95.10 0.01 92.59 0.05 97.82 0.05 91.84 0.00 96.80 0.02 96.89 0.00 96.09 0.06 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_host_grant_err.1269053554
95.33 0.03 95.11 0.01 92.69 0.10 97.82 0.00 91.84 0.00 96.84 0.04 96.89 0.00 96.12 0.03 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb_redun.2334670902
95.35 0.02 95.12 0.02 92.70 0.01 97.82 0.00 91.84 0.00 96.86 0.02 96.89 0.00 96.24 0.12 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wo.1767037978
95.38 0.02 95.12 0.00 92.70 0.00 97.98 0.16 91.84 0.00 96.86 0.00 96.89 0.00 96.24 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma.705546507
95.40 0.02 95.12 0.00 92.76 0.07 97.98 0.00 91.84 0.00 96.86 0.00 96.89 0.00 96.33 0.09 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_rw.3329870495
95.42 0.02 95.12 0.00 92.77 0.01 97.98 0.00 91.84 0.00 96.86 0.00 96.89 0.00 96.45 0.12 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.3073051813
95.43 0.02 95.12 0.00 92.80 0.03 97.98 0.00 91.84 0.00 96.86 0.00 96.89 0.00 96.55 0.09 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict.3439995114
95.45 0.02 95.13 0.01 92.84 0.04 97.98 0.00 91.84 0.00 96.91 0.04 96.89 0.00 96.58 0.03 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.2496727280
95.47 0.02 95.14 0.01 92.88 0.04 97.98 0.00 91.84 0.00 96.95 0.04 96.89 0.00 96.61 0.03 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_ack_consistency.3528925482
95.49 0.02 95.16 0.02 92.93 0.06 97.98 0.00 91.84 0.00 96.99 0.04 96.89 0.00 96.61 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_access_after_disable.20673128
95.50 0.02 95.16 0.00 93.05 0.11 97.98 0.00 91.84 0.00 96.99 0.00 96.89 0.00 96.61 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_errors.1180444514
95.52 0.01 95.16 0.00 93.06 0.01 97.98 0.00 91.84 0.00 96.99 0.00 96.89 0.00 96.70 0.09 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_derr_detect.2185414316
95.53 0.01 95.16 0.00 93.06 0.00 98.07 0.10 91.84 0.00 96.99 0.00 96.89 0.00 96.70 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_lcmgr_intg.3451713567
95.54 0.01 95.16 0.00 93.06 0.00 98.07 0.00 91.84 0.00 96.99 0.00 96.89 0.00 96.79 0.09 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_invalid_op.2114751538
95.56 0.01 95.17 0.01 93.07 0.01 98.07 0.00 91.84 0.00 97.03 0.04 96.89 0.00 96.82 0.03 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_read_seed_err.57645427
95.57 0.01 95.18 0.01 93.08 0.01 98.07 0.00 91.84 0.00 97.08 0.04 96.89 0.00 96.86 0.03 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.568753409
95.58 0.01 95.22 0.04 93.08 0.00 98.09 0.02 91.84 0.00 97.08 0.00 96.89 0.00 96.89 0.03 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_connect.2566882953
95.59 0.01 95.22 0.00 93.11 0.03 98.09 0.00 91.84 0.00 97.10 0.02 96.89 0.00 96.92 0.03 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_rma_reset.1751030196
95.61 0.01 95.22 0.00 93.13 0.02 98.09 0.00 91.84 0.00 97.10 0.00 96.89 0.00 96.98 0.06 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_derr.4024560929
95.62 0.01 95.22 0.00 93.17 0.05 98.09 0.00 91.84 0.00 97.10 0.00 96.89 0.00 97.01 0.03 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_type.3183011905
95.63 0.01 95.22 0.00 93.18 0.01 98.15 0.06 91.84 0.00 97.10 0.00 96.89 0.00 97.01 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_win.1776195075
95.64 0.01 95.22 0.00 93.19 0.01 98.19 0.03 91.84 0.00 97.10 0.00 96.89 0.00 97.04 0.03 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict.3042184880
95.65 0.01 95.22 0.00 93.20 0.01 98.19 0.00 91.84 0.00 97.10 0.00 96.89 0.00 97.10 0.06 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_ooo.1316985305
95.66 0.01 95.22 0.00 93.21 0.01 98.19 0.00 91.84 0.00 97.10 0.00 96.89 0.00 97.16 0.06 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd.436701912
95.67 0.01 95.22 0.00 93.21 0.00 98.19 0.00 91.84 0.00 97.10 0.00 96.89 0.00 97.23 0.06 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2945092478
95.68 0.01 95.22 0.00 93.21 0.00 98.19 0.00 91.84 0.00 97.10 0.00 96.89 0.00 97.29 0.06 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_read_seed_err.1865098663
95.68 0.01 95.22 0.00 93.21 0.00 98.19 0.00 91.84 0.00 97.10 0.00 96.89 0.00 97.35 0.06 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_info_access.1603660062
95.69 0.01 95.22 0.00 93.21 0.00 98.19 0.00 91.84 0.00 97.10 0.00 96.89 0.00 97.41 0.06 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_rw_evict.104074370
95.70 0.01 95.22 0.00 93.21 0.00 98.19 0.00 91.84 0.00 97.10 0.00 96.89 0.00 97.47 0.06 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_info_access.342209289
95.71 0.01 95.22 0.00 93.21 0.00 98.19 0.00 91.84 0.00 97.10 0.00 96.89 0.00 97.53 0.06 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_otp_reset.2216652857
95.72 0.01 95.22 0.00 93.21 0.00 98.19 0.00 91.84 0.00 97.10 0.00 96.89 0.00 97.60 0.06 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_sec_info_access.3034010437
95.73 0.01 95.22 0.00 93.24 0.03 98.22 0.03 91.84 0.00 97.10 0.00 96.89 0.00 97.60 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_sec_otp.2755853567
95.74 0.01 95.22 0.00 93.27 0.03 98.22 0.00 91.84 0.00 97.10 0.00 96.89 0.00 97.63 0.03 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_errors.809277881
95.74 0.01 95.22 0.00 93.29 0.02 98.22 0.00 91.84 0.00 97.10 0.00 96.89 0.00 97.66 0.03 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1464782000
95.75 0.01 95.22 0.00 93.31 0.02 98.22 0.00 91.84 0.00 97.10 0.00 96.89 0.00 97.69 0.03 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw.1366377559
95.76 0.01 95.22 0.00 93.35 0.05 98.22 0.00 91.84 0.00 97.10 0.00 96.89 0.00 97.69 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb_redun.1667592482
95.76 0.01 95.22 0.00 93.36 0.01 98.25 0.03 91.84 0.00 97.10 0.00 96.89 0.00 97.69 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_cm.2283509518
95.77 0.01 95.22 0.00 93.37 0.01 98.25 0.00 91.84 0.00 97.10 0.00 96.89 0.00 97.72 0.03 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_re_evict.1422930824
95.78 0.01 95.22 0.00 93.38 0.01 98.25 0.00 91.84 0.00 97.10 0.00 96.89 0.00 97.75 0.03 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_rw_evict_all_en.1503431272
95.78 0.01 95.22 0.00 93.42 0.04 98.25 0.00 91.84 0.00 97.10 0.00 96.89 0.00 97.75 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_errors.1828011667
95.79 0.01 95.22 0.00 93.42 0.00 98.28 0.03 91.84 0.00 97.10 0.00 96.89 0.00 97.75 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fetch_code.2180436737
95.79 0.01 95.22 0.00 93.42 0.00 98.31 0.03 91.84 0.00 97.10 0.00 96.89 0.00 97.75 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_lcmgr_intg.2135598413
95.79 0.01 95.22 0.00 93.42 0.00 98.31 0.00 91.84 0.00 97.10 0.00 96.89 0.00 97.78 0.03 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_intr_test.1175708466
95.80 0.01 95.22 0.00 93.42 0.00 98.31 0.00 91.84 0.00 97.10 0.00 96.89 0.00 97.81 0.03 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_config_regwen.700011983
95.80 0.01 95.22 0.00 93.42 0.00 98.31 0.00 91.84 0.00 97.10 0.00 96.89 0.00 97.84 0.03 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_disable.49835935
95.81 0.01 95.22 0.00 93.42 0.00 98.31 0.00 91.84 0.00 97.10 0.00 96.89 0.00 97.87 0.03 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_disable.597350512
95.81 0.01 95.22 0.00 93.42 0.00 98.31 0.00 91.84 0.00 97.10 0.00 96.89 0.00 97.90 0.03 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_disable.2157627482
95.82 0.01 95.22 0.00 93.42 0.00 98.31 0.00 91.84 0.00 97.10 0.00 96.89 0.00 97.93 0.03 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_invalid_op.118319788
95.82 0.01 95.22 0.00 93.42 0.00 98.31 0.00 91.84 0.00 97.10 0.00 96.89 0.00 97.97 0.03 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_sec_info_access.657198698
95.83 0.01 95.22 0.00 93.42 0.00 98.31 0.00 91.84 0.00 97.10 0.00 96.89 0.00 98.00 0.03 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_disable.941221320
95.83 0.01 95.22 0.00 93.42 0.00 98.31 0.00 91.84 0.00 97.10 0.00 96.89 0.00 98.03 0.03 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_sec_info_access.2136888704
95.83 0.01 95.22 0.00 93.42 0.00 98.31 0.00 91.84 0.00 97.10 0.00 96.89 0.00 98.06 0.03 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_disable.110270218
95.84 0.01 95.22 0.00 93.42 0.00 98.31 0.00 91.84 0.00 97.10 0.00 96.89 0.00 98.09 0.03 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_disable.3314053243
95.84 0.01 95.23 0.01 93.42 0.00 98.31 0.00 91.84 0.00 97.12 0.02 96.89 0.00 98.09 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rand_ops.4089654395
95.85 0.01 95.23 0.00 93.45 0.03 98.31 0.00 91.84 0.00 97.12 0.00 96.89 0.00 98.09 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.1458513587
95.85 0.01 95.23 0.00 93.48 0.03 98.31 0.00 91.84 0.00 97.12 0.00 96.89 0.00 98.09 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr.377447780
95.85 0.01 95.23 0.00 93.50 0.02 98.31 0.00 91.84 0.00 97.12 0.00 96.89 0.00 98.09 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_dir_rd.484704833
95.86 0.01 95.23 0.00 93.52 0.02 98.31 0.00 91.84 0.00 97.12 0.00 96.89 0.00 98.09 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_intr_rd_slow_flash.3098723803
95.86 0.01 95.23 0.00 93.53 0.02 98.31 0.00 91.84 0.00 97.12 0.00 96.89 0.00 98.09 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_serr.2987094668
95.86 0.01 95.23 0.00 93.54 0.01 98.31 0.00 91.84 0.00 97.12 0.00 96.89 0.00 98.09 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_errors.4265286742
95.86 0.01 95.23 0.00 93.55 0.01 98.31 0.00 91.84 0.00 97.12 0.00 96.89 0.00 98.09 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.1130193720
95.86 0.01 95.23 0.00 93.56 0.01 98.31 0.00 91.84 0.00 97.12 0.00 96.89 0.00 98.09 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_ctrl_arb.2968973330
95.86 0.01 95.23 0.00 93.57 0.01 98.31 0.00 91.84 0.00 97.12 0.00 96.89 0.00 98.09 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wr_intg.506445347
95.87 0.01 95.23 0.00 93.58 0.01 98.31 0.00 91.84 0.00 97.12 0.00 96.89 0.00 98.09 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_otp_reset.149740073
95.87 0.01 95.23 0.00 93.59 0.01 98.31 0.00 91.84 0.00 97.12 0.00 96.89 0.00 98.09 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_ctrl_arb.877657880
95.87 0.01 95.23 0.00 93.60 0.01 98.31 0.00 91.84 0.00 97.12 0.00 96.89 0.00 98.09 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb_redun.1771425389
95.87 0.01 95.23 0.00 93.61 0.01 98.31 0.00 91.84 0.00 97.12 0.00 96.89 0.00 98.09 0.00 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_integrity.2900507742

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1391774433
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.318558851
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.858375048
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_walk.3117567642
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.2925482263
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.203574953
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2153540944
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_errors.2820861956
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.3574033345
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.4173650753
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.42868751
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.282851281
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1544094206
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_intr_test.3637775451
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_walk.3888907669
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.4062199495
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.3466076198
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.423553462
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.892658559
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.4076479260
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_rw.3564074797
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_intr_test.2814430424
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.297245434
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.4210191740
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2119174621
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_errors.124240971
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.544461434
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_rw.269427572
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3751879317
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.4259138906
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.3047163089
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.486765758
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.3263396291
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2205742409
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_intr_test.1824821472
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.4099615808
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.334374260
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.4260641860
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_errors.854682364
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3708544841
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3052876750
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_rw.3245412493
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_intr_test.3897483743
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.305682974
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.2030028508
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.2874718054
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_errors.4120440277
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3549474626
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1788801109
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3493341582
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_intr_test.2638317926
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2559485471
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2751133408
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.213147663
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_errors.165759983
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.3219006956
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.2424604070
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_rw.1428469456
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_intr_test.3620618807
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.3004018965
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.147458297
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.4112758404
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1975693152
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.2655276666
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_rw.131737235
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_intr_test.3090941737
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3472539186
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1269138111
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1174059899
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2622413871
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.3290355067
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.2213176359
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1596225329
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_intr_test.760919729
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.2103360876
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.827902925
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1163765510
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_errors.4222296261
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3979975729
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.2053555794
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_rw.1375437021
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_intr_test.3475916569
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.3766999692
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.668121333
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.2032923077
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_errors.627219443
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.926408509
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_rw.4007603101
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_intr_test.809219839
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.868526370
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.171428483
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.936053207
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3349342846
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.1556998690
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.2268033384
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.4172731672
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3013610009
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_intr_test.973675118
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.794594624
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_walk.1282944814
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.2363092481
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.1867860600
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2362503747
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3632362577
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/20.flash_ctrl_intr_test.1423472938
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/21.flash_ctrl_intr_test.1978991793
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/22.flash_ctrl_intr_test.2573204168
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/23.flash_ctrl_intr_test.3863548565
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/24.flash_ctrl_intr_test.693863623
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/25.flash_ctrl_intr_test.672643407
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/26.flash_ctrl_intr_test.906299843
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/27.flash_ctrl_intr_test.1448996297
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/28.flash_ctrl_intr_test.3342479999
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/29.flash_ctrl_intr_test.828999529
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2720130778
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.987472912
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.33041607
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2415753760
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.4039516051
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1210508013
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3835919810
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1671593572
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.2087415214
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_errors.4167784946
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.162383184
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/30.flash_ctrl_intr_test.1180164370
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/31.flash_ctrl_intr_test.672606429
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/32.flash_ctrl_intr_test.1025284415
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/33.flash_ctrl_intr_test.4259497707
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/34.flash_ctrl_intr_test.2930700874
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/35.flash_ctrl_intr_test.1855028305
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/36.flash_ctrl_intr_test.1120489614
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/37.flash_ctrl_intr_test.3472030826
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/38.flash_ctrl_intr_test.2788736139
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/39.flash_ctrl_intr_test.3722479767
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1317660144
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.1595123635
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.2737741055
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1160836958
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_rw.3013149326
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_intr_test.2622047893
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1260719883
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_walk.105213305
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.3818551555
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.209249194
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.2202554165
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2329050528
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/40.flash_ctrl_intr_test.319622051
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/41.flash_ctrl_intr_test.200706904
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/42.flash_ctrl_intr_test.970439500
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/43.flash_ctrl_intr_test.2213028749
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/44.flash_ctrl_intr_test.1006634678
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/45.flash_ctrl_intr_test.2909190214
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/46.flash_ctrl_intr_test.2337379688
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/47.flash_ctrl_intr_test.3277095403
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/48.flash_ctrl_intr_test.993396592
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/49.flash_ctrl_intr_test.2290917691
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.520232165
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3052163640
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_intr_test.8462968
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.2231838452
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3656804702
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.2606973132
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_errors.4038467250
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.3939173121
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_rw.297552530
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_intr_test.760190541
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2745577516
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.1244438889
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.3199564162
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.1051041650
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.4158246514
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_rw.20383481
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_intr_test.4049921427
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1259864702
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.1804766697
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.2819753067
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_errors.3798230954
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.1016507196
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2710929156
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3740448211
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_intr_test.199995611
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.1689440211
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.412288138
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.3891417472
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3753990533
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.4256648164
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_rw.3432924055
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_intr_test.2211545281
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.3973268113
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.4259233310
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2870733841
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_errors.2209940881
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.751363230
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_alert_test.1830319976
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_connect.1854592250
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_derr_detect.2952929732
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fs_sup.621966379
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_full_mem_access.4024161397
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_addr_infection.2977710672
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_dir_rd.1257981300
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.2006520322
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma.3479343204
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_integrity.3014694848
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd.615729349
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd_slow_flash.1194292762
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr_slow_flash.1663936336
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mp_regions.619025516
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_otp_reset.3685770717
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_ack_consistency.2626180497
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb.1559421834
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_prog_reset.1294242880
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_buff_evict.110286956
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep.1253829127
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_derr.4100512740
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_serr.286149889
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro.971390262
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw.1593780798
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_derr.264996211
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict_all_en.2473034930
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_serr.2560975570
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_info_access.2103244532
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_address.372243456
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_counter.791437765
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke.450947229
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke_hw.749560848
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_stress_all.2002468017
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sw_op.764903236
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_access_after_disable.384327180
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_config_regwen.3071043420
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_connect.197183925
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_derr_detect.4008526340
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_disable.4102111811
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_erase_suspend.4000535682
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_win.798357450
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_full_mem_access.1215941617
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_addr_infection.2416169223
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma_reset.1060673223
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_sec_otp.904589093
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_integrity.1873995419
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd.1363034161
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd_slow_flash.1976647916
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr.947928563
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr_slow_flash.891618496
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_invalid_op.3980108858
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_otp_reset.2939015424
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_oversize_error.3781462724
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_ack_consistency.684581849
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb.1139692082
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb_redun.4147596938
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_host_grant_err.2345146589
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_prog_reset.1458868049
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rand_ops.3466779796
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_buff_evict.3150981081
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_intg.1643280104
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_derr.904494531
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_serr.2121237422
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rma_err.2206037628
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro.656213017
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_derr.1396674162
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_serr.359794015
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw.343741210
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_derr.19345524
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict_all_en.1440426375
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_serr.3027654116
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_cm.3014469916
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_address.2000509475
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_counter.270709128
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke.4069877498
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke_hw.1173398732
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_stress_all.1913926914
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sw_op.2260141932
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wo.1109917721
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wr_intg.3555611029
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_alert_test.2593908709
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_connect.2762118532
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_disable.2639488359
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_read_seed_err.4217360834
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_sec_otp.308682156
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd_slow_flash.682061867
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_invalid_op.3444433238
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_lcmgr_intg.3158518101
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_mp_regions.1354834593
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_otp_reset.2623807698
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_phy_arb.1532953548
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_prog_reset.1015997205
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rand_ops.3016753339
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_re_evict.2278219712
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_ro.835491543
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw.3076652828
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict_all_en.1441525553
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_sec_info_access.4231106132
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_smoke.1635309130
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_wo.684427298
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_alert_test.2868545119
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_connect.897495639
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_disable.2615358878
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.937279550
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_read_seed_err.3418612476
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_rma_reset.1571544981
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_sec_otp.1905133621
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd_slow_flash.3666469984
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_lcmgr_intg.3480036041
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_mp_regions.500792810
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_otp_reset.3622950509
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_phy_arb.853686583
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_prog_reset.3569756403
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rand_ops.927834388
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_ro.94809873
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw.3907996133
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict.2682906116
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict_all_en.2818106246
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_sec_info_access.1897758872
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_smoke.4250511718
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_wo.2716261357
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_alert_test.1098878782
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_connect.1982012969
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.3070762504
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_read_seed_err.820128155
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_rma_reset.3816416024
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_sec_otp.2440380889
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd.2268142809
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd_slow_flash.3865363132
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_invalid_op.4041907583
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_lcmgr_intg.1197549196
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_mp_regions.2422639862
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_otp_reset.1808297831
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_phy_arb.3937131049
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_prog_reset.2959147058
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rand_ops.3088182961
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_re_evict.902036334
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_ro.4042310970
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw.4112244133
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict.112632001
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict_all_en.2739823579
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_sec_info_access.1621132477
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_smoke.2240516357
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_wo.574545050
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_alert_test.2574847916
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_connect.3435698508
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.3316504571
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_read_seed_err.2488607958
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_rma_reset.363023424
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd.1929936826
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd_slow_flash.2675777090
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_invalid_op.3881803958
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_lcmgr_intg.1067236860
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_mp_regions.3421669479
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_otp_reset.431063578
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_phy_arb.2133025024
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_prog_reset.1540993954
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rand_ops.3468708207
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_re_evict.1474515118
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_ro.1063622502
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw.1578772654
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict_all_en.3712953824
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_sec_info_access.2476872288
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_smoke.1635639303
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_wo.4246808918
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_alert_test.2549705796
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_connect.2365280780
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_disable.1486949818
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_read_seed_err.774441817
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_rma_reset.900631652
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_sec_otp.1871170984
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd.988548925
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd_slow_flash.3394011281
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_invalid_op.4066281730
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_mp_regions.3484375160
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_otp_reset.3339450237
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_phy_arb.1809079074
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_prog_reset.3536246594
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rand_ops.952436631
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_re_evict.3254982915
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_ro.1508082646
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw.2898622831
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw_evict.4186812148
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw_evict_all_en.784614843
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_sec_info_access.436546722
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_smoke.2107955959
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_wo.1293008531
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_alert_test.3681537873
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_connect.259271401
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_disable.1066764551
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.1573595182
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_read_seed_err.3444266344
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_rma_reset.1737948515
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_sec_otp.3278272366
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_intr_rd.622761811
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_intr_rd_slow_flash.796448420
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_invalid_op.535002061
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_lcmgr_intg.4230564839
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_mp_regions.2122700221
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_otp_reset.2433553392
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_phy_arb.137172649
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_prog_reset.3672393245
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rand_ops.1913617547
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_re_evict.3835656717
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_ro.2227266806
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw.2853659809
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw_evict_all_en.2606785279
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_sec_info_access.2130334464
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_smoke.164769444
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_wo.2946363302
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_alert_test.2612390978
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_connect.421268957
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_disable.452762591
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.2235159999
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_read_seed_err.2470066644
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_rma_reset.3745305486
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_sec_otp.1366230872
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd.1680173172
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd_slow_flash.563970245
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_lcmgr_intg.3786503370
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_mp_regions.1413652336
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_otp_reset.1158356076
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_phy_arb.1729042629
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_prog_reset.1024779579
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rand_ops.3675886813
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_re_evict.3950997345
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_ro.2995879622
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw.3473741187
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw_evict.768188795
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw_evict_all_en.2648647312
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_sec_info_access.3137423587
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_smoke.3790218874
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_wo.2123205367
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_alert_test.4027873060
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_connect.297745798
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_disable.1791595389
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.368610175
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_read_seed_err.1418480011
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_rma_reset.1622847823
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_sec_otp.974843378
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_intr_rd.3584578759
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_intr_rd_slow_flash.2879242502
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_invalid_op.2163023301
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_lcmgr_intg.2485440162
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_mp_regions.432358594
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_otp_reset.2283459980
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_phy_arb.2567279432
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_prog_reset.2282498155
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rand_ops.2873808401
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_re_evict.2048863148
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_ro.4225586060
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw.2417755348
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw_evict_all_en.1113654605
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_sec_info_access.3428631289
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_smoke.3221389944
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_wo.1562616747
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_alert_test.1202660706
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_connect.2690801679
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_disable.3430298536
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.1606624278
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_read_seed_err.3542529279
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_rma_reset.2693877629
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_sec_otp.2666400743
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_intr_rd.3388913003
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_intr_rd_slow_flash.1964409321
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_invalid_op.3981971304
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_lcmgr_intg.2080749486
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_mp_regions.3839256430
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_otp_reset.688569501
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_phy_arb.225427295
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_prog_reset.748884742
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rand_ops.3749341150
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_re_evict.3385655027
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_ro.3348669385
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw.1533770563
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw_evict.1395912747
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw_evict_all_en.256664986
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_sec_info_access.906917392
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_smoke.2960288428
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_wo.2483428236
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_alert_test.3555417252
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_connect.1647572415
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_disable.2618550777
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.3338766507
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_read_seed_err.1960762170
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_rma_reset.3381884464
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_sec_otp.1826829927
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_intr_rd.2230822742
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_intr_rd_slow_flash.2755559070
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_invalid_op.3723783788
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_lcmgr_intg.3048341551
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_mp_regions.3673753682
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_otp_reset.3850141711
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_phy_arb.1968342228
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_prog_reset.2139757122
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rand_ops.849544493
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_re_evict.3670646936
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_ro.3774250110
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw.368620070
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw_evict.3702134002
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw_evict_all_en.1812007502
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_smoke.1861076940
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_wo.3299905002
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_access_after_disable.1225502655
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_alert_test.2536701267
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_config_regwen.509797136
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_derr_detect.758754954
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_disable.445586622
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_erase_suspend.2410785547
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_win.2192799409
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fetch_code.413217219
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fs_sup.2533204200
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_full_mem_access.3652461106
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_addr_infection.2701489917
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_dir_rd.3100637433
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.2251472140
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_read_seed_err.2571858127
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma.3246495191
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma_reset.170227148
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_sec_otp.1070783206
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_integrity.3206027780
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr.1852859638
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr_slow_flash.4020891337
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_invalid_op.1103095032
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_lcmgr_intg.3138483309
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mid_op_rst.4002276144
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_otp_reset.3613110984
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_oversize_error.2323145468
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_ack_consistency.2997872755
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb.2526958494
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb_redun.837242427
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_host_grant_err.2954588947
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_prog_reset.2099920675
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rand_ops.2730057562
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_buff_evict.1822591290
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_intg.2704294947
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_re_evict.2448858533
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_derr.3840718840
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_serr.3829537847
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rma_err.2847262962
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro.3925986916
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_derr.3990292853
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_serr.1380412980
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw.4159251713
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_serr.3330721551
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_cm.3381032214
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_address.3891223320
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_counter.3228364595
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke.1642060244
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke_hw.2991181390
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_stress_all.2371867406
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sw_op.263808154
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wo.1016206254
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_alert_test.498949595
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_connect.2596262519
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_hw_sec_otp.721225722
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_intr_rd.1976792591
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_intr_rd_slow_flash.3504808246
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_otp_reset.383328310
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_prog_reset.2396942322
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_rw_evict.3761731616
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_sec_info_access.1633961561
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_smoke.63476562
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_alert_test.683288892
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_connect.1379788220
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_disable.3718459396
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_hw_sec_otp.3478974830
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_intr_rd.3881521246
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_intr_rd_slow_flash.4262179718
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_prog_reset.212029179
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_sec_info_access.870695054
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_smoke.2055293903
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_alert_test.3150246198
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_connect.2249007912
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_disable.2329630191
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_hw_sec_otp.3060856107
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_intr_rd.2393144762
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_intr_rd_slow_flash.3682752987
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_otp_reset.1651918067
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_prog_reset.2818566756
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_rw_evict.2798552805
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_sec_info_access.444992287
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_smoke.2367235524
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_alert_test.68799040
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_connect.3845959303
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_disable.1594913102
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_hw_sec_otp.2195358677
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_intr_rd.2573125759
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_prog_reset.4288765674
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_rw_evict.4075899781
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_sec_info_access.390529772
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_smoke.566337426
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_alert_test.1265603573
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_connect.4196900098
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_disable.3241882165
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_hw_sec_otp.2824980621
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_intr_rd.162654653
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_intr_rd_slow_flash.2603780957
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_otp_reset.3976665111
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_prog_reset.2903799525
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_rw_evict.694334376
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_rw_evict_all_en.3474881307
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_sec_info_access.2758333933
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_smoke.3116328918
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_alert_test.2793483262
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_connect.1847780377
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_disable.3052464350
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_hw_sec_otp.2649509188
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_intr_rd.3917345335
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_intr_rd_slow_flash.2588609426
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_otp_reset.2654218495
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_prog_reset.1335185551
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_rw_evict_all_en.2735231802
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_sec_info_access.1018412216
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_smoke.1410079911
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_alert_test.3057542090
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_connect.3824363380
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_disable.653519086
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_hw_sec_otp.355708328
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_intr_rd.3304462659
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_intr_rd_slow_flash.2033638909
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_otp_reset.2033990724
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_prog_reset.1933028629
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_rw_evict.2497453477
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_sec_info_access.3439184807
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_smoke.3904662799
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_alert_test.2563538167
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_connect.3126580089
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_disable.2232582861
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_hw_sec_otp.4232965495
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_intr_rd_slow_flash.3120120154
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_otp_reset.2475830356
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_prog_reset.1076514630
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_rw_evict.1567771914
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_rw_evict_all_en.1792933584
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_sec_info_access.984251031
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_smoke.908422267
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_alert_test.1147195425
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_connect.4150717531
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_disable.1530951295
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_hw_sec_otp.927377591
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_intr_rd.25100581
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_intr_rd_slow_flash.584007187
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_otp_reset.97410710
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_prog_reset.541793123
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_rw_evict.4053897020
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_rw_evict_all_en.3062688247
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_sec_info_access.3730710579
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_smoke.1688034944
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_alert_test.3927464603
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_connect.3473998355
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_disable.806918188
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_hw_sec_otp.974921064
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_intr_rd.3187001554
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_intr_rd_slow_flash.440262043
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_otp_reset.4136053648
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_prog_reset.2600056763
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_rw_evict_all_en.2067296004
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_sec_info_access.3480571786
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_smoke.1136080031
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_alert_test.1658136603
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_config_regwen.2174761377
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_connect.2026386290
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_derr_detect.3512141247
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_disable.3457042937
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_erase_suspend.785246370
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_prog_win.2944403418
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fetch_code.742724583
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fs_sup.2995525183
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_full_mem_access.3127193854
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_dir_rd.2146051615
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.1720737972
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_read_seed_err.3962370204
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_rma_reset.394963033
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_sec_otp.1230431703
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_integrity.2918180495
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd.2597256671
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd_slow_flash.4283724576
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr.2805374899
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr_slow_flash.3220396957
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_invalid_op.219249628
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_lcmgr_intg.2661661461
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mp_regions.2580663570
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_otp_reset.821830948
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_oversize_error.923929406
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb.403039260
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_host_grant_err.688270991
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_prog_reset.970453361
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rand_ops.1908826051
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rd_buff_evict.1447684836
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_re_evict.3424665656
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_derr.443424290
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_serr.947146170
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro.1304988377
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_derr.3759792111
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw.2243636998
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_derr.3516543274
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict_all_en.4017491252
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_serr.768100611
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_cm.2874211954
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_address.2850905245
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_counter.3022596373
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke.1270681515
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke_hw.1975514012
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_stress_all.1885508027
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sw_op.3991275278
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_wo.3009698405
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_alert_test.1120840444
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_connect.1024717127
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_disable.2208687545
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_hw_sec_otp.3011785959
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_intr_rd.2478773454
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_intr_rd_slow_flash.147337485
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_otp_reset.3832147827
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_sec_info_access.3452170484
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_smoke.3919107347
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_alert_test.2788403947
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_connect.1513497390
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_disable.1122738729
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_hw_sec_otp.1327535045
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_intr_rd.2942668810
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_intr_rd_slow_flash.217070854
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_otp_reset.1308389930
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_rw_evict_all_en.1565763093
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_sec_info_access.1572163272
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_smoke.4151585987
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_alert_test.2240279304
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_connect.1897651625
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_disable.2965753770
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_hw_sec_otp.3142052004
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_intr_rd.3260951543
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_intr_rd_slow_flash.3624854059
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_rw_evict.610868164
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_rw_evict_all_en.3749114173
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_sec_info_access.1520402892
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_smoke.4015609297
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_alert_test.3827141335
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_connect.4192117362
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_hw_sec_otp.890024720
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_intr_rd.51683200
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_intr_rd_slow_flash.3088652339
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_otp_reset.4110863165
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_rw_evict.2052644782
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_rw_evict_all_en.1362312210
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_sec_info_access.3282981680
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_smoke.383322714
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_alert_test.2542843381
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_connect.3893443877
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_disable.2657339948
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_hw_sec_otp.1306202339
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_intr_rd.233180708
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_intr_rd_slow_flash.1538941524
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_otp_reset.3977278899
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_rw_evict.2694577578
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_rw_evict_all_en.2201124238
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_sec_info_access.1495873583
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_smoke.1700350982
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_alert_test.2073787871
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_connect.3985864813
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_disable.3365368796
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_hw_sec_otp.3511466666
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_intr_rd.4124654213
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_intr_rd_slow_flash.272344888
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_otp_reset.1944853358
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_rw_evict.26223439
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_sec_info_access.3189625938
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_smoke.2566301968
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_alert_test.3785232334
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_connect.1755261672
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_disable.3333343443
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_hw_sec_otp.1971837809
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_intr_rd.3463809467
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_intr_rd_slow_flash.268852784
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_otp_reset.1770572658
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_rw_evict.1128276457
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_rw_evict_all_en.1547726564
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_sec_info_access.4086274911
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_smoke.185271973
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_alert_test.1894868678
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_connect.2648413441
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_disable.3503731190
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_hw_sec_otp.1746700476
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_intr_rd.3408631589
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_intr_rd_slow_flash.1868533445
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_otp_reset.2352635629
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_rw_evict.2456409507
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_smoke.2477254582
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_alert_test.309476547
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_connect.2737976295
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_disable.1137702994
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_hw_sec_otp.3743531735
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_intr_rd.2149377035
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_intr_rd_slow_flash.3273374224
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_otp_reset.1484663922
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_rw_evict.4056909715
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_rw_evict_all_en.3716927876
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_sec_info_access.574509039
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_smoke.28085492
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_alert_test.15753997
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_connect.1567177951
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_disable.1211467053
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_hw_sec_otp.3126227070
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_intr_rd.3008225491
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_intr_rd_slow_flash.3419935038
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_otp_reset.3080588461
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_rw_evict.2963978787
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_rw_evict_all_en.68362431
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_sec_info_access.2853115910
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_smoke.327967978
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_alert_test.2277951156
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_config_regwen.4004980836
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_connect.4233410976
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_disable.377361270
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_erase_suspend.2099816020
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_prog_win.3992741678
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fetch_code.1758553572
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fs_sup.3994436326
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_full_mem_access.4147940966
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_dir_rd.2747458415
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.3346942999
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_read_seed_err.513607685
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_rma_reset.1215569580
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_sec_otp.3561119157
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd.119378479
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd_slow_flash.245604229
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr.1956883119
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr_slow_flash.222147202
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_invalid_op.4120952443
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_lcmgr_intg.2245615409
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mid_op_rst.1606111040
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mp_regions.1606634437
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_otp_reset.4080248772
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_oversize_error.4211323389
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_ack_consistency.1905990695
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb.4100720020
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_host_grant_err.4129953380
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_prog_reset.3600120104
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rand_ops.2858638058
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rd_buff_evict.1860745032
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_re_evict.3158534535
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_derr.427925602
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_serr.1363776915
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro.34846309
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_derr.2145645637
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_serr.2508336764
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw.2438331329
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_derr.2222287205
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict_all_en.1388220146
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_serr.2675575724
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_info_access.2992032662
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_address.226027310
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_counter.3455840067
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke.4260158621
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke_hw.1714598516
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_stress_all.3994541648
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sw_op.1855165178
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_wo.3024038761
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_alert_test.221551951
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_connect.4133274325
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_disable.1017146381
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_hw_sec_otp.1581767472
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_otp_reset.1860133476
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_sec_info_access.2225922640
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_smoke.3985531508
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_alert_test.2068349764
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_connect.54576488
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_disable.1514849090
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_hw_sec_otp.302567766
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_otp_reset.962321663
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_sec_info_access.1553262881
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_smoke.46050044
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_alert_test.27138167
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_connect.3069223841
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_disable.3331068355
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_hw_sec_otp.3412649413
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_otp_reset.620248827
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_smoke.1782650160
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_alert_test.2876013743
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_connect.2083903618
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_disable.440737108
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_hw_sec_otp.1598832575
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_otp_reset.1506827999
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_sec_info_access.3241227193
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_smoke.2458172612
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_alert_test.4110956933
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_connect.3882585548
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_hw_sec_otp.3324055342
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_otp_reset.3903429912
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_sec_info_access.1769209439
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_smoke.2321963198
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_alert_test.309370329
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_connect.2809589453
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_disable.2137564370
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_hw_sec_otp.16202123
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_otp_reset.1486732812
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_sec_info_access.401287130
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_smoke.897036940
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_alert_test.1326128841
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_connect.227835302
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_disable.2138582774
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_hw_sec_otp.3896690923
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_otp_reset.1069259271
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_sec_info_access.793010366
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_smoke.3372285344
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_alert_test.963300046
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_connect.650849641
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_hw_sec_otp.1787637432
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_otp_reset.277989345
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_sec_info_access.2256445654
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_smoke.1937004099
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_alert_test.2180689250
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_connect.4044724177
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_disable.505433225
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_hw_sec_otp.784811484
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_otp_reset.1763021976
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_sec_info_access.442632373
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_smoke.498362841
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_alert_test.1440069950
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_connect.2440289882
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_disable.1168231416
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_hw_sec_otp.1432334392
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_otp_reset.3517274822
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_sec_info_access.2476023663
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_smoke.3233469100
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_alert_test.1199243622
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_connect.461022433
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_disable.1446916067
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_prog_win.3599945401
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_fetch_code.2076043688
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.1251421258
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_read_seed_err.3990019804
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_rma_reset.467257731
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_sec_otp.865519299
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd.3454279834
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd_slow_flash.3243257297
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr.1451533327
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr_slow_flash.3076969315
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_invalid_op.1048092276
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_lcmgr_intg.929042003
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_mp_regions.2836027622
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_phy_arb.2641729770
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_prog_reset.267752879
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rand_ops.1585191282
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_re_evict.1955565586
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro.3366865056
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_derr.765635018
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_serr.359976658
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_derr.1822421038
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict.814830710
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict_all_en.1345348794
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_serr.2033732795
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_sec_info_access.3941051629
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_smoke.4249926296
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_wo.2330843458
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_connect.4127941369
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_otp_reset.1646703094
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_connect.215825053
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_otp_reset.2125717194
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_connect.1277084520
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_otp_reset.127901412
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_connect.357889412
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_otp_reset.2425253245
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_connect.3360356843
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_otp_reset.1801832861
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_connect.3983372835
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_otp_reset.1775583271
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_connect.176737957
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_otp_reset.981907235
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_connect.669432774
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_otp_reset.2003577165
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_connect.4202462477
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_otp_reset.352489621
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_connect.3780541191
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_otp_reset.801056549
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_alert_test.4056435404
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_connect.1919769974
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_disable.2472041084
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_prog_win.3043726566
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_fetch_code.3107589073
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.400792131
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_read_seed_err.1627279118
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_rma_reset.1395744439
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_sec_otp.3807376078
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd.2727284182
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd_slow_flash.2673039605
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr.1153073253
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr_slow_flash.4165356875
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_invalid_op.2625883523
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_lcmgr_intg.337151070
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_mp_regions.620244347
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_otp_reset.2682311693
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_phy_arb.2077612953
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_prog_reset.98560194
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rand_ops.3851582415
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_re_evict.3474602351
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro.1358692007
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_derr.3343464119
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_serr.3078712404
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw.2887069157
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_derr.1821120791
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict.218299516
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict_all_en.2384500476
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_serr.4074493905
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_sec_info_access.3556262522
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_smoke.1191320997
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_wo.3380053940
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_connect.4139077135
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_otp_reset.2390849956
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_connect.2195392511
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_otp_reset.2161799969
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_connect.4043859107
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_otp_reset.4047673258
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_connect.224017652
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_otp_reset.499581328
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_connect.1608292442
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_otp_reset.577607982
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_connect.2294217797
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_otp_reset.1169258779
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_connect.1180042616
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_otp_reset.2688690514
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_connect.1648394937
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_otp_reset.1232404609
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_connect.2020173466
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_otp_reset.3066134323
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_connect.664212073
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_otp_reset.1376457863
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_alert_test.1209775932
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_connect.380436322
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_disable.779272316
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_prog_win.1729535036
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_fetch_code.1895111586
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.653070641
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_read_seed_err.4060964325
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_rma_reset.2983409078
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_sec_otp.1142083120
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd_slow_flash.4076894510
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr.2241729060
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr_slow_flash.3343604379
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_invalid_op.3215555131
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_lcmgr_intg.2461940438
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_mp_regions.3569486374
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_phy_arb.1091850753
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_prog_reset.760028100
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rand_ops.3236220059
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_re_evict.3267661910
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro.104162614
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_derr.3566754272
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_serr.1582682805
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw.3447943057
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_derr.4211103756
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict_all_en.75270967
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_serr.528975401
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_sec_info_access.2573848286
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_smoke.2719924319
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_wo.498780778
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_connect.395424015
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_otp_reset.3142916492
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_connect.2659378452
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_connect.437156068
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_otp_reset.1421668049
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_connect.3295483230
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_otp_reset.2622613296
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_connect.2107992980
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_otp_reset.3600305168
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_connect.3900861414
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_otp_reset.625986526
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_connect.3588579752
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_otp_reset.663380515
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_connect.2232889506
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_otp_reset.2413160105
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_connect.3788166885
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_otp_reset.2430823581
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_connect.3973222735
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_otp_reset.3851643561
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_alert_test.798674986
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_connect.1445096993
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_disable.3942137627
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_prog_win.1551752771
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_fetch_code.212362011
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.3589156886
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_read_seed_err.3030834901
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_rma_reset.2728691407
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_sec_otp.2721519991
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd.3240747181
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd_slow_flash.1684931882
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr.1885852962
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr_slow_flash.1636777098
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_invalid_op.2559808514
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_lcmgr_intg.1525396767
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_mp_regions.2743599241
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_otp_reset.1085872370
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_phy_arb.1349720382
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_prog_reset.517011363
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rand_ops.2081984870
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_re_evict.1937352587
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro.3738296272
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_derr.2995070985
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_serr.739523842
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw.120065902
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_derr.3877338075
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict.2922877395
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_serr.2074787307
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_sec_info_access.1516665323
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_smoke.1202212386
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_wo.991460101
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_alert_test.2294552642
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_connect.2797284886
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_disable.3348755551
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_prog_win.4226806327
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_fetch_code.1770367285
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.1059359567
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_read_seed_err.2259982450
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_rma_reset.1347844867
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_sec_otp.3520447355
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd.1800105729
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd_slow_flash.3272010999
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr.3639404407
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr_slow_flash.3727048428
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_invalid_op.4209870165
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_lcmgr_intg.1118553457
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_mp_regions.1799189282
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_otp_reset.3490446146
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_phy_arb.1161858751
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_prog_reset.346537525
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rand_ops.3993382849
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_re_evict.1397278147
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro.3695265725
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_derr.1250986529
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_serr.1525316690
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw.1417122470
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_derr.1386092445
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict.2723435445
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict_all_en.2127703021
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_serr.1225909760
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_sec_info_access.1440622538
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_smoke.75579721
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_wo.1769354201



Total test records in report: 1241
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_prog_reset.1294242880 Aug 25 02:12:13 PM UTC 24 Aug 25 02:12:40 PM UTC 24 30111400 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_write_word_sweep.166660258 Aug 25 02:12:12 PM UTC 24 Aug 25 02:12:41 PM UTC 24 205499100 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep.1253829127 Aug 25 02:12:12 PM UTC 24 Aug 25 02:12:41 PM UTC 24 36096600 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_connect.1854592250 Aug 25 02:12:19 PM UTC 24 Aug 25 02:12:45 PM UTC 24 34059500 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wr_intg.3884294694 Aug 25 02:12:24 PM UTC 24 Aug 25 02:12:50 PM UTC 24 43778600 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_access_after_disable.20673128 Aug 25 02:12:26 PM UTC 24 Aug 25 02:12:51 PM UTC 24 17278200 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_derr.4100512740 Aug 25 02:12:12 PM UTC 24 Aug 25 02:12:52 PM UTC 24 19097400 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fetch_code.394787123 Aug 25 02:12:10 PM UTC 24 Aug 25 02:12:54 PM UTC 24 1282103000 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_disable.49835935 Aug 25 02:12:14 PM UTC 24 Aug 25 02:12:55 PM UTC 24 13121200 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_serr.286149889 Aug 25 02:12:12 PM UTC 24 Aug 25 02:12:57 PM UTC 24 154006200 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke_hw.749560848 Aug 25 02:12:09 PM UTC 24 Aug 25 02:13:01 PM UTC 24 20135500 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sw_op.764903236 Aug 25 02:12:09 PM UTC 24 Aug 25 02:13:02 PM UTC 24 176164800 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_lcmgr_intg.4171656833 Aug 25 02:12:42 PM UTC 24 Aug 25 02:13:04 PM UTC 24 48655600 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_ack_consistency.2626180497 Aug 25 02:12:39 PM UTC 24 Aug 25 02:13:04 PM UTC 24 26307000 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_host_grant_err.1269053554 Aug 25 02:12:39 PM UTC 24 Aug 25 02:13:07 PM UTC 24 42282400 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_config_regwen.700011983 Aug 25 02:12:40 PM UTC 24 Aug 25 02:13:07 PM UTC 24 68893000 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_read_seed_err.57645427 Aug 25 02:12:42 PM UTC 24 Aug 25 02:13:09 PM UTC 24 26341600 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict_all_en.2473034930 Aug 25 02:12:14 PM UTC 24 Aug 25 02:13:10 PM UTC 24 31199200 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_re_evict.1442771273 Aug 25 02:12:14 PM UTC 24 Aug 25 02:13:13 PM UTC 24 73009000 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_intg.858891356 Aug 25 02:12:21 PM UTC 24 Aug 25 02:13:14 PM UTC 24 65240000 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_alert_test.1830319976 Aug 25 02:12:52 PM UTC 24 Aug 25 02:13:14 PM UTC 24 115317700 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb_redun.1667592482 Aug 25 02:12:36 PM UTC 24 Aug 25 02:13:20 PM UTC 24 845673800 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fs_sup.621966379 Aug 25 02:12:27 PM UTC 24 Aug 25 02:13:28 PM UTC 24 1768231900 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr.377447780 Aug 25 02:12:12 PM UTC 24 Aug 25 02:13:40 PM UTC 24 4158929500 ps
T78 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke.450947229 Aug 25 02:12:07 PM UTC 24 Aug 25 02:13:40 PM UTC 24 43197900 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke_hw.1173398732 Aug 25 02:12:55 PM UTC 24 Aug 25 02:13:41 PM UTC 24 27253900 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_dir_rd.1257981300 Aug 25 02:12:10 PM UTC 24 Aug 25 02:13:42 PM UTC 24 63449300 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_invalid_op.4160188913 Aug 25 02:12:12 PM UTC 24 Aug 25 02:13:43 PM UTC 24 23311511100 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sw_op.2260141932 Aug 25 02:12:57 PM UTC 24 Aug 25 02:13:46 PM UTC 24 45644500 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_addr_infection.2977710672 Aug 25 02:12:51 PM UTC 24 Aug 25 02:13:52 PM UTC 24 174422600 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_counter.791437765 Aug 25 02:12:12 PM UTC 24 Aug 25 02:13:54 PM UTC 24 657017700 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fetch_code.2180436737 Aug 25 02:13:13 PM UTC 24 Aug 25 02:13:54 PM UTC 24 146550500 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_info_access.2103244532 Aug 25 02:12:16 PM UTC 24 Aug 25 02:14:07 PM UTC 24 11682139500 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_ooo.1316985305 Aug 25 02:12:47 PM UTC 24 Aug 25 02:14:09 PM UTC 24 289527700 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke.4069877498 Aug 25 02:12:53 PM UTC 24 Aug 25 02:14:23 PM UTC 24 39672900 ps
T142 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.2006520322 Aug 25 02:12:45 PM UTC 24 Aug 25 02:14:23 PM UTC 24 10039359700 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_serr.2121237422 Aug 25 02:13:46 PM UTC 24 Aug 25 02:14:27 PM UTC 24 24396700 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mid_op_rst.3281041315 Aug 25 02:12:12 PM UTC 24 Aug 25 02:14:37 PM UTC 24 7321999900 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_serr.3141901139 Aug 25 02:12:12 PM UTC 24 Aug 25 02:14:47 PM UTC 24 2300045400 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_derr.904494531 Aug 25 02:14:09 PM UTC 24 Aug 25 02:14:50 PM UTC 24 57985200 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_address.372243456 Aug 25 02:12:12 PM UTC 24 Aug 25 02:15:01 PM UTC 24 19730275800 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro.971390262 Aug 25 02:12:12 PM UTC 24 Aug 25 02:15:06 PM UTC 24 1176392900 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_invalid_op.3980108858 Aug 25 02:13:41 PM UTC 24 Aug 25 02:15:22 PM UTC 24 3418393000 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_buff_evict.110286956 Aug 25 02:12:10 PM UTC 24 Aug 25 02:15:30 PM UTC 24 1503715300 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_sec_otp.4287041554 Aug 25 02:12:10 PM UTC 24 Aug 25 02:15:30 PM UTC 24 9464992400 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_derr.1481698931 Aug 25 02:12:12 PM UTC 24 Aug 25 02:15:44 PM UTC 24 2434114200 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_counter.270709128 Aug 25 02:13:55 PM UTC 24 Aug 25 02:15:47 PM UTC 24 1318936000 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mid_op_rst.1139555542 Aug 25 02:13:41 PM UTC 24 Aug 25 02:15:49 PM UTC 24 1989113300 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_prog_reset.1458868049 Aug 25 02:15:22 PM UTC 24 Aug 25 02:15:50 PM UTC 24 19402300 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_otp_reset.3685770717 Aug 25 02:12:10 PM UTC 24 Aug 25 02:15:55 PM UTC 24 150961300 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_disable.4102111811 Aug 25 02:15:36 PM UTC 24 Aug 25 02:16:15 PM UTC 24 35956000 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict.3439995114 Aug 25 02:15:25 PM UTC 24 Aug 25 02:16:18 PM UTC 24 47530800 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_connect.197183925 Aug 25 02:15:50 PM UTC 24 Aug 25 02:16:18 PM UTC 24 18843500 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_address.2000509475 Aug 25 02:14:09 PM UTC 24 Aug 25 02:16:23 PM UTC 24 1601779000 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_dir_rd.484704833 Aug 25 02:13:01 PM UTC 24 Aug 25 02:16:25 PM UTC 24 228785800 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr.947928563 Aug 25 02:14:51 PM UTC 24 Aug 25 02:16:28 PM UTC 24 2461064500 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict_all_en.1440426375 Aug 25 02:15:31 PM UTC 24 Aug 25 02:16:30 PM UTC 24 225606800 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_re_evict.187053727 Aug 25 02:15:31 PM UTC 24 Aug 25 02:16:33 PM UTC 24 64916200 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_buff_evict.3150981081 Aug 25 02:13:02 PM UTC 24 Aug 25 02:16:35 PM UTC 24 314981000 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wr_intg.3555611029 Aug 25 02:16:16 PM UTC 24 Aug 25 02:16:45 PM UTC 24 113271300 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro.656213017 Aug 25 02:13:43 PM UTC 24 Aug 25 02:16:46 PM UTC 24 2638917900 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_access_after_disable.384327180 Aug 25 02:16:19 PM UTC 24 Aug 25 02:16:46 PM UTC 24 40124500 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wo.1767037978 Aug 25 02:12:12 PM UTC 24 Aug 25 02:16:48 PM UTC 24 3406325400 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_ack_consistency.684581849 Aug 25 02:16:26 PM UTC 24 Aug 25 02:16:51 PM UTC 24 31081800 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_host_grant_err.2345146589 Aug 25 02:16:26 PM UTC 24 Aug 25 02:16:53 PM UTC 24 16293200 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_config_regwen.3071043420 Aug 25 02:16:29 PM UTC 24 Aug 25 02:16:58 PM UTC 24 35945900 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb_redun.4147596938 Aug 25 02:16:24 PM UTC 24 Aug 25 02:16:59 PM UTC 24 835752700 ps
T348 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_intg.1643280104 Aug 25 02:15:56 PM UTC 24 Aug 25 02:17:00 PM UTC 24 498723600 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_lcmgr_intg.2135598413 Aug 25 02:16:34 PM UTC 24 Aug 25 02:17:02 PM UTC 24 15907500 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_read_seed_err.1865098663 Aug 25 02:16:36 PM UTC 24 Aug 25 02:17:04 PM UTC 24 141517700 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_otp_reset.2939015424 Aug 25 02:13:09 PM UTC 24 Aug 25 02:17:11 PM UTC 24 143291000 ps
T121 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_alert_test.185081703 Aug 25 02:16:47 PM UTC 24 Aug 25 02:17:13 PM UTC 24 165535500 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_serr.359794015 Aug 25 02:13:53 PM UTC 24 Aug 25 02:17:17 PM UTC 24 2579408900 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fs_sup.2970776036 Aug 25 02:16:19 PM UTC 24 Aug 25 02:17:19 PM UTC 24 1228537400 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb.1139692082 Aug 25 02:13:03 PM UTC 24 Aug 25 02:17:24 PM UTC 24 719087100 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd.615729349 Aug 25 02:12:12 PM UTC 24 Aug 25 02:17:29 PM UTC 24 15797828300 ps
T124 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_serr.2560975570 Aug 25 02:12:12 PM UTC 24 Aug 25 02:17:29 PM UTC 24 7829264100 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_addr_infection.2416169223 Aug 25 02:16:46 PM UTC 24 Aug 25 02:17:43 PM UTC 24 65802300 ps
T415 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wo.1109917721 Aug 25 02:13:42 PM UTC 24 Aug 25 02:17:43 PM UTC 24 2655102100 ps
T437 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke_hw.2991181390 Aug 25 02:16:52 PM UTC 24 Aug 25 02:17:44 PM UTC 24 29031300 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_derr.1396674162 Aug 25 02:14:10 PM UTC 24 Aug 25 02:17:44 PM UTC 24 2556582200 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_derr_detect.2952929732 Aug 25 02:12:12 PM UTC 24 Aug 25 02:17:44 PM UTC 24 966178200 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_info_access.1603660062 Aug 25 02:15:48 PM UTC 24 Aug 25 02:17:46 PM UTC 24 2530231800 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_oversize_error.772537802 Aug 25 02:12:12 PM UTC 24 Aug 25 02:17:52 PM UTC 24 3553580000 ps
T438 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sw_op.263808154 Aug 25 02:16:59 PM UTC 24 Aug 25 02:17:52 PM UTC 24 45302100 ps
T227 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_derr.264996211 Aug 25 02:12:12 PM UTC 24 Aug 25 02:18:05 PM UTC 24 1788023200 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_serr.3027654116 Aug 25 02:13:55 PM UTC 24 Aug 25 02:18:15 PM UTC 24 7408126700 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fetch_code.413217219 Aug 25 02:17:30 PM UTC 24 Aug 25 02:18:17 PM UTC 24 2130727700 ps
T125 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_sec_otp.904589093 Aug 25 02:13:05 PM UTC 24 Aug 25 02:18:22 PM UTC 24 12371201900 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb.1559421834 Aug 25 02:12:10 PM UTC 24 Aug 25 02:18:23 PM UTC 24 6090409800 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_dir_rd.3100637433 Aug 25 02:17:00 PM UTC 24 Aug 25 02:18:35 PM UTC 24 119952900 ps
T416 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_serr.3829537847 Aug 25 02:17:53 PM UTC 24 Aug 25 02:18:35 PM UTC 24 46581600 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_derr.19345524 Aug 25 02:14:24 PM UTC 24 Aug 25 02:19:00 PM UTC 24 1825173700 ps
T419 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_derr.3840718840 Aug 25 02:18:23 PM UTC 24 Aug 25 02:19:01 PM UTC 24 18642100 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_oversize_error.3781462724 Aug 25 02:14:28 PM UTC 24 Aug 25 02:19:17 PM UTC 24 6883806500 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_invalid_op.1103095032 Aug 25 02:17:45 PM UTC 24 Aug 25 02:19:32 PM UTC 24 974430200 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_counter.3228364595 Aug 25 02:18:16 PM UTC 24 Aug 25 02:19:39 PM UTC 24 979287800 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_address.3891223320 Aug 25 02:18:18 PM UTC 24 Aug 25 02:19:50 PM UTC 24 3902388500 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd_slow_flash.1194292762 Aug 25 02:12:13 PM UTC 24 Aug 25 02:19:50 PM UTC 24 61309682600 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr_slow_flash.1663936336 Aug 25 02:12:13 PM UTC 24 Aug 25 02:19:54 PM UTC 24 103645726600 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mid_op_rst.4002276144 Aug 25 02:17:45 PM UTC 24 Aug 25 02:19:54 PM UTC 24 10263966000 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_derr_detect.4008526340 Aug 25 02:14:25 PM UTC 24 Aug 25 02:19:56 PM UTC 24 773007100 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd.1363034161 Aug 25 02:14:48 PM UTC 24 Aug 25 02:20:00 PM UTC 24 7124109600 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_buff_evict.1822591290 Aug 25 02:17:01 PM UTC 24 Aug 25 02:20:19 PM UTC 24 900930600 ps
T411 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr.1852859638 Aug 25 02:19:05 PM UTC 24 Aug 25 02:20:24 PM UTC 24 4217841500 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_disable.445586622 Aug 25 02:19:54 PM UTC 24 Aug 25 02:20:32 PM UTC 24 10530300 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mp_regions.2605862468 Aug 25 02:17:25 PM UTC 24 Aug 25 02:20:34 PM UTC 24 7850227800 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro.3925986916 Aug 25 02:17:52 PM UTC 24 Aug 25 02:20:35 PM UTC 24 2168547700 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_connect.2566882953 Aug 25 02:20:20 PM UTC 24 Aug 25 02:20:43 PM UTC 24 15533400 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.118606397 Aug 25 02:16:45 PM UTC 24 Aug 25 02:20:53 PM UTC 24 10012141300 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wo.1016206254 Aug 25 02:17:47 PM UTC 24 Aug 25 02:20:55 PM UTC 24 3739663700 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_re_evict.2448858533 Aug 25 02:19:51 PM UTC 24 Aug 25 02:20:58 PM UTC 24 265910100 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wr_intg.506445347 Aug 25 02:20:33 PM UTC 24 Aug 25 02:21:00 PM UTC 24 47583000 ps
T126 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_sec_otp.1070783206 Aug 25 02:17:02 PM UTC 24 Aug 25 02:21:02 PM UTC 24 4248465900 ps
T98 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_otp_reset.3613110984 Aug 25 02:17:18 PM UTC 24 Aug 25 02:21:04 PM UTC 24 40554000 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_access_after_disable.1225502655 Aug 25 02:20:35 PM UTC 24 Aug 25 02:21:05 PM UTC 24 41237900 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_host_grant_err.2954588947 Aug 25 02:20:44 PM UTC 24 Aug 25 02:21:09 PM UTC 24 84781400 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_serr.1380412980 Aug 25 02:17:54 PM UTC 24 Aug 25 02:21:12 PM UTC 24 3044144500 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_ack_consistency.2997872755 Aug 25 02:20:47 PM UTC 24 Aug 25 02:21:13 PM UTC 24 17268800 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb_redun.837242427 Aug 25 02:20:39 PM UTC 24 Aug 25 02:21:14 PM UTC 24 785715000 ps
T386 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_config_regwen.509797136 Aug 25 02:20:54 PM UTC 24 Aug 25 02:21:23 PM UTC 24 21216900 ps
T311 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_intg.2704294947 Aug 25 02:20:25 PM UTC 24 Aug 25 02:21:25 PM UTC 24 64031500 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_lcmgr_intg.3138483309 Aug 25 02:20:58 PM UTC 24 Aug 25 02:21:28 PM UTC 24 207842700 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_read_seed_err.2571858127 Aug 25 02:21:01 PM UTC 24 Aug 25 02:21:29 PM UTC 24 27051000 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_alert_test.2536701267 Aug 25 02:21:07 PM UTC 24 Aug 25 02:21:33 PM UTC 24 33120000 ps
T412 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke.1642060244 Aug 25 02:16:49 PM UTC 24 Aug 25 02:21:34 PM UTC 24 32732100 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_derr.3990292853 Aug 25 02:18:25 PM UTC 24 Aug 25 02:21:35 PM UTC 24 2028445700 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fs_sup.2533204200 Aug 25 02:20:36 PM UTC 24 Aug 25 02:21:37 PM UTC 24 352856900 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_info_access.238371769 Aug 25 02:19:57 PM UTC 24 Aug 25 02:21:39 PM UTC 24 1583933100 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd.3471482203 Aug 25 02:19:03 PM UTC 24 Aug 25 02:21:54 PM UTC 24 548928200 ps
T429 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_addr_infection.2701489917 Aug 25 02:21:05 PM UTC 24 Aug 25 02:21:57 PM UTC 24 63748600 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mp_regions.1676669530 Aug 25 02:13:11 PM UTC 24 Aug 25 02:22:01 PM UTC 24 55775179400 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sw_op.3991275278 Aug 25 02:21:14 PM UTC 24 Aug 25 02:22:04 PM UTC 24 25021100 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke_hw.1975514012 Aug 25 02:21:13 PM UTC 24 Aug 25 02:22:08 PM UTC 24 26089500 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fetch_code.742724583 Aug 25 02:21:40 PM UTC 24 Aug 25 02:22:23 PM UTC 24 1545736300 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_serr.3330721551 Aug 25 02:18:09 PM UTC 24 Aug 25 02:22:35 PM UTC 24 2775155800 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_dir_rd.2146051615 Aug 25 02:21:15 PM UTC 24 Aug 25 02:22:50 PM UTC 24 54406800 ps
T79 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd_slow_flash.1976647916 Aug 25 02:15:02 PM UTC 24 Aug 25 02:22:52 PM UTC 24 11843310500 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr_slow_flash.891618496 Aug 25 02:15:07 PM UTC 24 Aug 25 02:23:16 PM UTC 24 95993124800 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_serr.947146170 Aug 25 02:22:39 PM UTC 24 Aug 25 02:23:20 PM UTC 24 154766800 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_derr.4024560929 Aug 25 02:18:37 PM UTC 24 Aug 25 02:23:24 PM UTC 24 2859745600 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_oversize_error.2323145468 Aug 25 02:19:01 PM UTC 24 Aug 25 02:23:36 PM UTC 24 2796751900 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_invalid_op.219249628 Aug 25 02:22:09 PM UTC 24 Aug 25 02:23:53 PM UTC 24 7964687000 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_derr_detect.758754954 Aug 25 02:18:37 PM UTC 24 Aug 25 02:23:54 PM UTC 24 2273211300 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw.1593780798 Aug 25 02:12:12 PM UTC 24 Aug 25 02:24:01 PM UTC 24 11617020900 ps
T420 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_derr.443424290 Aug 25 02:23:21 PM UTC 24 Aug 25 02:24:02 PM UTC 24 18814100 ps
T439 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_prog_reset.2099920675 Aug 25 02:19:33 PM UTC 24 Aug 25 02:24:03 PM UTC 24 2747620700 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mid_op_rst.24306816 Aug 25 02:22:11 PM UTC 24 Aug 25 02:24:15 PM UTC 24 6033202300 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.2251472140 Aug 25 02:21:02 PM UTC 24 Aug 25 02:24:24 PM UTC 24 10011877800 ps
T440 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_sec_otp.1230431703 Aug 25 02:21:28 PM UTC 24 Aug 25 02:24:38 PM UTC 24 13862081900 ps
T441 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_counter.3022596373 Aug 25 02:23:14 PM UTC 24 Aug 25 02:24:49 PM UTC 24 549780000 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro.1304988377 Aug 25 02:22:33 PM UTC 24 Aug 25 02:25:01 PM UTC 24 2302021500 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rd_buff_evict.1447684836 Aug 25 02:21:24 PM UTC 24 Aug 25 02:25:12 PM UTC 24 742735800 ps
T344 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd_slow_flash.1276127544 Aug 25 02:19:19 PM UTC 24 Aug 25 02:25:25 PM UTC 24 11418864200 ps
T143 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_otp_reset.821830948 Aug 25 02:21:36 PM UTC 24 Aug 25 02:25:30 PM UTC 24 78904900 ps
T442 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_address.2850905245 Aug 25 02:23:17 PM UTC 24 Aug 25 02:25:33 PM UTC 24 3519274500 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict_all_en.4017491252 Aug 25 02:24:55 PM UTC 24 Aug 25 02:25:47 PM UTC 24 46408100 ps
T443 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_wo.3009698405 Aug 25 02:22:24 PM UTC 24 Aug 25 02:25:50 PM UTC 24 8190687200 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_disable.3457042937 Aug 25 02:25:13 PM UTC 24 Aug 25 02:25:50 PM UTC 24 15416300 ps
T414 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr.2805374899 Aug 25 02:24:04 PM UTC 24 Aug 25 02:25:55 PM UTC 24 15503720000 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_re_evict.3424665656 Aug 25 02:25:02 PM UTC 24 Aug 25 02:26:04 PM UTC 24 384869100 ps
T444 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_connect.2026386290 Aug 25 02:25:34 PM UTC 24 Aug 25 02:26:04 PM UTC 24 27605700 ps
T445 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr_slow_flash.4020891337 Aug 25 02:19:22 PM UTC 24 Aug 25 02:26:09 PM UTC 24 105674772900 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_serr.2987094668 Aug 25 02:22:51 PM UTC 24 Aug 25 02:26:12 PM UTC 24 2620121300 ps
T413 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke.1270681515 Aug 25 02:21:10 PM UTC 24 Aug 25 02:26:14 PM UTC 24 510456900 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_config_regwen.2174761377 Aug 25 02:25:53 PM UTC 24 Aug 25 02:26:18 PM UTC 24 20492300 ps
T446 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_host_grant_err.688270991 Aug 25 02:25:51 PM UTC 24 Aug 25 02:26:20 PM UTC 24 43606400 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb_redun.1771425389 Aug 25 02:25:48 PM UTC 24 Aug 25 02:26:21 PM UTC 24 917043400 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_ack_consistency.3528925482 Aug 25 02:25:51 PM UTC 24 Aug 25 02:26:22 PM UTC 24 39541100 ps
T447 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_lcmgr_intg.2661661461 Aug 25 02:25:56 PM UTC 24 Aug 25 02:26:24 PM UTC 24 41842100 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_read_seed_err.3962370204 Aug 25 02:26:05 PM UTC 24 Aug 25 02:26:31 PM UTC 24 25875500 ps
T428 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_derr.3759792111 Aug 25 02:23:24 PM UTC 24 Aug 25 02:26:36 PM UTC 24 1201915700 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_alert_test.1658136603 Aug 25 02:26:10 PM UTC 24 Aug 25 02:26:39 PM UTC 24 282888500 ps
T349 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fs_sup.2995525183 Aug 25 02:25:47 PM UTC 24 Aug 25 02:26:41 PM UTC 24 1495165300 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_prog_reset.970453361 Aug 25 02:24:39 PM UTC 24 Aug 25 02:26:45 PM UTC 24 3802499100 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb.2526958494 Aug 25 02:17:02 PM UTC 24 Aug 25 02:26:50 PM UTC 24 2952929900 ps
T80 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mp_regions.619025516 Aug 25 02:12:10 PM UTC 24 Aug 25 02:26:52 PM UTC 24 8685147000 ps
T448 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke_hw.1714598516 Aug 25 02:26:15 PM UTC 24 Aug 25 02:27:02 PM UTC 24 16457600 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_erase_suspend.2410785547 Aug 25 02:17:04 PM UTC 24 Aug 25 02:27:07 PM UTC 24 2129931500 ps
T449 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sw_op.1855165178 Aug 25 02:26:21 PM UTC 24 Aug 25 02:27:08 PM UTC 24 25593400 ps
T450 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_serr.768100611 Aug 25 02:22:53 PM UTC 24 Aug 25 02:27:12 PM UTC 24 1530369100 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_erase_suspend.1294731614 Aug 25 02:12:10 PM UTC 24 Aug 25 02:27:17 PM UTC 24 41877723800 ps
T390 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_info_access.342209289 Aug 25 02:25:25 PM UTC 24 Aug 25 02:27:29 PM UTC 24 6255278800 ps
T436 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_integrity.3014694848 Aug 25 02:12:12 PM UTC 24 Aug 25 02:27:31 PM UTC 24 37267260900 ps
T451 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fetch_code.1758553572 Aug 25 02:26:50 PM UTC 24 Aug 25 02:27:34 PM UTC 24 1225920800 ps
T452 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.1720737972 Aug 25 02:26:05 PM UTC 24 Aug 25 02:27:39 PM UTC 24 10047995000 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw.343741210 Aug 25 02:13:44 PM UTC 24 Aug 25 02:27:47 PM UTC 24 19993661100 ps
T453 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_oversize_error.923929406 Aug 25 02:23:55 PM UTC 24 Aug 25 02:27:51 PM UTC 24 2282091500 ps
T454 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_integrity.1873995419 Aug 25 02:14:38 PM UTC 24 Aug 25 02:27:55 PM UTC 24 5035177800 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd_slow_flash.4283724576 Aug 25 02:24:16 PM UTC 24 Aug 25 02:28:02 PM UTC 24 11652990000 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_erase_suspend.4000535682 Aug 25 02:13:05 PM UTC 24 Aug 25 02:28:11 PM UTC 24 13933348900 ps
T455 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_serr.1363776915 Aug 25 02:27:40 PM UTC 24 Aug 25 02:28:14 PM UTC 24 23440600 ps
T456 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw.4159251713 Aug 25 02:17:53 PM UTC 24 Aug 25 02:28:26 PM UTC 24 3850974400 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_derr.3516543274 Aug 25 02:23:36 PM UTC 24 Aug 25 02:28:38 PM UTC 24 2647991800 ps
T457 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_derr.427925602 Aug 25 02:28:02 PM UTC 24 Aug 25 02:28:39 PM UTC 24 59359400 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_derr_detect.3512141247 Aug 25 02:23:54 PM UTC 24 Aug 25 02:28:43 PM UTC 24 1457052600 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_dir_rd.2747458415 Aug 25 02:26:22 PM UTC 24 Aug 25 02:29:11 PM UTC 24 50545100 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd.2597256671 Aug 25 02:24:03 PM UTC 24 Aug 25 02:29:18 PM UTC 24 9868811100 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mid_op_rst.1606111040 Aug 25 02:27:17 PM UTC 24 Aug 25 02:29:19 PM UTC 24 646318300 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_invalid_op.4120952443 Aug 25 02:27:13 PM UTC 24 Aug 25 02:29:22 PM UTC 24 6470280300 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma_reset.1060673223 Aug 25 02:13:08 PM UTC 24 Aug 25 02:29:23 PM UTC 24 180179885100 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mp_regions.2580663570 Aug 25 02:21:38 PM UTC 24 Aug 25 02:29:29 PM UTC 24 55052642500 ps
T458 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr_slow_flash.3220396957 Aug 25 02:24:24 PM UTC 24 Aug 25 02:29:35 PM UTC 24 20937688100 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_erase_suspend.785246370 Aug 25 02:21:29 PM UTC 24 Aug 25 02:29:40 PM UTC 24 2964362800 ps
T459 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_address.226027310 Aug 25 02:28:02 PM UTC 24 Aug 25 02:29:50 PM UTC 24 590557700 ps
T460 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_counter.3455840067 Aug 25 02:27:55 PM UTC 24 Aug 25 02:29:51 PM UTC 24 2916104400 ps
T461 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro.34846309 Aug 25 02:27:32 PM UTC 24 Aug 25 02:29:53 PM UTC 24 2698586800 ps
T462 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_prog_reset.3600120104 Aug 25 02:29:19 PM UTC 24 Aug 25 02:29:57 PM UTC 24 583637800 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rd_buff_evict.1860745032 Aug 25 02:26:22 PM UTC 24 Aug 25 02:29:58 PM UTC 24 1503568600 ps
T463 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_sec_otp.3561119157 Aug 25 02:26:24 PM UTC 24 Aug 25 02:29:58 PM UTC 24 15969092400 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma_reset.527626293 Aug 25 02:12:10 PM UTC 24 Aug 25 02:30:03 PM UTC 24 40119257400 ps
T111 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_disable.377361270 Aug 25 02:29:31 PM UTC 24 Aug 25 02:30:07 PM UTC 24 12114600 ps
T354 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict_all_en.1388220146 Aug 25 02:29:23 PM UTC 24 Aug 25 02:30:15 PM UTC 24 73634800 ps
T464 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_otp_reset.4080248772 Aug 25 02:26:40 PM UTC 24 Aug 25 02:30:18 PM UTC 24 151756000 ps
T112 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_connect.4233410976 Aug 25 02:29:52 PM UTC 24 Aug 25 02:30:21 PM UTC 24 134873200 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_ack_consistency.1905990695 Aug 25 02:29:59 PM UTC 24 Aug 25 02:30:23 PM UTC 24 15480600 ps
T362 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_re_evict.3158534535 Aug 25 02:29:24 PM UTC 24 Aug 25 02:30:28 PM UTC 24 274475700 ps
T465 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_serr.2508336764 Aug 25 02:27:48 PM UTC 24 Aug 25 02:30:29 PM UTC 24 2202347500 ps
T466 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_host_grant_err.4129953380 Aug 25 02:29:58 PM UTC 24 Aug 25 02:30:29 PM UTC 24 14946300 ps
T467 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_wo.3024038761 Aug 25 02:27:30 PM UTC 24 Aug 25 02:30:29 PM UTC 24 7079571600 ps
T468 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr.1956883119 Aug 25 02:28:42 PM UTC 24 Aug 25 02:30:30 PM UTC 24 7017084800 ps
T469 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_config_regwen.4004980836 Aug 25 02:30:04 PM UTC 24 Aug 25 02:30:31 PM UTC 24 35631800 ps
T470 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_lcmgr_intg.2245615409 Aug 25 02:30:07 PM UTC 24 Aug 25 02:30:31 PM UTC 24 26225700 ps
T471 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke.4260158621 Aug 25 02:26:12 PM UTC 24 Aug 25 02:30:37 PM UTC 24 224514200 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb_redun.2334670902 Aug 25 02:29:58 PM UTC 24 Aug 25 02:30:38 PM UTC 24 857297800 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_read_seed_err.513607685 Aug 25 02:30:15 PM UTC 24 Aug 25 02:30:41 PM UTC 24 21079200 ps
T97 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rand_ops.4089654395 Aug 25 02:12:09 PM UTC 24 Aug 25 02:30:43 PM UTC 24 104217500 ps
T472 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_alert_test.2277951156 Aug 25 02:30:19 PM UTC 24 Aug 25 02:30:45 PM UTC 24 71534300 ps
T473 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_integrity.3206027780 Aug 25 02:19:01 PM UTC 24 Aug 25 02:30:52 PM UTC 24 6940960700 ps
T474 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fs_sup.3994436326 Aug 25 02:29:54 PM UTC 24 Aug 25 02:30:56 PM UTC 24 594933300 ps
T475 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_derr.2145645637 Aug 25 02:28:12 PM UTC 24 Aug 25 02:31:10 PM UTC 24 2683001800 ps
T476 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_fetch_code.2076043688 Aug 25 02:30:32 PM UTC 24 Aug 25 02:31:10 PM UTC 24 489738200 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_info_access.2992032662 Aug 25 02:29:42 PM UTC 24 Aug 25 02:31:14 PM UTC 24 1628836200 ps
T315 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_oversize_error.4211323389 Aug 25 02:28:29 PM UTC 24 Aug 25 02:31:48 PM UTC 24 4141349700 ps
T477 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_invalid_op.1048092276 Aug 25 02:30:38 PM UTC 24 Aug 25 02:32:04 PM UTC 24 1706768300 ps
T478 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_serr.2675575724 Aug 25 02:27:52 PM UTC 24 Aug 25 02:32:16 PM UTC 24 1526319100 ps
T114 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.3346942999 Aug 25 02:30:16 PM UTC 24 Aug 25 02:32:44 PM UTC 24 10032376000 ps
T479 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_derr.2222287205 Aug 25 02:28:15 PM UTC 24 Aug 25 02:33:01 PM UTC 24 11951902800 ps
T342 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd.119378479 Aug 25 02:28:40 PM UTC 24 Aug 25 02:33:14 PM UTC 24 5956466100 ps
T480 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro.3366865056 Aug 25 02:30:44 PM UTC 24 Aug 25 02:33:19 PM UTC 24 2488988600 ps
T481 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_stress_all.3994541648 Aug 25 02:29:51 PM UTC 24 Aug 25 02:33:30 PM UTC 24 846429200 ps
T482 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr.1451533327 Aug 25 02:31:48 PM UTC 24 Aug 25 02:33:31 PM UTC 24 5101124200 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_serr.359976658 Aug 25 02:30:53 PM UTC 24 Aug 25 02:33:31 PM UTC 24 1417423100 ps
T430 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_derr_detect.2185414316 Aug 25 02:28:27 PM UTC 24 Aug 25 02:33:39 PM UTC 24 1584966000 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict.814830710 Aug 25 02:33:02 PM UTC 24 Aug 25 02:33:42 PM UTC 24 71938900 ps
T483 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb.4100720020 Aug 25 02:26:23 PM UTC 24 Aug 25 02:33:50 PM UTC 24 4323475800 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_mp_regions.2836027622 Aug 25 02:30:31 PM UTC 24 Aug 25 02:33:59 PM UTC 24 10885314100 ps
T484 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_smoke.4249926296 Aug 25 02:30:22 PM UTC 24 Aug 25 02:34:00 PM UTC 24 19763600 ps
T485 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_connect.461022433 Aug 25 02:33:33 PM UTC 24 Aug 25 02:34:03 PM UTC 24 14358100 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_read_seed_err.3990019804 Aug 25 02:33:43 PM UTC 24 Aug 25 02:34:07 PM UTC 24 50908500 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%