Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	250106	1		T1	1		T2	14		T3	20
auto[FlashEraseBank]	275511	1		T4	3		T5	5		T8	11

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	268802	1		T3	20		T5	2		T16	20
auto[FlashOpProgram]	236852	1		T1	1		T2	14		T4	6
auto[FlashOpErase]	15963	1		T5	2		T6	1		T9	1
auto[FlashOpInvalid]	4000	1		T28	200		T92	200		T168	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	268802	1		T3	20		T5	2		T16	20
op[FlashOpProgram]	236852	1		T1	1		T2	14		T4	6
op[FlashOpErase]	15963	1		T5	2		T6	1		T9	1
read_erase_read	492	1		T27	11		T29	2		T94	17
read_prog_read	653	1		T34	3		T24	2		T51	2

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	383071	1		T1	1		T2	14		T3	20
auto[FlashPartInfo]	139089	1		T4	3		T11	1		T34	11
auto[FlashPartInfo1]	835	1		T52	2		T84	1		T74	1
auto[FlashPartInfo2]	2622	1		T27	1		T36	11		T37	2

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	198721	1		T3	20		T5	2		T16	20
auto[FlashPartData]	auto[FlashOpProgram]	177169	1		T1	1		T2	14		T4	3
auto[FlashPartData]	auto[FlashOpErase]	3259	1		T5	2		T6	1		T9	1
auto[FlashPartData]	auto[FlashOpInvalid]	3922	1		T28	190		T92	194		T168	194
auto[FlashPartInfo]	auto[FlashOpRead]	67829	1		T34	10		T27	14		T19	1
auto[FlashPartInfo]	auto[FlashOpProgram]	58527	1		T4	3		T11	1		T34	1
auto[FlashPartInfo]	auto[FlashOpErase]	12663	1		T27	5		T28	5		T42	11
auto[FlashPartInfo]	auto[FlashOpInvalid]	70	1		T28	10		T92	6		T168	6
auto[FlashPartInfo1]	auto[FlashOpRead]	666	1		T52	2		T84	1		T74	1
auto[FlashPartInfo1]	auto[FlashOpProgram]	162	1		T154	1		T177	1		T433	32
auto[FlashPartInfo1]	auto[FlashOpErase]	5	1		T96	1		T154	1		T156	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	2	1		T154	2		-	-		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1586	1		T27	1		T36	6		T51	1
auto[FlashPartInfo2]	auto[FlashOpProgram]	994	1		T36	5		T37	2		T51	2
auto[FlashPartInfo2]	auto[FlashOpErase]	36	1		T94	5		T169	3		T170	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	6	1		T170	2		T434	2		T435	2