Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.24	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	2	30	93.75

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	2	30	93.75	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31941	1		T9	4		T24	12		T28	400
auto[1]	72	1		T27	13		T36	4		T165	4
auto[2]	45	1		T27	5		T69	12		T90	4
auto[3]	237	1		T34	1		T38	1		T94	10

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	8078	1		T9	1		T34	1		T27	2
evic_idx[1]	8081	1		T9	1		T27	5		T36	1
evic_idx[2]	8074	1		T9	1		T27	7		T36	1
evic_idx[3]	8062	1		T9	1		T27	4		T36	1

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	31541	1		T9	4		T27	18		T28	400
evic_op[2]	310	1		T34	1		T36	4		T24	12

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	2	30	93.75	2

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[0]]	[evic_op[2]]	[auto[2]]	0	1	1
[evic_idx[3]]	[evic_op[2]]	[auto[2]]	0	1	1

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7818	1		T9	1		T28	100		T58	1
evic_idx[0]	evic_op[1]	auto[1]	12	1		T27	2		T169	2		T313	1
evic_idx[0]	evic_op[1]	auto[2]	3	1		T231	3		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	56	1		T94	2		T169	5		T313	2
evic_idx[0]	evic_op[2]	auto[0]	63	1		T24	3		T29	4		T236	9
evic_idx[0]	evic_op[2]	auto[1]	5	1		T36	1		T165	1		T349	1
evic_idx[0]	evic_op[2]	auto[3]	10	1		T34	1		T350	1		T351	1
evic_idx[1]	evic_op[1]	auto[0]	7818	1		T9	1		T28	100		T58	1
evic_idx[1]	evic_op[1]	auto[1]	13	1		T27	3		T169	2		T313	1
evic_idx[1]	evic_op[1]	auto[2]	6	1		T27	2		T352	1		T231	2
evic_idx[1]	evic_op[1]	auto[3]	52	1		T94	3		T169	3		T313	3
evic_idx[1]	evic_op[2]	auto[0]	63	1		T24	3		T29	4		T236	9
evic_idx[1]	evic_op[2]	auto[1]	7	1		T36	1		T165	1		T349	2
evic_idx[1]	evic_op[2]	auto[2]	1	1		T353	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[3]	10	1		T354	1		T355	1		T356	1
evic_idx[2]	evic_op[1]	auto[0]	7818	1		T9	1		T28	100		T58	1
evic_idx[2]	evic_op[1]	auto[1]	14	1		T27	5		T169	2		T313	2
evic_idx[2]	evic_op[1]	auto[2]	6	1		T27	2		T352	1		T231	3
evic_idx[2]	evic_op[1]	auto[3]	48	1		T94	3		T169	4		T313	5
evic_idx[2]	evic_op[2]	auto[0]	61	1		T24	3		T29	4		T236	9
evic_idx[2]	evic_op[2]	auto[1]	6	1		T36	1		T165	1		T290	1
evic_idx[2]	evic_op[2]	auto[2]	2	1		T357	1		T358	1		-	-
evic_idx[2]	evic_op[2]	auto[3]	8	1		T359	1		T360	1		T361	1
evic_idx[3]	evic_op[1]	auto[0]	7820	1		T9	1		T28	100		T58	1
evic_idx[3]	evic_op[1]	auto[1]	10	1		T27	3		T169	2		T362	1
evic_idx[3]	evic_op[1]	auto[2]	3	1		T27	1		T231	2		-	-
evic_idx[3]	evic_op[1]	auto[3]	44	1		T94	2		T169	4		T313	4
evic_idx[3]	evic_op[2]	auto[0]	60	1		T24	3		T29	4		T236	9
evic_idx[3]	evic_op[2]	auto[1]	5	1		T36	1		T165	1		T290	1
evic_idx[3]	evic_op[2]	auto[3]	9	1		T38	1		T363	1		T364	1