Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	5	0	5	100.00
Crosses	6	0	6	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
instr_type_cp	3	0	3	100.00	100	1	1	0
key_cp	2	0	2	100.00	100	1	1	2

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::fetch_code_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
key_instr_cross	6	0	6	100.00	100	1	1	0

Summary for Variable instr_type_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for instr_type_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
others	6471	1		T8	97		T56	133		T62	174
instr_types[0]	7665	1		T8	262		T56	221		T62	276
instr_types[1]	4142304	1		T5	1		T8	327		T6	16

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Summary for Variable key_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4154203	1		T5	1		T8	480		T6	16
auto[1]	2237	1		T8	206		T56	198		T62	293

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Summary for Cross key_instr_cross

Samples crossed: key_cp instr_type_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	6	0	6	100.00

Automatically Generated Cross Bins for key_instr_cross

Bins

key_cp	instr_type_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	others	5980	1		T8	47		T56	86		T62	125
auto[0]	instr_types[0]	6654	1		T8	185		T56	145		T62	139
auto[0]	instr_types[1]	4141569	1		T5	1		T8	248		T6	16
auto[1]	others	491	1		T8	50		T56	47		T62	49
auto[1]	instr_types[0]	1011	1		T8	77		T56	76		T62	137
auto[1]	instr_types[1]	735	1		T8	79		T56	75		T62	107