Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	31499	1		T333	2435		T334	14561		T335	14503
rd_lvl[2]	62840	1		T79	12736		T336	1277		T333	2405
rd_lvl[3]	8690	1		T337	808		T336	976		T333	1535
rd_lvl[4]	33801	1		T337	2383		T338	5642		T339	5240
rd_lvl[5]	17608	1		T337	68		T340	2399		T338	1066
rd_lvl[6]	20368	1		T337	1326		T340	1225		T336	328
rd_lvl[7]	7844	1		T337	1707		T341	901		T336	496
rd_lvl[8]	18407	1		T342	2624		T337	943		T341	491
rd_lvl[9]	8343	1		T46	193		T342	634		T343	388
rd_lvl[10]	8952	1		T49	1103		T46	43		T343	682
rd_lvl[11]	2198	1		T49	420		T50	418		T46	1
rd_lvl[12]	6797	1		T50	1233		T46	24		T344	1205
rd_lvl[13]	2518	1		T344	271		T47	404		T336	24
rd_lvl[14]	8534	1		T43	1373		T47	1290		T345	1243
rd_lvl[15]	4172	1		T43	301		T346	483		T345	420