Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	367710	1		T1	1		T2	2		T3	2
all_pins[1]	367710	1		T1	1		T2	2		T3	2
all_pins[2]	367710	1		T1	1		T2	2		T3	2
all_pins[3]	367710	1		T1	1		T2	2		T3	2
all_pins[4]	367710	1		T1	1		T2	2		T3	2
all_pins[5]	367710	1		T1	1		T2	2		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1836783	1		T1	6		T2	12		T3	12
values[0x1]	369477	1		T37	1399		T40	1613		T43	3348
transitions[0x0=>0x1]	332627	1		T37	1399		T40	1613		T43	3348
transitions[0x1=>0x0]	332613	1		T37	1399		T40	1613		T43	3348

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	367569	1		T1	1		T2	2		T3	2
all_pins[0]	values[0x1]	141	1		T267	5		T276	3		T327	1
all_pins[0]	transitions[0x0=>0x1]	70	1		T327	1		T328	2		T329	1
all_pins[0]	transitions[0x1=>0x0]	73	1		T276	1		T329	2		T331	4
all_pins[1]	values[0x0]	367566	1		T1	1		T2	2		T3	2
all_pins[1]	values[0x1]	144	1		T267	5		T276	4		T328	2
all_pins[1]	transitions[0x0=>0x1]	127	1		T267	5		T276	4		T328	1
all_pins[1]	transitions[0x1=>0x0]	2476	1		T346	1234		T365	916		T366	86
all_pins[2]	values[0x0]	365217	1		T1	1		T2	2		T3	2
all_pins[2]	values[0x1]	2493	1		T346	1234		T365	916		T366	86
all_pins[2]	transitions[0x0=>0x1]	34	1		T328	1		T367	1		T368	1
all_pins[2]	transitions[0x1=>0x0]	242692	1		T43	1674		T49	1523		T50	1651
all_pins[3]	values[0x0]	122559	1		T1	1		T2	2		T3	2
all_pins[3]	values[0x1]	245151	1		T43	1674		T49	1523		T50	1651
all_pins[3]	transitions[0x0=>0x1]	210901	1		T43	1674		T49	1523		T50	1651
all_pins[3]	transitions[0x1=>0x0]	87239	1		T37	1399		T40	1613		T43	1674
all_pins[4]	values[0x0]	246221	1		T1	1		T2	2		T3	2
all_pins[4]	values[0x1]	121489	1		T37	1399		T40	1613		T43	1674
all_pins[4]	transitions[0x0=>0x1]	121472	1		T37	1399		T40	1613		T43	1674
all_pins[4]	transitions[0x1=>0x0]	42	1		T267	2		T330	2		T331	2
all_pins[5]	values[0x0]	367651	1		T1	1		T2	2		T3	2
all_pins[5]	values[0x1]	59	1		T267	2		T327	1		T330	2
all_pins[5]	transitions[0x0=>0x1]	23	1		T331	2		T369	1		T370	1
all_pins[5]	transitions[0x1=>0x0]	91	1		T267	2		T276	2		T327	1