Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	266	1		T267	4		T276	4		T327	4
all_values[1]	266	1		T267	4		T276	4		T327	4
all_values[2]	266	1		T267	4		T276	4		T327	4
all_values[3]	266	1		T267	4		T276	4		T327	4
all_values[4]	266	1		T267	4		T276	4		T327	4
all_values[5]	266	1		T267	4		T276	4		T327	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	901	1		T267	11		T276	18		T327	17
auto[1]	695	1		T267	13		T276	6		T327	7

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	512	1		T267	11		T276	6		T327	5
auto[1]	1084	1		T267	13		T276	18		T327	19

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	957	1		T267	18		T276	13		T327	13
auto[1]	639	1		T267	6		T276	11		T327	11

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	92	1		T276	1		T327	3		T328	2
all_values[0]	auto[0]	auto[1]	auto[1]	77	1		T267	3		T276	1		T328	3
all_values[0]	auto[1]	auto[0]	auto[1]	58	1		T276	2		T328	1		T329	1
all_values[0]	auto[1]	auto[1]	auto[1]	39	1		T267	1		T327	1		T328	1
all_values[1]	auto[0]	auto[0]	auto[1]	85	1		T327	3		T328	4		T329	1
all_values[1]	auto[0]	auto[1]	auto[1]	75	1		T267	3		T276	3		T329	1
all_values[1]	auto[1]	auto[0]	auto[1]	60	1		T276	1		T327	1		T328	1
all_values[1]	auto[1]	auto[1]	auto[1]	46	1		T267	1		T328	2		T330	2
all_values[2]	auto[0]	auto[0]	auto[0]	99	1		T267	2		T276	2		T327	1
all_values[2]	auto[0]	auto[1]	auto[0]	65	1		T327	1		T328	3		T330	2
all_values[2]	auto[1]	auto[0]	auto[1]	52	1		T267	1		T276	2		T327	1
all_values[2]	auto[1]	auto[1]	auto[1]	50	1		T267	1		T327	1		T328	2
all_values[3]	auto[0]	auto[0]	auto[0]	82	1		T267	3		T276	2		T327	1
all_values[3]	auto[0]	auto[1]	auto[0]	77	1		T267	1		T328	3		T330	5
all_values[3]	auto[1]	auto[0]	auto[1]	60	1		T276	2		T327	1		T328	1
all_values[3]	auto[1]	auto[1]	auto[1]	47	1		T327	2		T328	2		T330	2
all_values[4]	auto[0]	auto[0]	auto[0]	59	1		T267	2		T276	1		T327	2
all_values[4]	auto[0]	auto[0]	auto[1]	34	1		T328	1		T331	1		T332	1
all_values[4]	auto[0]	auto[1]	auto[0]	37	1		T267	2		T329	1		T330	2
all_values[4]	auto[0]	auto[1]	auto[1]	24	1		T276	1		T328	1		T329	1
all_values[4]	auto[1]	auto[0]	auto[1]	60	1		T276	2		T327	1		T328	3
all_values[4]	auto[1]	auto[1]	auto[1]	52	1		T327	1		T329	2		T330	1
all_values[5]	auto[0]	auto[0]	auto[0]	58	1		T267	1		T328	3		T329	2
all_values[5]	auto[0]	auto[0]	auto[1]	31	1		T276	1		T327	1		T328	1
all_values[5]	auto[0]	auto[1]	auto[0]	35	1		T276	1		T328	1		T329	2
all_values[5]	auto[0]	auto[1]	auto[1]	27	1		T267	1		T327	1		T331	1
all_values[5]	auto[1]	auto[0]	auto[1]	71	1		T267	2		T276	2		T327	2
all_values[5]	auto[1]	auto[1]	auto[1]	44	1		T328	1		T330	3		T331	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal