Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	349136	1		T1	2		T2	1		T3	2
all_values[1]	349136	1		T1	2		T2	1		T3	2
all_values[2]	349136	1		T1	2		T2	1		T3	2
all_values[3]	349136	1		T1	2		T2	1		T3	2
all_values[4]	349136	1		T1	2		T2	1		T3	2
all_values[5]	349136	1		T1	2		T2	1		T3	2

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	704638	1		T1	12		T2	6		T3	12
auto[1]	1390178	1		T26	6096		T33	12592		T29	6024

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1024784	1		T1	7		T2	4		T3	7
auto[1]	1070032	1		T1	5		T2	2		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	348982	1		T1	2		T2	1		T3	2
all_values[0]	auto[1]	auto[1]	154	1		T257	3		T330	4		T331	1
all_values[1]	auto[0]	auto[1]	348991	1		T1	2		T2	1		T3	2
all_values[1]	auto[1]	auto[1]	145	1		T257	4		T258	2		T330	7
all_values[2]	auto[0]	auto[0]	1612	1		T1	2		T2	1		T3	2
all_values[2]	auto[0]	auto[1]	52	1		T257	3		T258	1		T330	3
all_values[2]	auto[1]	auto[0]	347421	1		T26	1524		T33	3148		T29	1506
all_values[2]	auto[1]	auto[1]	51	1		T258	1		T330	1		T331	2
all_values[3]	auto[0]	auto[0]	1602	1		T1	2		T2	1		T3	2
all_values[3]	auto[0]	auto[1]	66	1		T257	2		T258	1		T330	3
all_values[3]	auto[1]	auto[0]	69162	1		T26	1524		T33	1574		T29	1506
all_values[3]	auto[1]	auto[1]	278306	1		T33	1574		T37	1183		T38	42614
all_values[4]	auto[0]	auto[0]	1133	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	519	1		T1	1		T3	1		T13	1
all_values[4]	auto[1]	auto[0]	254863	1		T26	1		T33	1574		T29	1
all_values[4]	auto[1]	auto[1]	92621	1		T26	1523		T33	1574		T29	1505
all_values[5]	auto[0]	auto[0]	1593	1		T1	2		T2	1		T3	2
all_values[5]	auto[0]	auto[1]	88	1		T14	1		T39	1		T86	1
all_values[5]	auto[1]	auto[0]	347398	1		T26	1524		T33	3148		T29	1506
all_values[5]	auto[1]	auto[1]	57	1		T257	3		T330	3		T331	4