Assertions
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Detail Report for Assertions

Assertions Uncovered:
ASSERTIONS   CATEGORY   SEVERITY   ATTEMPTS   REAL SUCCESSES   FAILURES   INCOMPLETE   SRC   
tb.dut.FpvSecCmEflashReqFifoRptrCheck_A 00375370398000
tb.dut.FpvSecCmEflashReqFifoWptrCheck_A 00375370398000
tb.dut.FpvSecCmEflashRspFifoRptrCheck_A 00375370398000
tb.dut.FpvSecCmEflashRspFifoWptrCheck_A 00375370398000
tb.dut.FpvSecCmEflashSramReqFifoRptrCheck_A 00375370398000
tb.dut.FpvSecCmEflashSramReqFifoWptrCheck_A 00375370398000
tb.dut.FpvSecCmRdReqFifoRptrCheck_A 00375370398000
tb.dut.FpvSecCmRdReqFifoWptrCheck_A 00375370398000
tb.dut.FpvSecCmRdSramReqFifoRptrCheck_A 00375370398000
tb.dut.FpvSecCmRdSramReqFifoWptrCheck_A 00375370398000
tb.dut.PrimRspPayLoad_A 00375370398000
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.LockArbDecision_A 00375370398000
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M 00375370398000
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.RoundRobin_A 00375370398001047
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.LockArbDecision_A 00375370398000
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqStaysHighUntilGranted0_M 00375370398000
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.RoundRobin_A 00375370398001047
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A 00375370398001047
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A 00375370398001047
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A 00375370398001047
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A 00375370398001047
tb.dut.u_prog_tl_gate.OutStandingOvfl_A 00375370398000
tb.dut.u_tl_gate.OutStandingOvfl_A 00375370398000
tb.dut.u_to_prog_fifo.rvalidHighReqFifoEmpty 00375370398000
tb.dut.u_to_prog_fifo.rvalidHighWhenRspFifoFull 00375370398000
tb.dut.u_to_prog_fifo.u_rspfifo.DataKnown_A 00375370398000
tb.dut.u_to_prog_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00375370398000
tb.dut.u_to_prog_fifo.u_sramreqfifo.DataKnown_A 00375370398000
tb.dut.u_to_prog_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00375370398000

Assertions Success:
ASSERTIONS   CATEGORY   SEVERITY   ATTEMPTS   REAL SUCCESSES   FAILURES   INCOMPLETE   SRC   
tb.dut.FifoDepthCheck_A 001052105200
tb.dut.FlashAddrKnown_A 0037537039826166575600
tb.dut.FlashAddrKnown_AKnownEnable 0037537039837458303800
tb.dut.FlashKnownO_A 0037537039837458303800
tb.dut.FlashProgKnown_A 0037537039815911963900
tb.dut.FlashProgKnown_AKnownEnable 0037537039837458303800
tb.dut.FpvSecCmAddrCntAlertCheck_A 003753703985000
tb.dut.FpvSecCmArbFsmCheck_A 003753703985000
tb.dut.FpvSecCmLcCtrlFsmCheck_A 003753703985000
tb.dut.FpvSecCmLcCtrlRmaFsmCheck_A 003753703985000
tb.dut.FpvSecCmPageCntAlertCheck_A 003753703985000
tb.dut.FpvSecCmProgCnt_A 003753703985000
tb.dut.FpvSecCmRdCnt_A 003753703985000
tb.dut.FpvSecCmRdRspFifoRptrCheck_A 003753703985000
tb.dut.FpvSecCmRdRspFifoWptrCheck_A 003753703985000
tb.dut.FpvSecCmRegWeOnehotCheck_A 003753703985000
tb.dut.FpvSecCmSeedCntAlertCheck_A 003753703985000
tb.dut.FpvSecCmTlLcGateFsm_A 003753703985000
tb.dut.FpvSecCmTlProgLcGateFsm_A 003753703985000
tb.dut.FpvSecCmWipeIdx_A 003753703985000
tb.dut.FpvSecCmWordCntAlertCheck_A 003753703985000
tb.dut.IntrErrO_A 0037537039837458303800
tb.dut.IntrOpDoneKnownO_A 0037537039837458303800
tb.dut.IntrProgEmptyKnownO_A 0037537039837458303800
tb.dut.IntrProgLvlKnownO_A 0037537039837458303800
tb.dut.IntrProgRdFullKnownO_A 0037537039837458303800
tb.dut.IntrRdLvlKnownO_A 0037537039837458303800
tb.dut.MemRspPayLoad_A 00375370398518125700
tb.dut.MemRspPayLoad_AKnownEnable 0037537039837458303800
tb.dut.MemTlAReadyKnownO_A 0037537039837458303800
tb.dut.MemTlDValidKnownO_A 0037537039837458303800
tb.dut.PrimRspPayLoad_AKnownEnable 0037537039837458303800
tb.dut.PrimTlAReadyKnownO_A 0037537039837458303800
tb.dut.PrimTlDValidKnownO_A 0037537039837458303800
tb.dut.RspPayLoad_A 003752037684260628400
tb.dut.RspPayLoad_AKnownEnable 0037537039837458303800
tb.dut.TdoEnIsOne_A 0037537039837458303800
tb.dut.TdoKnown_A 0037537039837458303800
tb.dut.TlAReadyKnownO_A 0037537039837458303800
tb.dut.TlDValidKnownO_A 0037537039837458303800
tb.dut.flash_ctrl_core_csr_assert.TlulOOBAddrErr_A 00378349590353100
tb.dut.flash_ctrl_core_csr_assert.addr_rd_A 00378349590244300
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_0_rd_A 00378349590384600
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_1_rd_A 00378349590379700
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_2_rd_A 00378349590363300
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_3_rd_A 00378349590378200
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_4_rd_A 00378349590408600
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_5_rd_A 00378349590339000
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_6_rd_A 00378349590368700
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_7_rd_A 00378349590375800
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_8_rd_A 00378349590362400
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_page_cfg_9_rd_A 00378349590357900
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_0_rd_A 00378349590215900
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_1_rd_A 00378349590201600
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_2_rd_A 00378349590211000
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_3_rd_A 00378349590212100
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_4_rd_A 00378349590201300
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_5_rd_A 00378349590233500
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_6_rd_A 00378349590210700
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_7_rd_A 00378349590253100
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_8_rd_A 00378349590230600
tb.dut.flash_ctrl_core_csr_assert.bank0_info0_regwen_9_rd_A 00378349590184500
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_page_cfg_rd_A 00378349590346400
tb.dut.flash_ctrl_core_csr_assert.bank0_info1_regwen_rd_A 00378349590228700
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_0_rd_A 00378349590385400
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_page_cfg_1_rd_A 00378349590377600
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_0_rd_A 00378349590239300
tb.dut.flash_ctrl_core_csr_assert.bank0_info2_regwen_1_rd_A 00378349590241400
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_0_rd_A 00378349590389200
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_1_rd_A 00378349590390800
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_2_rd_A 00378349590394300
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_3_rd_A 00378349590363300
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_4_rd_A 00378349590418100
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_5_rd_A 00378349590375500
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_6_rd_A 00378349590383500
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_7_rd_A 00378349590381500
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_8_rd_A 00378349590371800
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_page_cfg_9_rd_A 00378349590372900
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_0_rd_A 00378349590217700
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_1_rd_A 00378349590225200
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_2_rd_A 00378349590233800
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_3_rd_A 00378349590227200
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_4_rd_A 00378349590237100
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_5_rd_A 00378349590215800
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_6_rd_A 00378349590234600
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_7_rd_A 00378349590217500
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_8_rd_A 00378349590175700
tb.dut.flash_ctrl_core_csr_assert.bank1_info0_regwen_9_rd_A 00378349590254600
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_page_cfg_rd_A 00378349590402800
tb.dut.flash_ctrl_core_csr_assert.bank1_info1_regwen_rd_A 00378349590188000
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_0_rd_A 00378349590366200
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_page_cfg_1_rd_A 00378349590385900
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_0_rd_A 00378349590244100
tb.dut.flash_ctrl_core_csr_assert.bank1_info2_regwen_1_rd_A 00378349590231800
tb.dut.flash_ctrl_core_csr_assert.bank_cfg_regwen_rd_A 00378349590248800
tb.dut.flash_ctrl_core_csr_assert.default_region_rd_A 00378349590373300
tb.dut.flash_ctrl_core_csr_assert.exec_rd_A 00378349590220200
tb.dut.flash_ctrl_core_csr_assert.fifo_lvl_rd_A 00378349590267300
tb.dut.flash_ctrl_core_csr_assert.fifo_rst_rd_A 00378349590236200
tb.dut.flash_ctrl_core_csr_assert.hw_info_cfg_override_rd_A 00378349590225500
tb.dut.flash_ctrl_core_csr_assert.intr_enable_rd_A 00378349590355200
tb.dut.flash_ctrl_core_csr_assert.mp_region_0_rd_A 00378349590229000
tb.dut.flash_ctrl_core_csr_assert.mp_region_1_rd_A 00378349590202400
tb.dut.flash_ctrl_core_csr_assert.mp_region_2_rd_A 00378349590262000
tb.dut.flash_ctrl_core_csr_assert.mp_region_3_rd_A 00378349590238300
tb.dut.flash_ctrl_core_csr_assert.mp_region_4_rd_A 00378349590238600
tb.dut.flash_ctrl_core_csr_assert.mp_region_5_rd_A 00378349590242400
tb.dut.flash_ctrl_core_csr_assert.mp_region_6_rd_A 00378349590229800
tb.dut.flash_ctrl_core_csr_assert.mp_region_7_rd_A 00378349590211700
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_0_rd_A 00378349590392300
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_1_rd_A 00378349590405100
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_2_rd_A 00378349590370600
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_3_rd_A 00378349590393200
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_4_rd_A 00378349590390000
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_5_rd_A 00378349590397800
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_6_rd_A 00378349590402500
tb.dut.flash_ctrl_core_csr_assert.mp_region_cfg_7_rd_A 00378349590375500
tb.dut.flash_ctrl_core_csr_assert.phy_alert_cfg_rd_A 0037834959072400
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_0_rd_A 00378349590247000
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_1_rd_A 00378349590240100
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_2_rd_A 00378349590243900
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_3_rd_A 00378349590205000
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_4_rd_A 00378349590223300
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_5_rd_A 00378349590246600
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_6_rd_A 00378349590203500
tb.dut.flash_ctrl_core_csr_assert.region_cfg_regwen_7_rd_A 00378349590236600
tb.dut.flash_ctrl_core_csr_assert.scratch_rd_A 00378349590191500
tb.dut.gen_phy_assertions[0].FpvSecCmPhyFsmCheck_A 003753703985000
tb.dut.gen_phy_assertions[0].FpvSecCmPhyProgFsmCheck_A 003753703985000
tb.dut.gen_phy_assertions[1].FpvSecCmPhyFsmCheck_A 003753703985000
tb.dut.gen_phy_assertions[1].FpvSecCmPhyProgFsmCheck_A 003753703985000
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyHostCnt_A 003753703985000
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoRPtr_A 003753703985000
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoWPtr_A 003753703985000
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoRPtr_A 003753703985000
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoWPtr_A 003753703985000
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoRPtr_A 003753703985000
tb.dut.gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoWPtr_A 003753703985000
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyHostCnt_A 003753703985000
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoRPtr_A 003753703985000
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoWPtr_A 003753703985000
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoRPtr_A 003753703985000
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoWPtr_A 003753703985000
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoRPtr_A 003753703985000
tb.dut.gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoWPtr_A 003753703985000
tb.dut.gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A 003753703982600
tb.dut.tlul_assert_device.aKnown_A 003783495513342790100
tb.dut.tlul_assert_device.aKnown_AKnownEnable 0037834955137747744200
tb.dut.tlul_assert_device.aReadyKnown_A 0037834955137747744200
tb.dut.tlul_assert_device.dKnown_A 003783495514358425600
tb.dut.tlul_assert_device.dKnown_AKnownEnable 0037834955137747744200
tb.dut.tlul_assert_device.dReadyKnown_A 0037834955137747744200
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A 001262126200
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A 001262126200
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tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A 001262126200
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tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A 001262126200
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total1020010
Category 01020010


Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total1020010
Severity 01020010


Summary for Assertions
NUMBERPERCENT
Total Number1020100.00
Uncovered292.84
Success99197.16
Failure00.00
Incomplete151.47
Without Attempts00.00


Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered220.00
All Matches880.00
First Matches880.00