Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	224841	1		T1	4		T3	30		T12	329
auto[FlashEraseBank]	256844	1		T3	10		T13	2		T18	2

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	243919	1		T1	2		T3	40		T12	173
auto[FlashOpProgram]	219066	1		T1	1		T12	78		T13	4
auto[FlashOpErase]	14700	1		T1	1		T12	78		T16	100
auto[FlashOpInvalid]	4000	1		T16	200		T145	200		T147	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	243919	1		T1	2		T3	40		T12	173
op[FlashOpProgram]	219066	1		T1	1		T12	78		T13	4
op[FlashOpErase]	14700	1		T1	1		T12	78		T16	100
read_erase_read	595	1		T23	2		T28	15		T31	2
read_prog_read	865	1		T13	3		T23	1		T63	2

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	346032	1		T1	4		T3	40		T13	8
auto[FlashPartInfo]	131409	1		T12	329		T16	12		T14	106
auto[FlashPartInfo1]	747	1		T14	1		T50	1		T39	2
auto[FlashPartInfo2]	3497	1		T14	5		T65	13		T63	11

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	176199	1		T1	2		T3	40		T13	4
auto[FlashPartData]	auto[FlashOpProgram]	162360	1		T1	1		T13	4		T16	98
auto[FlashPartData]	auto[FlashOpErase]	3567	1		T1	1		T16	98		T20	41
auto[FlashPartData]	auto[FlashOpInvalid]	3906	1		T16	196		T145	194		T147	192
auto[FlashPartInfo]	auto[FlashOpRead]	65224	1		T12	173		T16	4		T14	61
auto[FlashPartInfo]	auto[FlashOpProgram]	55025	1		T12	78		T16	2		T14	45
auto[FlashPartInfo]	auto[FlashOpErase]	11080	1		T12	78		T16	2		T28	14
auto[FlashPartInfo]	auto[FlashOpInvalid]	80	1		T16	4		T145	6		T147	8
auto[FlashPartInfo1]	auto[FlashOpRead]	574	1		T14	1		T50	1		T39	2
auto[FlashPartInfo1]	auto[FlashOpProgram]	163	1		T128	32		T129	32		T153	1
auto[FlashPartInfo1]	auto[FlashOpErase]	6	1		T411	1		T153	1		T412	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T153	2		T412	2		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1922	1		T14	3		T63	4		T50	3
auto[FlashPartInfo2]	auto[FlashOpProgram]	1518	1		T14	2		T65	13		T63	7
auto[FlashPartInfo2]	auto[FlashOpErase]	47	1		T159	4		T146	2		T413	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	10	1		T160	2		T414	2		T415	4